cpuvar.h revision 1.7
1 /* $NetBSD: cpuvar.h,v 1.7 2011/06/14 22:36:12 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _POWERPC_BOOKE_CPUVAR_H_ 38 #define _POWERPC_BOOKE_CPUVAR_H_ 39 40 #include <machine/bus.h> 41 #include <prop/proplib.h> 42 43 struct cpunode_softc { 44 device_t sc_dev; 45 u_int sc_children; 46 }; 47 48 struct cpu_softc { 49 struct cpu_info *cpu_ci; 50 struct evcnt *cpu_evcnt_intrs; 51 bus_space_tag_t cpu_bst; 52 bus_space_tag_t cpu_le_bst; 53 bus_space_handle_t cpu_bsh; 54 bus_addr_t cpu_clock_gtbcr; 55 56 paddr_t cpu_highmem; 57 58 u_int cpu_pcpls[5]; 59 struct evcnt cpu_evcnt_spurious_intr; 60 61 struct evcnt cpu_ev_late_clock; 62 u_long cpu_ticks_per_clock_intr; 63 struct evcnt cpu_ev_exec_trap_sync; 64 }; 65 66 struct cpunode_locators { 67 const char *cnl_name; 68 bus_addr_t cnl_addr; 69 bus_size_t cnl_size; 70 uint8_t cnl_instance; 71 uint8_t cnl_nintr; 72 uint8_t cnl_intrs[4]; 73 uint32_t cnl_flags; 74 uint16_t cnl_ids[6]; 75 }; 76 77 struct cpunode_attach_args { 78 const char *cna_busname; 79 bus_space_tag_t cna_memt; 80 bus_space_tag_t cna_le_memt; 81 bus_dma_tag_t cna_dmat; 82 struct cpunode_locators cna_locs; 83 u_int cna_childmask; 84 }; 85 86 struct mainbus_attach_args { 87 const char *ma_name; 88 bus_space_tag_t ma_memt; 89 bus_space_tag_t ma_le_memt; 90 bus_dma_tag_t ma_dmat; 91 int ma_node; 92 }; 93 94 struct generic_attach_args { 95 const char *ga_name; 96 bus_space_tag_t ga_bst; 97 bus_dma_tag_t ga_dmat; 98 bus_addr_t ga_addr; 99 bus_size_t ga_size; 100 int ga_cs; 101 int ga_irq; 102 }; 103 104 struct tlbmask; 105 106 struct tlb_md_ops { 107 /* 108 * We need mapiodev to be first so we can easily override it in 109 * early boot by doing cpu_md_ops.tlb_md_ops = (const struct 110 * tlb_md_ops *) &<variable containing mapiodev pointer>. 111 */ 112 void *(*md_tlb_mapiodev)(paddr_t, psize_t); 113 void (*md_tlb_unmapiodev)(vaddr_t, vsize_t); 114 void (*md_tlb_set_asid)(uint32_t); 115 uint32_t (*md_tlb_get_asid)(void); 116 void (*md_tlb_invalidate_all)(void); 117 void (*md_tlb_invalidate_globals)(void); 118 void (*md_tlb_invalidate_asids)(uint32_t, uint32_t); 119 void (*md_tlb_invalidate_addr)(vaddr_t, uint32_t); 120 bool (*md_tlb_update_addr)(vaddr_t, uint32_t, uint32_t, bool); 121 void (*md_tlb_read_entry)(size_t, struct tlbmask *); 122 u_int (*md_tlb_record_asids)(u_long *, uint32_t); 123 int (*md_tlb_ioreserve)(vaddr_t, vsize_t, uint32_t); 124 int (*md_tlb_iorelease)(vaddr_t); 125 void (*md_tlb_dump)(void (*)(const char *, ...)); 126 void (*md_tlb_walk)(void *, bool (*)(void *, vaddr_t, uint32_t, 127 uint32_t)); 128 }; 129 130 struct cpu_md_ops { 131 const struct cpunode_locators *md_cpunode_locs; 132 void (*md_cpu_attach)(device_t, u_int); 133 134 void (*md_device_register)(device_t, void *); 135 void (*md_cpu_startup)(void); 136 void (*md_cpu_reset)(void); 137 void (*md_cpunode_attach)(device_t, device_t, void *); 138 139 const struct tlb_md_ops *md_tlb_ops; 140 }; 141 142 143 #ifdef _KERNEL 144 145 static inline register_t 146 wrtee(register_t msr) 147 { 148 register_t old_msr; 149 __asm("mfmsr\t%0" : "=r"(old_msr)); 150 151 if (__builtin_constant_p(msr)) { 152 __asm __volatile("wrteei\t%0" :: "n"((msr & PSL_EE) ? 1 : 0)); 153 } else { 154 __asm __volatile("wrtee\t%0" :: "r"(msr)); 155 } 156 return old_msr; 157 } 158 159 uint32_t ufetch_32(const void *); 160 161 struct trapframe; 162 void booke_sstep(struct trapframe *); 163 164 void booke_fixup_stubs(void); 165 void booke_cpu_startup(const char *); /* model name */ 166 struct powerpc_bus_dma_tag booke_bus_dma_tag; 167 168 extern struct cpu_info cpu_info[]; 169 170 void cpu_evcnt_attach(struct cpu_info *); 171 uint32_t cpu_read_4(bus_size_t); 172 uint8_t cpu_read_1(bus_size_t); 173 void cpu_write_4(bus_size_t, uint32_t); 174 void cpu_write_1(bus_size_t, uint8_t); 175 176 void calc_delayconst(void); 177 178 struct intrsw; 179 void exception_init(const struct intrsw *); 180 181 uint32_t tlb_get_asid(void); 182 void tlb_set_asid(uint32_t); 183 void tlb_invalidate_all(void); 184 void tlb_invalidate_globals(void); 185 void tlb_invalidate_asids(uint32_t, uint32_t); 186 void tlb_invalidate_addr(vaddr_t, uint32_t); 187 bool tlb_update_addr(vaddr_t, uint32_t, uint32_t, bool); 188 u_int tlb_record_asids(u_long *, uint32_t); 189 void tlb_enter_addr(size_t, const struct tlbmask *); 190 void tlb_read_entry(size_t, struct tlbmask *); 191 void *tlb_mapiodev(paddr_t, psize_t); 192 void tlb_unmapiodev(vaddr_t, vsize_t); 193 int tlb_ioreserve(vaddr_t, vsize_t, uint32_t); 194 int tlb_iorelease(vaddr_t); 195 void tlb_dump(void (*)(const char *, ...)); 196 void tlb_walk(void *, bool (*)(void *, vaddr_t, uint32_t, uint32_t)); 197 198 extern struct cpu_md_ops cpu_md_ops; 199 200 void board_info_init(void); 201 void board_info_add_number(const char *, uint64_t); 202 void board_info_add_data(const char *, const void *, size_t); 203 void board_info_add_string(const char *, const char *); 204 void board_info_add_bool(const char *); 205 void board_info_add_object(const char *, void *); 206 uint64_t board_info_get_number(const char *); 207 bool board_info_get_bool(const char *); 208 void *board_info_get_object(const char *); 209 const void * 210 board_info_get_data(const char *, size_t *); 211 212 extern paddr_t msgbuf_paddr; 213 extern prop_dictionary_t board_properties; 214 extern psize_t pmemsize; 215 #endif 216 217 #endif /* !_POWERPC_BOOKE_CPUVAR_H_ */ 218
Indexes created Tue Oct 14 08:09:56 GMT 2025