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spr.h revision 1.1.4.1
      1  1.1.4.1  rmind /*	$NetBSD: spr.h,v 1.1.4.1 2010/05/30 05:17:03 rmind Exp $	*/
      2      1.1   matt /*-
      3      1.1   matt  * Copyright (c) 2010 The NetBSD Foundation, Inc.
      4      1.1   matt  * All rights reserved.
      5      1.1   matt  *
      6      1.1   matt  * This code is derived from software contributed to The NetBSD Foundation
      7      1.1   matt  * by Matt Thomas <matt (at) 3am-software.com>.
      8      1.1   matt  *
      9      1.1   matt  * Redistribution and use in source and binary forms, with or without
     10      1.1   matt  * modification, are permitted provided that the following conditions
     11      1.1   matt  * are met:
     12      1.1   matt  * 1. Redistributions of source code must retain the above copyright
     13      1.1   matt  *    notice, this list of conditions and the following disclaimer.
     14      1.1   matt  * 2. Redistributions in binary form must reproduce the above copyright
     15      1.1   matt  *    notice, this list of conditions and the following disclaimer in the
     16      1.1   matt  *    documentation and/or other materials provided with the distribution.
     17      1.1   matt  *
     18      1.1   matt  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19      1.1   matt  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20      1.1   matt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21      1.1   matt  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22      1.1   matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23      1.1   matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24      1.1   matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25      1.1   matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26      1.1   matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27      1.1   matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28      1.1   matt  * POSSIBILITY OF SUCH DAMAGE.
     29      1.1   matt  */
     30      1.1   matt 
     31      1.1   matt #ifndef _POWERPC_BOOKE_SPR_H_
     32      1.1   matt #define	_POWERPC_BOOKE_SPR_H_
     33      1.1   matt 
     34      1.1   matt #define PVR_MPCe500		  0x8020
     35      1.1   matt #define PVR_MPCe500v2		  0x8021
     36      1.1   matt #define	SVR_MPC8548v1		  0x80310010
     37      1.1   matt #define	SVR_MPC8543v1		  0x80320010
     38      1.1   matt #define	SVR_MPC8548v1plus	  0x80310011
     39      1.1   matt #define	SVR_MPC8543v1plus	  0x80320011
     40      1.1   matt #define	SVR_MPC8548v2		  0x80310020
     41      1.1   matt #define	SVR_MPC8547v2		  0x80310120
     42      1.1   matt #define	SVR_MPC8545v2		  0x80310220
     43      1.1   matt #define	SVR_MPC8543v2		  0x80320020
     44      1.1   matt #define	SVR_MPC8572		  0x80300011
     45      1.1   matt 
     46      1.1   matt /*
     47      1.1   matt  * Special Purpose Register declarations.
     48      1.1   matt  *
     49      1.1   matt  * The first column in the comments indicates which PowerPC architectures the
     50      1.1   matt  * SPR is valid on - E for BookE series, 4 for 4xx series,
     51      1.1   matt  * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series.
     52      1.1   matt  */
     53      1.1   matt 
     54      1.1   matt #define	SPR_PID0		48	/* E4.. 440 Process ID */
     55      1.1   matt #define	SPR_DECAR		54	/* E... Decrementer Auto-reload */
     56      1.1   matt #define	SPR_CSRR0		58	/* E... Critical Save/Restore Reg. 0 */
     57      1.1   matt #define	SPR_CSRR1		59	/* E... Critical Save/Restore Reg. 1 */
     58      1.1   matt #define	SPR_DEAR		61	/* E... Data Exception Address Reg. */
     59      1.1   matt #define	SPR_ESR			62	/* E... Exception Syndrome Register */
     60      1.1   matt #define	  ESR_PIL		  0x08000000 /* 4: Program ILlegal */
     61      1.1   matt #define	  ESR_PPR		  0x04000000 /* 5: Program PRivileged */
     62      1.1   matt #define	  ESR_PTR		  0x02000000 /* 6: Program TRap */
     63      1.1   matt #define	  ESR_ST		  0x00800000 /* 8: Store operation */
     64      1.1   matt #define	  ESR_DLK		  0x00200000 /* 10: dcache exception */
     65      1.1   matt #define	  ESR_ILK		  0x00100000 /* 11: icache exception */
     66      1.1   matt #define	  ESR_AP		  0x00100000 /* 12: Auxiliary Processor operation exception */
     67      1.1   matt #define	  ESR_PUO		  0x00100000 /* 13: Program Unimplemented Operation exception */
     68      1.1   matt #define	  ESR_BO		  0x00020000 /* 14: Byte ordering exception */
     69      1.1   matt #define	  ESR_PIE		  0x00020000 /* 14: Program Imprecise Exception */
     70      1.1   matt #define	  ESR_SPV		  0x00000080 /* 24: SPE exception */
     71      1.1   matt #define	  ESR_VLEMI		  0x00000080 /* 26: VLE exception */
     72      1.1   matt #define	  ESR_MIF		  0x00000080 /* 30: VLE Misaligned Instruction Fetch */
     73      1.1   matt #define	  ESR_XTE		  0x00000080 /* 31: eXternal Transaction Error */
     74      1.1   matt #define	SPR_IVPR		63	/* E... Interrupt Vector Prefix Reg. */
     75      1.1   matt #define	SPR_USPRG0		256	/* E4.. User SPR General 0 */
     76      1.1   matt #define	SPR_USPRG3		259	/* E... User SPR General 3 */
     77      1.1   matt #define	SPR_USPRG4		260	/* E... User SPR General 4 */
     78      1.1   matt #define	SPR_USPRG5		261	/* E... User SPR General 5 */
     79      1.1   matt #define	SPR_USPRG6		262	/* E... User SPR General 6 */
     80      1.1   matt #define	SPR_USPRG7		263	/* E... User SPR General 7 */
     81      1.1   matt #define	SPR_RTBL		268	/* E468 Time Base Lower (RO) */
     82      1.1   matt #define	SPR_RTBU		269	/* E468 Time Base Upper (RO) */
     83      1.1   matt #define	SPR_WTBL		284	/* E468 Time Base Lower (WO) */
     84      1.1   matt #define	SPR_WTBU		285	/* E468 Time Base Upper (WO) */
     85      1.1   matt 
     86      1.1   matt #define	SPR_DBSR		304	/* E... Debug Status Register (W1C) */
     87      1.1   matt #define   DBSR_IDE		  0x80000000 /* 0: Imprecise debug event */
     88      1.1   matt #define	  DBSR_UDE		  0x40000000 /* 1: Unconditional debug event */
     89      1.1   matt #define	  DBSR_MRR_HARD		  0x20000000 /* 2: Most Recent Reset (Hard) */
     90      1.1   matt #define	  DBSR_MRR_SOFT		  0x10000000 /* 3: Most Recent Reset (Soft) */
     91      1.1   matt #define	  DBSR_ICMP		  0x08000000 /* 4: Instruction completion debug event */
     92      1.1   matt #define	  DBSR_BRT		  0x04000000 /* 5: Branch Taken debug event */
     93      1.1   matt #define	  DBSR_IRPT		  0x02000000 /* 6: Interrupt Taken debug event */
     94      1.1   matt #define	  DBSR_TRAP		  0x01000000 /* 7: Trap Instruction debug event */
     95      1.1   matt #define	  DBSR_IAC1		  0x00800000 /* 8: IAC1 debug event */
     96      1.1   matt #define	  DBSR_IAC2		  0x00400000 /* 9: IAC2 debug event */
     97      1.1   matt #define	  DBSR_DR1		  0x00080000 /* 12: DAC1 Read debug event */
     98      1.1   matt #define	  DBSR_DW1		  0x00040000 /* 13: DAC1 Write debug event */
     99      1.1   matt #define	  DBSR_DR2		  0x00020000 /* 14: DAC2 Read debug event */
    100      1.1   matt #define	  DBSR_DW2		  0x00010000 /* 15: DAC2 Write debug event */
    101      1.1   matt #define	  DBSR_RET		  0x00008000 /* 16: Return debug event */
    102      1.1   matt #define	SPR_DBCR0		308	/* E... Debug Control Register 0 */
    103      1.1   matt #define	  DBCR0_EDM		  0x80000000 /* 0: External Debug Mode */
    104      1.1   matt #define	  DBCR0_IDM		  0x40000000 /* 1: Internal Debug Mode */
    105      1.1   matt #define	  DBCR0_RST_MASK	  0x30000000 /* 2..3: ReSeT */
    106      1.1   matt #define	  DBCR0_RST_NONE	  0x00000000 /*   No action */
    107      1.1   matt #define	  DBCR0_RST_CORE	  0x10000000 /*   Core reset */
    108      1.1   matt #define	  DBCR0_RST_CHIP	  0x20000000 /*   Chip reset */
    109      1.1   matt #define	  DBCR0_RST_SYSTEM	  0x30000000 /*   System reset */
    110      1.1   matt #define	  DBCR0_IC		  0x08000000 /* 4: Instruction Completion debug event */
    111      1.1   matt #define	  DBCR0_BT		  0x04000000 /* 5: Branch Taken debug event */
    112      1.1   matt #define	  DBCR0_EDE		  0x02000000 /* 6: Exception Debug Event */
    113      1.1   matt #define	  DBCR0_TDE		  0x01000000 /* 7: Trap Debug Event */
    114      1.1   matt #define	  DBCR0_IA1		  0x00800000 /* 8: IAC (Instruction Address Compare) 1 debug event */
    115      1.1   matt #define	  DBCR0_IA2		  0x00400000 /* 9: IAC 2 debug event */
    116      1.1   matt #define	  DBCR0_IA12		  0x00200000 /* 10: Instruction Address Range Compare 1-2 */
    117      1.1   matt #define	  DBCR0_IA12X		  0x00100000 /* 11: IA12 eXclusive */
    118      1.1   matt #define	  DBCR0_IA3		  0x00080000 /* 12: IAC 3 debug event */
    119      1.1   matt #define	  DBCR0_DAC1_LOAD	  0x00080000 /* 12: DAC (Data Address Compare) 1 load event (e500) */
    120      1.1   matt #define	  DBCR0_IA4		  0x00040000 /* 13: IAC 4 debug event */
    121      1.1   matt #define	  DBCR0_DAC1_STORE	  0x00040000 /* 13: DAC (Data Address Compare) 1 store event (e500) */
    122      1.1   matt #define	  DBCR0_IA34		  0x00020000 /* 14: Instruction Address Range Compare 3-4 */
    123      1.1   matt #define	  DBCR0_DAC2_LOAD	  0x00020000 /* 14: DAC 2 load event (e500) */
    124      1.1   matt #define	  DBCR0_IA34X		  0x00010000 /* 15: IA34 eXclusive */
    125      1.1   matt #define	  DBCR0_DAC2_STORE	  0x00010000 /* 15: DAC 2 store event (e500) */
    126      1.1   matt #define	  DBCR0_IA12T		  0x00008000 /* 16: Instruction Address Range Compare 1-2 range Toggle */
    127      1.1   matt #define	  DBCR0_RET		  0x00008000 /* 16: Return debug event (e500) */
    128      1.1   matt #define	  DBCR0_IA34T		  0x00004000 /* 17: Instruction Address Range Compare 3-4 range Toggle */
    129      1.1   matt #define	  DBCR0_FT		  0x00000001 /* 31: Freeze Timers on debug event */
    130      1.1   matt #define	SPR_DBCR1		309	/* E... Debug Control Register 1 */
    131      1.1   matt #define	SPR_DBCR2		310	/* E... Debug Control Register 2 */
    132      1.1   matt #define	SPR_IAC1		312	/* E... Instruction Address Compare 1 */
    133      1.1   matt #define	SPR_IAC2		313	/* E... Instruction Address Compare 2 */
    134      1.1   matt #define	SPR_IAC3		314	/* E... Instruction Address Compare 3 */
    135      1.1   matt #define	SPR_IAC4		315	/* E... Instruction Address Compare 4 */
    136      1.1   matt #define	SPR_DAC1		316	/* E... Data Address Compare 1 */
    137      1.1   matt #define	SPR_DAC2		317	/* E... Data Address Compare 2 */
    138      1.1   matt #define	SPR_TSR			336	/* E... Timer Status Register */
    139      1.1   matt #define   TSR_ENW		  0x80000000 /* Enable Next Watchdog (W1C) */
    140      1.1   matt #define   TSR_WIS		  0x40000000 /* Watchdog Interrupt Status (W1C) */
    141      1.1   matt #define   TSR_WRS		  0x30000000 /* Watchdog Reset Status (W1C) */
    142      1.1   matt #define   TSR_DIS		  0x08000000 /* Decementer Interrupt Status (W1C) */
    143      1.1   matt #define   TSR_FIS		  0x04000000 /* Fixed-interval Interrupt Status (W1C) */
    144      1.1   matt #define	SPR_TCR			340	/* E... Timer Control Register */
    145      1.1   matt #define   TCR_WP		  0xc0000000 /* Watchdog Period */
    146  1.1.4.1  rmind #define	  TCR_WP_2_N(n)		  ((((64 - (n)) & 3) << 30) | (((64 - (n)) & 0x3c0) << 15))
    147  1.1.4.1  rmind #define	  TCR_WP_2_64		  0x00000000
    148  1.1.4.1  rmind #define	  TCR_WP_2_1		  0xc01e0000
    149      1.1   matt #define   TCR_WRC		  0x30000000 /* Watchdog Timer Reset Control */
    150      1.1   matt #define   TCR_WIE		  0x08000000 /* Watchdog Time Interrupt Enable */
    151      1.1   matt #define   TCR_DIE		  0x04000000 /* Decremnter Interrupt Enable */
    152      1.1   matt #define   TCR_FP		  0x03000000 /* Fixed-interval Timer Period */
    153  1.1.4.1  rmind #define	  TCR_FP_2_N(n)		  ((((64 - (n)) & 3) << 24) | (((64 - (n)) & 0x3c0) << 11))
    154  1.1.4.1  rmind #define	  TCR_FP_2_64		  0x00000000
    155  1.1.4.1  rmind #define	  TCR_FP_2_1		  0x0301e000
    156      1.1   matt #define   TCR_FIE		  0x00800000 /* Fixed-interval Interrupt Enable */
    157      1.1   matt #define   TCR_ARE		  0x00400000 /* Auto-reload Enable */
    158  1.1.4.1  rmind #define   TCR_WPEXT		  0x001e0000 /* Watchdog Period Extension */
    159  1.1.4.1  rmind #define   TCR_FPEXT		  0x0001e000 /* Fixed-interval Period Extension */
    160      1.1   matt 
    161      1.1   matt #define	SPR_IVOR0		400	/* E... Critical input interrupt offset */
    162      1.1   matt #define	SPR_IVOR1		401	/* E... Machine check interrupt offset */
    163      1.1   matt #define	SPR_IVOR2		402	/* E... Data storage interrupt offset */
    164      1.1   matt #define	SPR_IVOR3		403	/* E... Instruction storage interrupt offset */
    165      1.1   matt #define	SPR_IVOR4		404	/* E... External input interrupt offset */
    166      1.1   matt #define	SPR_IVOR5		405	/* E... Alignment interrupt offset */
    167      1.1   matt #define	SPR_IVOR6		406	/* E... Program interrupt offset */
    168      1.1   matt #define	SPR_IVOR8		408	/* E... Syscall call interrupt offset */
    169      1.1   matt #define	SPR_IVOR10		410	/* E... Decrementer interrupt offset */
    170      1.1   matt #define	SPR_IVOR11		411	/* E... Fixed-interval timer interrupt offset */
    171      1.1   matt #define	SPR_IVOR12		412	/* E... Watchdog timer interrupt offset */
    172      1.1   matt #define	SPR_IVOR13		413	/* E... Data TLB error interrupt offset */
    173      1.1   matt #define	SPR_IVOR14		414	/* E... Instruction TLB error interrupt offset */
    174      1.1   matt #define	SPR_IVOR15		415	/* E... Debug interrupt offset */
    175      1.1   matt #define SPR_SPEFSCR		512	/* E... Signal processing and embedded floating-point status and control register */
    176      1.1   matt #define  SPEFSCR_SOVH		  0x80000000 /* 0: Summary Integer Overflow High */
    177      1.1   matt #define  SPEFSCR_OVH		  0x40000000 /* 1: Integer Overflow High */
    178      1.1   matt #define  SPEFSCR_FGH		  0x20000000 /* 2: Embedded Floating-Point Guard Bit High */
    179      1.1   matt #define  SPEFSCR_FXH		  0x10000000 /* 3: Embedded Floating-Point Sticky Bit High */
    180      1.1   matt #define  SPEFSCR_FINVH		  0x08000000 /* 4: Embedded Floating-Point Invalid Operation High */
    181      1.1   matt #define  SPEFSCR_FDBZH		  0x04000000 /* 5: Embedded Floating-Point Divide By Zero Error High */
    182      1.1   matt #define  SPEFSCR_FUNFH		  0x02000000 /* 6: Embedded Floating-Point Underflow Error High */
    183      1.1   matt #define  SPEFSCR_FOVFH		  0x01000000 /* 7: Embedded Floating-Point Overflow Error High */
    184      1.1   matt #define  SPEFSCR_FINXS		  0x00200000 /* 10: Embedded Floating-Point Inexact Sticky Bit */
    185      1.1   matt #define  SPEFSCR_FINVS		  0x00100000 /* 11: Embedded Floating-Point Invalid Operation Sticky Bit */
    186      1.1   matt #define  SPEFSCR_FDBZS		  0x00080000 /* 12: Embedded Floating-Point Divide By Zero Sticky Bit */
    187      1.1   matt #define  SPEFSCR_FUNFS		  0x00040000 /* 13: Embedded Floating-Point Underflow Sticky Bit */
    188      1.1   matt #define  SPEFSCR_FOVFS		  0x00020000 /* 14: Embedded Floating-Point Overflow Sticky Bit */
    189      1.1   matt #define  SPEFSCR_MODE		  0x00010000 /* 15: Embedded Floating-Point Mode */
    190      1.1   matt #define  SPEFSCR_SOV		  0x80000000 /* 16: Summary Integer Overflow */
    191      1.1   matt #define  SPEFSCR_OV		  0x00004000 /* 17: Integer Overflow */
    192      1.1   matt #define  SPEFSCR_FG		  0x00002000 /* 18: Embedded Floating-Point Guard Bit */
    193      1.1   matt #define  SPEFSCR_FX		  0x00001000 /* 19: Embedded Floating-Point Sticky Bit */
    194      1.1   matt #define  SPEFSCR_FINV		  0x00000800 /* 20: Embedded Floating-Point Invalid Operation */
    195      1.1   matt #define  SPEFSCR_FDBZ		  0x00000400 /* 21: Embedded Floating-Point Divide By Zero Error */
    196      1.1   matt #define  SPEFSCR_FUNF		  0x00000200 /* 22: Embedded Floating-Point Underflow Error */
    197      1.1   matt #define  SPEFSCR_FOVF		  0x00000100 /* 23: Embedded Floating-Point Overflow Error */
    198      1.1   matt #define  SPEFSCR_FINXE		  0x00000040 /* 25: Embedded Floating-Point Inexact Execption Enable */
    199      1.1   matt #define  SPEFSCR_FINVE		  0x00000020 /* 26: Embedded Floating-Point Invalid Operation/Input Error Execption Enable */
    200      1.1   matt #define  SPEFSCR_FDBZE		  0x00000010 /* 27: Embedded Floating-Point Divide By Zero Exception Enable */
    201      1.1   matt #define  SPEFSCR_FUNFE		  0x00000008 /* 28: Embedded Floating-Point Underflow Exception Enable */
    202      1.1   matt #define  SPEFSCR_FOVFE		  0x00000004 /* 29: Embedded Floating-Point Overflow Exception Enable */
    203      1.1   matt #define  SPEFSCR_FRMC_MASK	  0x00000003 /* 30..31: Embedded Floating-Point Rounding Mode Control */
    204      1.1   matt #define  SPEFSCR_FRMC_DOWNWARD	  0x00000003 /* Round toward -infinity */
    205      1.1   matt #define  SPEFSCR_FRMC_UPWARD	  0x00000002 /* Round toward +infinity */
    206      1.1   matt #define  SPEFSCR_FRMC_TOWARDZERO  0x00000001 /* Round toward zero */
    207      1.1   matt #define  SPEFSCR_FRMC_TONEAREST	  0x00000000 /* Round to nearest */
    208      1.1   matt #define	SPR_BBEAR		513	/* E... Brach buffer entry addr register */
    209      1.1   matt #define	SPR_BBTAR		514	/* E... Brach buffer target addr register */
    210      1.1   matt #define	SPR_L1CFG0		515	/* E... L1 Cache Configuration Register 0 */
    211      1.1   matt #define	SPR_L1CFG1		516	/* E... L1 Cache Configuration Register 1 */
    212      1.1   matt #define   L1CFG_CARCH_GET(n)	  (((n) >> 30) & 3)
    213      1.1   matt #define   L1CFG_CARCH_HARVARD	  0
    214      1.1   matt #define   L1CFG_CARCH_UNIFIED	  1
    215      1.1   matt #define   L1CFG_CBSIZE_GET(n)	  (((n) >> 23) & 3)
    216      1.1   matt #define   L1CFG_CBSIZE_32B	  0
    217      1.1   matt #define   L1CFG_CBSIZE_64B	  1
    218      1.1   matt #define   L1CFG_CREPL_GET(n)	  (((n) >> 21) & 3)
    219      1.1   matt #define   L1CFG_CREPL_TRUE_LRU	  0
    220      1.1   matt #define   L1CFG_CREPL_PSEUDO_LRU  1
    221      1.1   matt #define   L1CFG_CLA_P(n)	  (((n) >> 20) & 1)
    222      1.1   matt #define   L1CFG_CPA_P(n)	  (((n) >> 19) & 1)
    223      1.1   matt #define   L1CFG_CNWAY_GET(n)	  ((((n) >> 13) & 0xff) + 1)
    224      1.1   matt #define   L1CFG_CSIZE_GET(n)	  ((((n) >>  0) & 0x7ff) << 10)
    225      1.1   matt #define	SPR_ATBL		526	/* E... Alternate Time Base Lower */
    226      1.1   matt #define	SPR_ATBU		527	/* E... Alternate Time Base Upper */
    227      1.1   matt #define	SPR_IVOR32		528	/* E... SPE unavailable interrupt offset */
    228      1.1   matt #define	SPR_IVOR33		529	/* E... Floating-point data exception interrupt offset */
    229      1.1   matt #define	SPR_IVOR34		530	/* E... Floating-point round exception interrupt offset */
    230      1.1   matt #define	SPR_IVOR35		531	/* E... Performance monitor interrupt offset */
    231      1.1   matt #define SPR_MCARU		569	/* E... Machine check address register upper */
    232      1.1   matt #define SPR_MCSRR0		570	/* E... Machine check save/restore register 0 */
    233      1.1   matt #define SPR_MCSRR1		571	/* E... Machine check save/restore register 1 */
    234      1.1   matt #define SPR_MCSR		572	/* E... Machine check syndrome register */
    235      1.1   matt #define   MCSR_MCP		  0x80000000 /* 0: Machine Check Input Pin */
    236      1.1   matt #define   MCSR_ICPERR		  0x40000000 /* 1: Instruction Cache Parity Error */
    237      1.1   matt #define   MCSR_DCP_PERR		  0x20000000 /* 2: Data Cache Push Parity Error */
    238      1.1   matt #define   MCSR_DCPERR		  0x10000000 /* 3: Data Cache Parity Error */
    239      1.1   matt #define   MCSR_NMI		  0x00100000 /* 12: non maskable interrupt */
    240      1.1   matt #define   MCSR_MAV		  0x00080000 /* 13: MCAR address valid */
    241      1.1   matt #define   MCSR_MEA		  0x00040000 /* 14: MCAR [is an] effective address */
    242      1.1   matt #define   MCSR_BUS_IAERR	  0x00000080 /* 24: Bus Instruction Address Error */
    243      1.1   matt #define   MCSR_BUS_RAERR	  0x00000040 /* 25: Bus Read Address Error */
    244      1.1   matt #define   MCSR_BUS_WAERR	  0x00000020 /* 26: Bus Write Address Error */
    245      1.1   matt #define   MCSR_BUS_IBERR	  0x00000010 /* 27: Bus Instruction Data Bus Error */
    246      1.1   matt #define   MCSR_BUS_RBERR	  0x00000008 /* 28: Bus Read Data Bus Error */
    247      1.1   matt #define   MCSR_BUS_WBERR	  0x00000004 /* 29: Bus Write Data Bus Error */
    248      1.1   matt #define   MCSR_BUS_IPERR	  0x00000002 /* 30: Bus Instruction Parity Error */
    249      1.1   matt #define   MCSR_BUS_RPERR	  0x00000001 /* 31: Bus Read Parity Error */
    250      1.1   matt #define SPR_MCAR		573	/* E... Machine check address register */
    251      1.1   matt #define	SPR_MAS0		624	/* E... MAS Register 0 */
    252      1.1   matt #define   MAS0_TLBSEL		  0x03000000 /* Select TLB<n> for access */
    253      1.1   matt #define   MAS0_TLBSEL_TLB3	  0x03000000 /* Select TLB3 for access */
    254      1.1   matt #define   MAS0_TLBSEL_TLB2	  0x02000000 /* Select TLB2 for access */
    255      1.1   matt #define   MAS0_TLBSEL_TLB1	  0x01000000 /* Select TLB1 for access */
    256      1.1   matt #define   MAS0_TLBSEL_TLB0	  0x00000000 /* Select TLB0 for access */
    257      1.1   matt #define   MASX_TLBSEL_GET(n)	  (((n) >> 28) & 3)
    258      1.1   matt #define   MASX_TLBSEL_MAKE(n)	  (((n) & 3) << 28)
    259      1.1   matt #define   MAS0_ESEL		  0x0fff0000 /* entry (way) select for tlbwe */
    260      1.1   matt #define   MAS0_ESEL_GET(n)	  (((n) >> 16) & 4095)
    261      1.1   matt #define   MAS0_ESEL_MAKE(n)	  (((n) & 4095) << 16)
    262      1.1   matt #define   MAS0_NV		  0x00000fff /* next victim fr TLB0[NV] */
    263      1.1   matt #define	SPR_MAS1		625	/* E... MAS Register 1 */
    264      1.1   matt #define	  MAS1_V		  0x80000000 /* TLB Valid Bit */
    265      1.1   matt #define   MAS1_IPROT		  0x40000000 /* Invalidate Protect */
    266      1.1   matt #define   MAS1_TID		  0x0fff0000 /* Translation Identity */
    267      1.1   matt #define   MASX_TID_GET(n)	  (((n) >> 16) & 4095)
    268      1.1   matt #define   MASX_TID_MAKE(n)	  (((n) & 4095) << 16)
    269      1.1   matt #define   MAS1_TS		  0x00001000 /* Translation Space [IS/DS MSR] */
    270      1.1   matt #define	  MAS1_TS_SHIFT		  12
    271      1.1   matt #define   MAS1_TSIZE		  0x00000f00 /* Translation Size (4KB**tsize) */
    272      1.1   matt #define   MASX_TSIZE_GET(n)	  (((n) >> 8) & 15)
    273      1.1   matt #define   MASX_TSIZE_MAKE(n)	  (((n) & 15) << 8)
    274      1.1   matt #define	SPR_MAS2		626	/* E... MAS Register 2 */
    275      1.1   matt #define   MAS2_EPN		  0xfffff000 /* Effective Page Number */
    276      1.1   matt #define   MAS2_EPN_GET(n)	  (((n) >> 12) & 1048575)
    277      1.1   matt #define   MAS2_EPN_MAKE(n)	  (((n) & 1048575) << 12)
    278      1.1   matt #define	  MAS2_X0		  0x00000040 /* Impl. dependent page attr. */
    279      1.1   matt #define	  MAS2_ACM		  0x000000c0 /* Alternate Coherency Mode. */
    280      1.1   matt #define	  MAS2_X1		  0x00000020 /* Impl. dependent page attr. */
    281      1.1   matt #define	  MAS2_VLE		  0x00000020 /* VLE mode. */
    282      1.1   matt #define	  MAS2_WIMGE		  0x0000001f /* Mask of next 5 bits */
    283      1.1   matt #define	  MAS2_W		  0x00000010 /* Write-through */
    284      1.1   matt #define	  MAS2_I		  0x00000008 /* cache-Inhibited */
    285      1.1   matt #define	  MAS2_M		  0x00000004 /* Memory coherency required */
    286      1.1   matt #define	  MAS2_G		  0x00000002 /* Gaurded */
    287      1.1   matt #define	  MAS2_E		  0x00000001 /* [little] Endianness */
    288      1.1   matt #define	SPR_MAS3		627	/* E... MAS Register 3 */
    289      1.1   matt #define   MAS3_RPN		  0xfffff000 /* Real Page Number */
    290      1.1   matt #define   MAS3_RPN_GET(n)	  (((n) >> 12) & 1048575)
    291      1.1   matt #define   MAS3_RPN_MAKE(n)	  (((n) & 1048575) << 12)
    292      1.1   matt #define   MAS3_U0		  0x00000200 /* User attribute 0 */
    293      1.1   matt #define   MAS3_U1		  0x00000100 /* User attribute 1 */
    294      1.1   matt #define   MAS3_U2		  0x00000080 /* User attribute 2 */
    295      1.1   matt #define   MAS3_U3		  0x00000040 /* User attribute 3 */
    296      1.1   matt #define   MAS3_UX		  0x00000020 /* User execute permission */
    297      1.1   matt #define   MAS3_SX		  0x00000010 /* System execute permission */
    298      1.1   matt #define   MAS3_UW		  0x00000008 /* User write permission */
    299      1.1   matt #define   MAS3_SW		  0x00000004 /* System write permission */
    300      1.1   matt #define   MAS3_UR		  0x00000002 /* User read permission */
    301      1.1   matt #define   MAS3_SR		  0x00000001 /* System read permission */
    302      1.1   matt #define	SPR_MAS4		628	/* E... MAS Register 4 */
    303      1.1   matt #define   MAS4_TLBSELD		  0x30000000 /* TLBSEL default value */
    304      1.1   matt #define   MAS4_TIDSELD		  0x0fff0000 /* select TID default value */
    305      1.1   matt #define   MAS4_TSIZED		  0x00000f00 /* TSIZE default value */
    306      1.1   matt #define	  MAS4_ACMD		  0x000000c0 /* Alternate Coherency Mode. */
    307      1.1   matt #define	  MAS4_X0D		  0x00000040 /* default Impl. dep. page attr. */
    308      1.1   matt #define	  MAS4_VLED		  0x00000020 /* VLE mode. */
    309      1.1   matt #define	  MAS4_X1D		  0x00000020 /* default Impl. dep. page attr. */
    310      1.1   matt #define	  MAS4_WD		  0x00000010 /* default Write-through */
    311      1.1   matt #define	  MAS4_ID		  0x00000008 /* default Cache-inhibited */
    312      1.1   matt #define	  MAS4_MD		  0x00000004 /* default Memory coherency req. */
    313      1.1   matt #define	  MAS4_GD		  0x00000002 /* default Gaurded */
    314      1.1   matt #define	  MAS4_ED		  0x00000001 /* default [little] Endianness */
    315      1.1   matt #define	SPR_MAS6		630	/* E... MAS Register 6 (TLB Seach CTX) */
    316      1.1   matt #define   MAS6_SPID0		  0x0fff0000 /* PID used with tlbsx */
    317      1.1   matt #define	  MAS6_SPID0_SHIFT	  16
    318      1.1   matt #define   MAS6_SAS		  0x00000001 /* Address space (IS/DS MSR) ... */
    319      1.1   matt #define   MAS6_SAS_USER		  0x00000001 /* Address space (IS/DS MSR) ... */
    320      1.1   matt #define	SPR_PID1		633	/* E... PID Register 1 */
    321      1.1   matt #define	SPR_PID2		634	/* E... PID Register 2 */
    322      1.1   matt #define	SPR_TLB0CFG		688	/* E... TLB Configuration Register 0 */
    323      1.1   matt #define	SPR_TLB1CFG		689	/* E... TLB Configuration Register 1 */
    324      1.1   matt #define	  TLBCFG_ASSOC(n)	  (((n) >> 24) & 0xff) /* assoc of tlb */
    325      1.1   matt #define	  TLBCFG_MINSIZE(n)	  (((n) >> 20) & 0x0f) /* minpagesize */
    326      1.1   matt #define	  TLBCFG_MAXSIZE(n)	  (((n) >> 16) & 0x0f) /* maxpagesize */
    327      1.1   matt #define	  TLBCFG_IPROT_P(n)	  (((n) >> 15) & 0x01)
    328      1.1   matt #define	  TLBCFG_AVAIL_P(n)	  (((n) >> 14) & 0x01) /* variable page size */
    329      1.1   matt #define	  TLBCFG_NENTRY(n)	  (((n) >>  0) & 0xfff) /* # entrys */
    330      1.1   matt #define	SPR_MAS7		944	/* E... MAS Register 7 */
    331      1.1   matt #define	 MAS7_RPNHI		  0x00000004 /* bits 32-35 of RPN */
    332      1.1   matt #define	SPR_HID0		1008
    333      1.1   matt #define	SPR_HID1		1009
    334      1.1   matt #define	SPR_L1CSR0		1010	/* E... L1 Cache Control and Status Register 0 (Data) */
    335      1.1   matt #define	SPR_L1CSR1		1011	/* E... L1 Cache Control and Status Register 1 (Instruction) */
    336      1.1   matt #define   L1CSR_CPE		  0x00010000 /* 15: Cache Parity Error */
    337      1.1   matt #define   L1CSR_CPI		  0x00008000 /* 16: Cache Parity Injection Enable */
    338      1.1   matt #define   L1CSR_CSLC		  0x00000800 /* 20: Cache Snoop Lock Clear */
    339      1.1   matt #define   L1CSR_CUL		  0x00000400 /* 21: Cache Unable to Lock (W0C) */
    340      1.1   matt #define   L1CSR_CLO		  0x00000200 /* 22: Cache Lock Overflow (W0C) */
    341      1.1   matt #define   L1CSR_CLFR		  0x00000100 /* 23: Cache Lock Bits Flash Reset */
    342      1.1   matt #define   L1CSR_CFI		  0x00000002 /* 30: Cache Flash Invalidate */
    343      1.1   matt #define   L1CSR_CE		  0x00000001 /* 31: Cache Enable */
    344      1.1   matt #define	SPR_MMUCSR0		1012	/* E... MMU Control and Status Register 0 */
    345      1.1   matt #define	  MMUCSR0_TLB2_FI	  0x00000040 /* TLB2 Flash Invalidate */
    346      1.1   matt #define	  MMUCSR0_TLB3_FI	  0x00000020 /* TLB3 Flash Invalidate */
    347      1.1   matt #define	  MMUCSR0_TLB0_FI	  0x00000004 /* TLB0 Flash Invalidate */
    348      1.1   matt #define	  MMUCSR0_TLB1_FI	  0x00000002 /* TLB1 Flash Invalidate */
    349      1.1   matt #define SPR_BUCSR		1013	/* E... Branch Unit Control and Status Register */
    350      1.1   matt #define	SPR_MMUCFG		1015	/* E... MMU Configuration Register */
    351      1.1   matt #define   MMUCFG_RASIZE_GET(n)	  (((n) >> 17) & 127) /* Real Address Size */
    352      1.1   matt #define	  MMUCFG_NPIDS_GET(n)	  (((n) >> 11) & 15) /* # of PID registers */
    353      1.1   matt #define	  MMUCFG_PIDSIZE_GET(n)	  (((n) >> 6) & 31) /* PID is PIDSIZE+1 bits wide */
    354      1.1   matt #define	  MMUCFG_NTLBS_GET(n)	  (((n) >> 2) & 3) /* NTLBS is max value of MAS0[TLBSEL] */
    355      1.1   matt #define	  MMUCFG_MAVN		  0x00000003 /* MMU Architecture Version Number */
    356      1.1   matt #define	  MMUCFG_MAVN_V1	  0
    357      1.1   matt #define	SPR_SVR			1023	/* E... System Version Register */
    358      1.1   matt 
    359      1.1   matt #define	PMR_PMC0		16
    360      1.1   matt #define	PMR_PMC1		17
    361      1.1   matt #define	PMR_PMC2		18
    362      1.1   matt #define	PMR_PMC3		19
    363      1.1   matt #define	PMR_PMLCa0		144
    364      1.1   matt #define	PMR_PMLCa1		145
    365      1.1   matt #define	PMR_PMLCa2		146
    366      1.1   matt #define	PMR_PMLCa3		147
    367      1.1   matt #define   PMLCa_FC		  0x80000000 /* 0: Freeze Counter */
    368      1.1   matt #define   PMLCa_FCS		  0x40000000 /* 1: Freeze Counter In Super */
    369      1.1   matt #define   PMLCa_FCU		  0x20000000 /* 2: Freeze Counter In User */
    370      1.1   matt #define   PMLCa_FCM1		  0x10000000 /* 3: Freeze Counter While Mark=1 */
    371      1.1   matt #define   PMLCa_FCM0		  0x08000000 /* 4: Freeze Counter While Mark=0 */
    372      1.1   matt #define   PMLCa_CE		  0x04000000 /* 5: Condition Enable */
    373      1.1   matt #define   PMLCa_EVENT		  0x007f0000 /* 9..15: Event */
    374      1.1   matt #define   PMLCa_EVENT_GET(n)	  (((n) >> 16) & 127)
    375      1.1   matt #define   PMLCa_EVENT_MAKE(n)	  (((n) & 127) << 16)
    376      1.1   matt 
    377      1.1   matt #define	PMR_PMLCb0		272
    378      1.1   matt #define	PMR_PMLCb1		273
    379      1.1   matt #define	PMR_PMLCb2		274
    380      1.1   matt #define	PMR_PMLCb3		275
    381      1.1   matt #define   PMLCb_THRESHMUL	  0x00007f00 /* 21..23: multiply threshold by 2**<n> */
    382      1.1   matt #define   PMLCb_THRESHMUL_GET(n)  (((n) >> 16) & 127)
    383      1.1   matt #define   PMLCb_THRESHMUL_MAKE(n) (((n) & 127) << 16)
    384      1.1   matt #define   PMLCb_THRESHOLD	  0x0000003f /* 26..31: threshold */
    385      1.1   matt #define   PMLCb_THRESHOLD_GET(n)  (((n) >> 0) & 63)
    386      1.1   matt #define   PMLCb_THRESHOLD_MAKE(n) (((n) & 63) << 0)
    387      1.1   matt #define	PMR_PMGC0		400
    388      1.1   matt #define   PMGC0_FAC		  0x80000000 /* 0: Freeze All Counters */
    389      1.1   matt #define	  PMGC0_PMIE		  0x40000000 /* 1: Performance Monitor Interrupt Enable */
    390      1.1   matt #define	  PMGC0_FCECE		  0x40000000 /* 1: Freeze count on enabled condition or event */
    391      1.1   matt #define   PMGC0_TBSEL		  0x00001800 /* 19..20: Time base selector */
    392      1.1   matt #define   PMGC0_TBEE		  0x00000100 /* 23: Time base transition event exception enable */
    393      1.1   matt 
    394      1.1   matt #define	PMR_UPMC0			(PMR_PMC0 - 16)
    395      1.1   matt #define	PMR_UPMC1			(PMR_PMC1 - 16)
    396      1.1   matt #define	PMR_UPMC2			(PMR_PMC2 - 16)
    397      1.1   matt #define	PMR_UPMC3			(PMR_PMC3 - 16)
    398      1.1   matt #define	PMR_UPMLCa0			(PMR_PMLCa0 - 16)
    399      1.1   matt #define	PMR_UPMLCa1			(PMR_PMLCa1 - 16)
    400      1.1   matt #define	PMR_UPMLCa2			(PMR_PMLCa2 - 16)
    401      1.1   matt #define	PMR_UPMLCa3			(PMR_PMLCa3 - 16)
    402      1.1   matt #define	PMR_UPMLCb0			(PMR_PMLCb0 - 16)
    403      1.1   matt #define	PMR_UPMLCb1			(PMR_PMLCb1 - 16)
    404      1.1   matt #define	PMR_UPMLCb2			(PMR_PMLCb2 - 16)
    405      1.1   matt #define	PMR_UPMLCb3			(PMR_PMLCb3 - 16)
    406      1.1   matt #define	PMR_UPMGC0			(PMR_PMGC0 - 16)
    407      1.1   matt 
    408      1.1   matt #endif /* !_POWERPC_SPR_H_ */
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