spr.h revision 1.3
1 /* $NetBSD: spr.h,v 1.3 2011/01/18 01:02:54 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _POWERPC_BOOKE_SPR_H_ 38 #define _POWERPC_BOOKE_SPR_H_ 39 40 #define PVR_MPCe500 0x8020 41 #define PVR_MPCe500v2 0x8021 42 #define SVR_MPC8548v1 0x80310010 43 #define SVR_MPC8543v1 0x80320010 44 #define SVR_MPC8548v1plus 0x80310011 45 #define SVR_MPC8543v1plus 0x80320011 46 #define SVR_MPC8548v2 0x80310020 47 #define SVR_MPC8547v2 0x80310120 48 #define SVR_MPC8545v2 0x80310220 49 #define SVR_MPC8543v2 0x80320020 50 51 #define SVR_MPC8544v1 0x80340110 52 #define SVR_MPC8544v1plus 0x80340111 53 54 #define SVR_MPC8536v1 0x80370091 55 56 #define SVR_MPC8555v1 0x80710110 57 #define SVR_MPC8541v1 0x80720111 58 59 #define SVR_MPC8572 0x80e00011 60 #define SVR_SECURITY_P(svr) (((svr) & 0x00080000) != 0) 61 62 /* 63 * Special Purpose Register declarations. 64 * 65 * The first column in the comments indicates which PowerPC architectures the 66 * SPR is valid on - E for BookE series, 4 for 4xx series, 67 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series. 68 */ 69 70 #define SPR_PID0 48 /* E4.. 440 Process ID */ 71 #define SPR_DECAR 54 /* E... Decrementer Auto-reload */ 72 #define SPR_CSRR0 58 /* E... Critical Save/Restore Reg. 0 */ 73 #define SPR_CSRR1 59 /* E... Critical Save/Restore Reg. 1 */ 74 #define SPR_DEAR 61 /* E... Data Exception Address Reg. */ 75 #define SPR_ESR 62 /* E... Exception Syndrome Register */ 76 #define ESR_PIL 0x08000000 /* 4: Program ILlegal */ 77 #define ESR_PPR 0x04000000 /* 5: Program PRivileged */ 78 #define ESR_PTR 0x02000000 /* 6: Program TRap */ 79 #define ESR_ST 0x00800000 /* 8: Store operation */ 80 #define ESR_DLK 0x00200000 /* 10: dcache exception */ 81 #define ESR_ILK 0x00100000 /* 11: icache exception */ 82 #define ESR_AP 0x00100000 /* 12: Auxiliary Processor operation exception */ 83 #define ESR_PUO 0x00100000 /* 13: Program Unimplemented Operation exception */ 84 #define ESR_BO 0x00020000 /* 14: Byte ordering exception */ 85 #define ESR_PIE 0x00020000 /* 14: Program Imprecise Exception */ 86 #define ESR_SPV 0x00000080 /* 24: SPE exception */ 87 #define ESR_VLEMI 0x00000080 /* 26: VLE exception */ 88 #define ESR_MIF 0x00000080 /* 30: VLE Misaligned Instruction Fetch */ 89 #define ESR_XTE 0x00000080 /* 31: eXternal Transaction Error */ 90 #define SPR_IVPR 63 /* E... Interrupt Vector Prefix Reg. */ 91 #define SPR_USPRG0 256 /* E4.. User SPR General 0 */ 92 #define SPR_USPRG3 259 /* E... User SPR General 3 */ 93 #define SPR_USPRG4 260 /* E... User SPR General 4 */ 94 #define SPR_USPRG5 261 /* E... User SPR General 5 */ 95 #define SPR_USPRG6 262 /* E... User SPR General 6 */ 96 #define SPR_USPRG7 263 /* E... User SPR General 7 */ 97 #define SPR_RTBL 268 /* E468 Time Base Lower (RO) */ 98 #define SPR_RTBU 269 /* E468 Time Base Upper (RO) */ 99 #define SPR_WTBL 284 /* E468 Time Base Lower (WO) */ 100 #define SPR_WTBU 285 /* E468 Time Base Upper (WO) */ 101 #define SPR_PIR 286 /* E... Processor ID Register (RO) */ 102 103 #define SPR_DBSR 304 /* E... Debug Status Register (W1C) */ 104 #define DBSR_IDE 0x80000000 /* 0: Imprecise debug event */ 105 #define DBSR_UDE 0x40000000 /* 1: Unconditional debug event */ 106 #define DBSR_MRR_HARD 0x20000000 /* 2: Most Recent Reset (Hard) */ 107 #define DBSR_MRR_SOFT 0x10000000 /* 3: Most Recent Reset (Soft) */ 108 #define DBSR_ICMP 0x08000000 /* 4: Instruction completion debug event */ 109 #define DBSR_BRT 0x04000000 /* 5: Branch Taken debug event */ 110 #define DBSR_IRPT 0x02000000 /* 6: Interrupt Taken debug event */ 111 #define DBSR_TRAP 0x01000000 /* 7: Trap Instruction debug event */ 112 #define DBSR_IAC1 0x00800000 /* 8: IAC1 debug event */ 113 #define DBSR_IAC2 0x00400000 /* 9: IAC2 debug event */ 114 #define DBSR_DAC1R 0x00080000 /* 12: DAC1 Read debug event */ 115 #define DBSR_DAC1W 0x00040000 /* 13: DAC1 Write debug event */ 116 #define DBSR_DAC2R 0x00020000 /* 14: DAC2 Read debug event */ 117 #define DBSR_DAC2W 0x00010000 /* 15: DAC2 Write debug event */ 118 #define DBSR_RET 0x00008000 /* 16: Return debug event */ 119 #define SPR_DBCR0 308 /* E... Debug Control Register 0 */ 120 #define DBCR0_EDM 0x80000000 /* 0: External Debug Mode */ 121 #define DBCR0_IDM 0x40000000 /* 1: Internal Debug Mode */ 122 #define DBCR0_RST_MASK 0x30000000 /* 2..3: ReSeT */ 123 #define DBCR0_RST_NONE 0x00000000 /* No action */ 124 #define DBCR0_RST_CORE 0x10000000 /* Core reset */ 125 #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 126 #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 127 #define DBCR0_IC 0x08000000 /* 4: Instruction Completion debug event */ 128 #define DBCR0_BT 0x04000000 /* 5: Branch Taken debug event */ 129 #define DBCR0_EDE 0x02000000 /* 6: Exception Debug Event */ 130 #define DBCR0_TDE 0x01000000 /* 7: Trap Debug Event */ 131 #define DBCR0_IA1 0x00800000 /* 8: IAC (Instruction Address Compare) 1 debug event */ 132 #define DBCR0_IA2 0x00400000 /* 9: IAC 2 debug event */ 133 #define DBCR0_IA12 0x00200000 /* 10: Instruction Address Range Compare 1-2 */ 134 #define DBCR0_IA12X 0x00100000 /* 11: IA12 eXclusive */ 135 #define DBCR0_IA3 0x00080000 /* 12: IAC 3 debug event */ 136 #define DBCR0_DAC1_LOAD 0x00080000 /* 12: DAC (Data Address Compare) 1 load event (e500) */ 137 #define DBCR0_IA4 0x00040000 /* 13: IAC 4 debug event */ 138 #define DBCR0_DAC1_STORE 0x00040000 /* 13: DAC (Data Address Compare) 1 store event (e500) */ 139 #define DBCR0_IA34 0x00020000 /* 14: Instruction Address Range Compare 3-4 */ 140 #define DBCR0_DAC2_LOAD 0x00020000 /* 14: DAC 2 load event (e500) */ 141 #define DBCR0_IA34X 0x00010000 /* 15: IA34 eXclusive */ 142 #define DBCR0_DAC2_STORE 0x00010000 /* 15: DAC 2 store event (e500) */ 143 #define DBCR0_IA12T 0x00008000 /* 16: Instruction Address Range Compare 1-2 range Toggle */ 144 #define DBCR0_RET 0x00008000 /* 16: Return debug event (e500) */ 145 #define DBCR0_IA34T 0x00004000 /* 17: Instruction Address Range Compare 3-4 range Toggle */ 146 #define DBCR0_FT 0x00000001 /* 31: Freeze Timers on debug event */ 147 #define SPR_DBCR1 309 /* E... Debug Control Register 1 */ 148 #define SPR_DBCR2 310 /* E... Debug Control Register 2 */ 149 #define DBCR2_DAC1US 0xc0000000 /* 0-1: Data Address Compare 1 user/supervisor mode */ 150 #define DBCR2_DAC1US_ANY 0x00000000 /* MSR[PR] = don't care */ 151 #define DBCR2_DAC1US_KERNEL 0x80000000 /* MSR[PR] = 0 */ 152 #define DBCR2_DAC1US_USER 0xc0000000 /* MSR[PR] = 1 */ 153 #define DBCR2_DAC1ER 0x30000000 /* 2-3: Data Address Compare 1 effective/real mode */ 154 #define DBCR2_DAC1ER_REAL 0x00000000 /* real address */ 155 #define DBCR2_DAC1ER_DS0 0x20000000 /* effective address MSR[DS] = 0 */ 156 #define DBCR2_DAC1ER_DS1 0x30000000 /* effective address MSR[DS] = 1 */ 157 #define DBCR2_DAC2US 0x0c000000 /* 0-1: Data Address Compare 1 user/supervisor mode */ 158 #define DBCR2_DAC2US_ANY 0x00000000 /* MSR[PR] = don't care */ 159 #define DBCR2_DAC2US_KERNEL 0x08000000 /* MSR[PR] = 0 */ 160 #define DBCR2_DAC2US_USER 0x0c000000 /* MSR[PR] = 1 */ 161 #define DBCR2_DAC2ER 0x03000000 /* 2-3: Data Address Compare 1 effective/real mode */ 162 #define DBCR2_DAC2ER_REAL 0x00000000 /* real address */ 163 #define DBCR2_DAC2ER_DS0 0x02000000 /* effective address MSR[DS] = 0 */ 164 #define DBCR2_DAC2ER_DS1 0x03000000 /* effective address MSR[DS] = 1 */ 165 #define DBCR2_DAC12M 0x00c00000 /* 2-3: Data Address Compare 1 effective/real mode */ 166 #define DBCR2_DAC12M_EXACT 0x00000000 /* equal DAC1 or DAC2 */ 167 #define DBCR2_DAC12M_MASK 0x00400000 /* (addr & DAC2) == (DAC1 & DAC2) */ 168 #define DBCR2_DAC12M_INCLUSIVE 0x00800000 /* DAC1 <= addr < DAC2 */ 169 #define DBCR2_DAC12M_EXCLUSIVE 0x00c00000 /* addr < DAC1 || DAC2 <= addr */ 170 #define SPR_IAC1 312 /* E... Instruction Address Compare 1 */ 171 #define SPR_IAC2 313 /* E... Instruction Address Compare 2 */ 172 #define SPR_IAC3 314 /* E... Instruction Address Compare 3 */ 173 #define SPR_IAC4 315 /* E... Instruction Address Compare 4 */ 174 #define SPR_DAC1 316 /* E... Data Address Compare 1 */ 175 #define SPR_DAC2 317 /* E... Data Address Compare 2 */ 176 #define SPR_TSR 336 /* E... Timer Status Register */ 177 #define TSR_ENW 0x80000000 /* Enable Next Watchdog (W1C) */ 178 #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status (W1C) */ 179 #define TSR_WRS 0x30000000 /* Watchdog Reset Status (W1C) */ 180 #define TSR_DIS 0x08000000 /* Decementer Interrupt Status (W1C) */ 181 #define TSR_FIS 0x04000000 /* Fixed-interval Interrupt Status (W1C) */ 182 #define SPR_TCR 340 /* E... Timer Control Register */ 183 #define TCR_WP 0xc0000000 /* Watchdog Period */ 184 #define TCR_WP_2_N(n) (__SHIFTIN((n), TCR_WP) | __SHIFTIN((n) >> 2, TCR_WPEXT)) 185 #define TCR_WP_2_64 0x00000000 186 #define TCR_WP_2_1 0xc01e0000 187 #define TCR_WRC 0x30000000 /* Watchdog Timer Reset Control */ 188 #define TCR_WRC_RESET 0x20000000 189 #define TCR_WIE 0x08000000 /* Watchdog Time Interrupt Enable */ 190 #define TCR_DIE 0x04000000 /* Decremnter Interrupt Enable */ 191 #define TCR_FP 0x03000000 /* Fixed-interval Timer Period */ 192 #define TCR_FP_2_N(n) ((((64 - (n)) & 0x30) << 20) | (((64 - (n)) & 0xf) << 13)) 193 #define TCR_FP_2_64 0x00000000 194 #define TCR_FP_2_1 0x0301e000 195 #define TCR_FIE 0x00800000 /* Fixed-interval Interrupt Enable */ 196 #define TCR_ARE 0x00400000 /* Auto-reload Enable */ 197 #define TCR_WPEXT 0x001e0000 /* Watchdog Period Extension */ 198 #define TCR_FPEXT 0x0001e000 /* Fixed-interval Period Extension */ 199 200 #define SPR_IVOR0 400 /* E... Critical input interrupt offset */ 201 #define SPR_IVOR1 401 /* E... Machine check interrupt offset */ 202 #define SPR_IVOR2 402 /* E... Data storage interrupt offset */ 203 #define SPR_IVOR3 403 /* E... Instruction storage interrupt offset */ 204 #define SPR_IVOR4 404 /* E... External input interrupt offset */ 205 #define SPR_IVOR5 405 /* E... Alignment interrupt offset */ 206 #define SPR_IVOR6 406 /* E... Program interrupt offset */ 207 #define SPR_IVOR8 408 /* E... Syscall call interrupt offset */ 208 #define SPR_IVOR10 410 /* E... Decrementer interrupt offset */ 209 #define SPR_IVOR11 411 /* E... Fixed-interval timer interrupt offset */ 210 #define SPR_IVOR12 412 /* E... Watchdog timer interrupt offset */ 211 #define SPR_IVOR13 413 /* E... Data TLB error interrupt offset */ 212 #define SPR_IVOR14 414 /* E... Instruction TLB error interrupt offset */ 213 #define SPR_IVOR15 415 /* E... Debug interrupt offset */ 214 #define SPR_SPEFSCR 512 /* E... Signal processing and embedded floating-point status and control register */ 215 #define SPEFSCR_SOVH 0x80000000 /* 0: Summary Integer Overflow High */ 216 #define SPEFSCR_OVH 0x40000000 /* 1: Integer Overflow High */ 217 #define SPEFSCR_FGH 0x20000000 /* 2: Embedded Floating-Point Guard Bit High */ 218 #define SPEFSCR_FXH 0x10000000 /* 3: Embedded Floating-Point Sticky Bit High */ 219 #define SPEFSCR_FINVH 0x08000000 /* 4: Embedded Floating-Point Invalid Operation High */ 220 #define SPEFSCR_FDBZH 0x04000000 /* 5: Embedded Floating-Point Divide By Zero Error High */ 221 #define SPEFSCR_FUNFH 0x02000000 /* 6: Embedded Floating-Point Underflow Error High */ 222 #define SPEFSCR_FOVFH 0x01000000 /* 7: Embedded Floating-Point Overflow Error High */ 223 #define SPEFSCR_FINXS 0x00200000 /* 10: Embedded Floating-Point Inexact Sticky Bit */ 224 #define SPEFSCR_FINVS 0x00100000 /* 11: Embedded Floating-Point Invalid Operation Sticky Bit */ 225 #define SPEFSCR_FDBZS 0x00080000 /* 12: Embedded Floating-Point Divide By Zero Sticky Bit */ 226 #define SPEFSCR_FUNFS 0x00040000 /* 13: Embedded Floating-Point Underflow Sticky Bit */ 227 #define SPEFSCR_FOVFS 0x00020000 /* 14: Embedded Floating-Point Overflow Sticky Bit */ 228 #define SPEFSCR_MODE 0x00010000 /* 15: Embedded Floating-Point Mode */ 229 #define SPEFSCR_SOV 0x80000000 /* 16: Summary Integer Overflow */ 230 #define SPEFSCR_OV 0x00004000 /* 17: Integer Overflow */ 231 #define SPEFSCR_FG 0x00002000 /* 18: Embedded Floating-Point Guard Bit */ 232 #define SPEFSCR_FX 0x00001000 /* 19: Embedded Floating-Point Sticky Bit */ 233 #define SPEFSCR_FINV 0x00000800 /* 20: Embedded Floating-Point Invalid Operation */ 234 #define SPEFSCR_FDBZ 0x00000400 /* 21: Embedded Floating-Point Divide By Zero Error */ 235 #define SPEFSCR_FUNF 0x00000200 /* 22: Embedded Floating-Point Underflow Error */ 236 #define SPEFSCR_FOVF 0x00000100 /* 23: Embedded Floating-Point Overflow Error */ 237 #define SPEFSCR_FINXE 0x00000040 /* 25: Embedded Floating-Point Inexact Execption Enable */ 238 #define SPEFSCR_FINVE 0x00000020 /* 26: Embedded Floating-Point Invalid Operation/Input Error Execption Enable */ 239 #define SPEFSCR_FDBZE 0x00000010 /* 27: Embedded Floating-Point Divide By Zero Exception Enable */ 240 #define SPEFSCR_FUNFE 0x00000008 /* 28: Embedded Floating-Point Underflow Exception Enable */ 241 #define SPEFSCR_FOVFE 0x00000004 /* 29: Embedded Floating-Point Overflow Exception Enable */ 242 #define SPEFSCR_FRMC_MASK 0x00000003 /* 30..31: Embedded Floating-Point Rounding Mode Control */ 243 #define SPEFSCR_FRMC_DOWNWARD 0x00000003 /* Round toward -infinity */ 244 #define SPEFSCR_FRMC_UPWARD 0x00000002 /* Round toward +infinity */ 245 #define SPEFSCR_FRMC_TOWARDZERO 0x00000001 /* Round toward zero */ 246 #define SPEFSCR_FRMC_TONEAREST 0x00000000 /* Round to nearest */ 247 #define SPR_BBEAR 513 /* E... Brach buffer entry addr register */ 248 #define SPR_BBTAR 514 /* E... Brach buffer target addr register */ 249 #define SPR_L1CFG0 515 /* E... L1 Cache Configuration Register 0 */ 250 #define SPR_L1CFG1 516 /* E... L1 Cache Configuration Register 1 */ 251 #define L1CFG_CARCH_GET(n) (((n) >> 30) & 3) 252 #define L1CFG_CARCH_HARVARD 0 253 #define L1CFG_CARCH_UNIFIED 1 254 #define L1CFG_CBSIZE_GET(n) (((n) >> 23) & 3) 255 #define L1CFG_CBSIZE_32B 0 256 #define L1CFG_CBSIZE_64B 1 257 #define L1CFG_CREPL_GET(n) (((n) >> 21) & 3) 258 #define L1CFG_CREPL_TRUE_LRU 0 259 #define L1CFG_CREPL_PSEUDO_LRU 1 260 #define L1CFG_CLA_P(n) (((n) >> 20) & 1) 261 #define L1CFG_CPA_P(n) (((n) >> 19) & 1) 262 #define L1CFG_CNWAY_GET(n) ((((n) >> 11) & 0xff) + 1) 263 #define L1CFG_CSIZE_GET(n) ((((n) >> 0) & 0x7ff) << 10) 264 #define SPR_ATBL 526 /* E... Alternate Time Base Lower */ 265 #define SPR_ATBU 527 /* E... Alternate Time Base Upper */ 266 #define SPR_IVOR32 528 /* E... SPE unavailable interrupt offset */ 267 #define SPR_IVOR33 529 /* E... Floating-point data exception interrupt offset */ 268 #define SPR_IVOR34 530 /* E... Floating-point round exception interrupt offset */ 269 #define SPR_IVOR35 531 /* E... Performance monitor interrupt offset */ 270 #define SPR_MCARU 569 /* E... Machine check address register upper */ 271 #define SPR_MCSRR0 570 /* E... Machine check save/restore register 0 */ 272 #define SPR_MCSRR1 571 /* E... Machine check save/restore register 1 */ 273 #define SPR_MCSR 572 /* E... Machine check syndrome register */ 274 #define MCSR_MCP 0x80000000 /* 0: Machine Check Input Pin */ 275 #define MCSR_ICPERR 0x40000000 /* 1: Instruction Cache Parity Error */ 276 #define MCSR_DCP_PERR 0x20000000 /* 2: Data Cache Push Parity Error */ 277 #define MCSR_DCPERR 0x10000000 /* 3: Data Cache Parity Error */ 278 #define MCSR_NMI 0x00100000 /* 12: non maskable interrupt */ 279 #define MCSR_MAV 0x00080000 /* 13: MCAR address valid */ 280 #define MCSR_MEA 0x00040000 /* 14: MCAR [is an] effective address */ 281 #define MCSR_BUS_IAERR 0x00000080 /* 24: Bus Instruction Address Error */ 282 #define MCSR_BUS_RAERR 0x00000040 /* 25: Bus Read Address Error */ 283 #define MCSR_BUS_WAERR 0x00000020 /* 26: Bus Write Address Error */ 284 #define MCSR_BUS_IBERR 0x00000010 /* 27: Bus Instruction Data Bus Error */ 285 #define MCSR_BUS_RBERR 0x00000008 /* 28: Bus Read Data Bus Error */ 286 #define MCSR_BUS_WBERR 0x00000004 /* 29: Bus Write Data Bus Error */ 287 #define MCSR_BUS_IPERR 0x00000002 /* 30: Bus Instruction Parity Error */ 288 #define MCSR_BUS_RPERR 0x00000001 /* 31: Bus Read Parity Error */ 289 #define SPR_MCAR 573 /* E... Machine check address register */ 290 #define SPR_MAS0 624 /* E... MAS Register 0 */ 291 #define MAS0_TLBSEL 0x30000000 /* Select TLB<n> for access */ 292 #define MAS0_TLBSEL_TLB3 0x30000000 /* Select TLB3 for access */ 293 #define MAS0_TLBSEL_TLB2 0x20000000 /* Select TLB2 for access */ 294 #define MAS0_TLBSEL_TLB1 0x10000000 /* Select TLB1 for access */ 295 #define MAS0_TLBSEL_TLB0 0x00000000 /* Select TLB0 for access */ 296 #define MASX_TLBSEL_GET(n) (((n) >> 28) & 3) 297 #define MASX_TLBSEL_MAKE(n) (((n) & 3) << 28) 298 #define MAS0_ESEL 0x0fff0000 /* entry (way) select for tlbwe */ 299 #define MAS0_ESEL_GET(n) (((n) >> 16) & 4095) 300 #define MAS0_ESEL_MAKE(n) (((n) & 4095) << 16) 301 #define MAS0_NV 0x00000fff /* next victim fr TLB0[NV] */ 302 #define SPR_MAS1 625 /* E... MAS Register 1 */ 303 #define MAS1_V 0x80000000 /* TLB Valid Bit */ 304 #define MAS1_IPROT 0x40000000 /* Invalidate Protect */ 305 #define MAS1_TID 0x0fff0000 /* Translation Identity */ 306 #define MASX_TID_GET(n) (((n) >> 16) & 4095) 307 #define MASX_TID_MAKE(n) (((n) & 4095) << 16) 308 #define MAS1_TS 0x00001000 /* Translation Space [IS/DS MSR] */ 309 #define MAS1_TS_SHIFT 12 310 #define MAS1_TSIZE 0x00000f00 /* Translation Size (4KB**tsize) */ 311 #define MASX_TSIZE_4KB 0x00000100 /* 4KB TSIZE */ 312 #define MASX_TSIZE_16KB 0x00000200 /* 16KB TSIZE */ 313 #define MASX_TSIZE_64KB 0x00000300 /* 64KB TSIZE */ 314 #define MASX_TSIZE_256KB 0x00000400 /* 256KB TSIZE */ 315 #define MASX_TSIZE_1MB 0x00000500 /* 1MB TSIZE */ 316 #define MASX_TSIZE_4MB 0x00000600 /* 4MB TSIZE */ 317 #define MASX_TSIZE_16MB 0x00000700 /* 16MB TSIZE */ 318 #define MASX_TSIZE_64MB 0x00000800 /* 64MB TSIZE */ 319 #define MASX_TSIZE_256MB 0x00000900 /* 256MB TSIZE */ 320 #define MASX_TSIZE_1GB 0x00000a00 /* 1GB TSIZE */ 321 #define MASX_TSIZE_4GB 0x00000b00 /* 4GB TSIZE */ 322 #define MASX_TSIZE_GET(n) (((n) >> 8) & 15) 323 #define MASX_TSIZE_MAKE(n) (((n) & 15) << 8) 324 #define SPR_MAS2 626 /* E... MAS Register 2 */ 325 #define MAS2_EPN 0xfffff000 /* Effective Page Number */ 326 #define MAS2_EPN_GET(n) (((n) >> 12) & 1048575) 327 #define MAS2_EPN_MAKE(n) (((n) & 1048575) << 12) 328 #define MAS2_X0 0x00000040 /* Impl. dependent page attr. */ 329 #define MAS2_ACM 0x000000c0 /* Alternate Coherency Mode. */ 330 #define MAS2_X1 0x00000020 /* Impl. dependent page attr. */ 331 #define MAS2_VLE 0x00000020 /* VLE mode. */ 332 #define MAS2_WIMGE 0x0000001f /* Mask of next 5 bits */ 333 #define MAS2_W 0x00000010 /* Write-through */ 334 #define MAS2_I 0x00000008 /* cache-Inhibited */ 335 #define MAS2_M 0x00000004 /* Memory coherency required */ 336 #define MAS2_G 0x00000002 /* Gaurded */ 337 #define MAS2_E 0x00000001 /* [little] Endianness */ 338 #define SPR_MAS3 627 /* E... MAS Register 3 */ 339 #define MAS3_RPN 0xfffff000 /* Real Page Number */ 340 #define MAS3_RPN_GET(n) (((n) >> 12) & 1048575) 341 #define MAS3_RPN_MAKE(n) (((n) & 1048575) << 12) 342 #define MAS3_U0 0x00000200 /* User attribute 0 */ 343 #define MAS3_U1 0x00000100 /* User attribute 1 */ 344 #define MAS3_U2 0x00000080 /* User attribute 2 */ 345 #define MAS3_U3 0x00000040 /* User attribute 3 */ 346 #define MAS3_UX 0x00000020 /* User execute permission */ 347 #define MAS3_SX 0x00000010 /* System execute permission */ 348 #define MAS3_UW 0x00000008 /* User write permission */ 349 #define MAS3_SW 0x00000004 /* System write permission */ 350 #define MAS3_UR 0x00000002 /* User read permission */ 351 #define MAS3_SR 0x00000001 /* System read permission */ 352 #define SPR_MAS4 628 /* E... MAS Register 4 */ 353 #define MAS4_TLBSELD 0x30000000 /* TLBSEL default value */ 354 #define MAS4_TLBSEL_TLB3 0x30000000 /* Select TLB3 for access */ 355 #define MAS4_TLBSEL_TLB2 0x20000000 /* Select TLB2 for access */ 356 #define MAS4_TLBSEL_TLB1 0x10000000 /* Select TLB1 for access */ 357 #define MAS4_TLBSEL_TLB0 0x00000000 /* Select TLB0 for access */ 358 #define MAS4_TIDSELD 0x00030000 /* select TID default value */ 359 #define MAS4_TIDSELD_TIDZ 0x00030000 /* fill in MAS1[TID] with 0 */ 360 #define MAS4_TIDSELD_PID2 0x00020000 /* fill in MAS1[TAD] from ... */ 361 #define MAS4_TIDSELD_PID1 0x00010000 /* fill in MAS1[TAD] from ... */ 362 #define MAS4_TIDSELD_PID0 0x00000000 /* fill in MAS1[TAD] from ... */ 363 #define MAS4_TSIZED 0x00000f00 /* TSIZE default value */ 364 #define MAS4_TSIZED_4KB 0x00000100 /* 4KB TSIZE */ 365 #define MAS4_ACMD 0x000000c0 /* Alternate Coherency Mode. */ 366 #define MAS4_X0D 0x00000040 /* default Impl. dep. page attr. */ 367 #define MAS4_VLED 0x00000020 /* VLE mode. */ 368 #define MAS4_X1D 0x00000020 /* default Impl. dep. page attr. */ 369 #define MAS4_WD 0x00000010 /* default Write-through */ 370 #define MAS4_ID 0x00000008 /* default Cache-inhibited */ 371 #define MAS4_MD 0x00000004 /* default Memory coherency req. */ 372 #define MAS4_GD 0x00000002 /* default Gaurded */ 373 #define MAS4_ED 0x00000001 /* default [little] Endianness */ 374 #define SPR_MAS6 630 /* E... MAS Register 6 (TLB Seach CTX) */ 375 #define MAS6_SPID0 0x0fff0000 /* PID used with tlbsx */ 376 #define MAS6_SPID0_SHIFT 16 377 #define MAS6_SAS 0x00000001 /* Address space (IS/DS MSR) ... */ 378 #define MAS6_SAS_USER 0x00000001 /* Address space (IS/DS MSR) ... */ 379 #define SPR_PID1 633 /* E... PID Register 1 */ 380 #define SPR_PID2 634 /* E... PID Register 2 */ 381 #define SPR_TLB0CFG 688 /* E... TLB Configuration Register 0 */ 382 #define SPR_TLB1CFG 689 /* E... TLB Configuration Register 1 */ 383 #define TLBCFG_ASSOC(n) (((n) >> 24) & 0xff) /* assoc of tlb */ 384 #define TLBCFG_MINSIZE(n) (((n) >> 20) & 0x0f) /* minpagesize */ 385 #define TLBCFG_MAXSIZE(n) (((n) >> 16) & 0x0f) /* maxpagesize */ 386 #define TLBCFG_IPROT_P(n) (((n) >> 15) & 0x01) 387 #define TLBCFG_AVAIL_P(n) (((n) >> 14) & 0x01) /* variable page size */ 388 #define TLBCFG_NENTRY(n) (((n) >> 0) & 0xfff) /* # entrys */ 389 #define SPR_MAS7 944 /* E... MAS Register 7 */ 390 #define MAS7_RPNHI 0x00000004 /* bits 32-35 of RPN */ 391 #define SPR_HID0 1008 392 #define HID0_EMCP 0x80000000 /* Enable Machine Check Pin */ 393 #define HID0_DOZE 0x00800000 /* Core in doze mode */ 394 #define HID0_NAP 0x00400000 /* Core in nap mode */ 395 #define HID0_SLEEP 0x00200000 /* Core in sleep mode */ 396 #define HID0_TBEN 0x00004000 /* Time Base ENable */ 397 #define HID0_SEL_TBCLK 0x00002000 /* SELect Time Base Clock */ 398 #define HID0_EN_MAS7_UPDATE 0x00000080 /* ENable MAS7 UPDATE */ 399 #define HID0_DCFA 0x00000040 /* Data Cache Flush Assist */ 400 #define HID0_NOOPTI 0x00000001 /* NO-OP Touch Instructions */ 401 #define SPR_HID1 1009 402 #define SPR_L1CSR0 1010 /* E... L1 Cache Control and Status Register 0 (Data) */ 403 #define SPR_L1CSR1 1011 /* E... L1 Cache Control and Status Register 1 (Instruction) */ 404 #define L1CSR_CPE 0x00010000 /* 15: Cache Parity Error */ 405 #define L1CSR_CPI 0x00008000 /* 16: Cache Parity Injection Enable */ 406 #define L1CSR_CSLC 0x00000800 /* 20: Cache Snoop Lock Clear */ 407 #define L1CSR_CUL 0x00000400 /* 21: Cache Unable to Lock (W0C) */ 408 #define L1CSR_CLO 0x00000200 /* 22: Cache Lock Overflow (W0C) */ 409 #define L1CSR_CLFR 0x00000100 /* 23: Cache Lock Bits Flash Reset */ 410 #define L1CSR_CFI 0x00000002 /* 30: Cache Flash Invalidate */ 411 #define L1CSR_CE 0x00000001 /* 31: Cache Enable */ 412 #define SPR_MMUCSR0 1012 /* E... MMU Control and Status Register 0 */ 413 #define MMUCSR0_TLB2_FI 0x00000040 /* TLB2 Flash Invalidate */ 414 #define MMUCSR0_TLB3_FI 0x00000020 /* TLB3 Flash Invalidate */ 415 #define MMUCSR0_TLB0_FI 0x00000004 /* TLB0 Flash Invalidate */ 416 #define MMUCSR0_TLB1_FI 0x00000002 /* TLB1 Flash Invalidate */ 417 #define SPR_BUCSR 1013 /* E... Branch Unit Control and Status Register */ 418 #define SPR_MMUCFG 1015 /* E... MMU Configuration Register */ 419 #define MMUCFG_RASIZE_GET(n) (((n) >> 17) & 127) /* Real Address Size */ 420 #define MMUCFG_NPIDS_GET(n) (((n) >> 11) & 15) /* # of PID registers */ 421 #define MMUCFG_PIDSIZE_GET(n) (((n) >> 6) & 31) /* PID is PIDSIZE+1 bits wide */ 422 #define MMUCFG_NTLBS_GET(n) (((n) >> 2) & 3) /* NTLBS is max value of MAS0[TLBSEL] */ 423 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 424 #define MMUCFG_MAVN_V1 0 425 #define SPR_SVR 1023 /* E... System Version Register */ 426 427 #define PMR_PMC0 16 428 #define PMR_PMC1 17 429 #define PMR_PMC2 18 430 #define PMR_PMC3 19 431 #define PMR_PMLCa0 144 432 #define PMR_PMLCa1 145 433 #define PMR_PMLCa2 146 434 #define PMR_PMLCa3 147 435 #define PMLCa_FC 0x80000000 /* 0: Freeze Counter */ 436 #define PMLCa_FCS 0x40000000 /* 1: Freeze Counter In Super */ 437 #define PMLCa_FCU 0x20000000 /* 2: Freeze Counter In User */ 438 #define PMLCa_FCM1 0x10000000 /* 3: Freeze Counter While Mark=1 */ 439 #define PMLCa_FCM0 0x08000000 /* 4: Freeze Counter While Mark=0 */ 440 #define PMLCa_CE 0x04000000 /* 5: Condition Enable */ 441 #define PMLCa_EVENT 0x007f0000 /* 9..15: Event */ 442 #define PMLCa_EVENT_GET(n) (((n) >> 16) & 127) 443 #define PMLCa_EVENT_MAKE(n) (((n) & 127) << 16) 444 445 #define PMR_PMLCb0 272 446 #define PMR_PMLCb1 273 447 #define PMR_PMLCb2 274 448 #define PMR_PMLCb3 275 449 #define PMLCb_THRESHMUL 0x00007f00 /* 21..23: multiply threshold by 2**<n> */ 450 #define PMLCb_THRESHMUL_GET(n) (((n) >> 16) & 127) 451 #define PMLCb_THRESHMUL_MAKE(n) (((n) & 127) << 16) 452 #define PMLCb_THRESHOLD 0x0000003f /* 26..31: threshold */ 453 #define PMLCb_THRESHOLD_GET(n) (((n) >> 0) & 63) 454 #define PMLCb_THRESHOLD_MAKE(n) (((n) & 63) << 0) 455 #define PMR_PMGC0 400 456 #define PMGC0_FAC 0x80000000 /* 0: Freeze All Counters */ 457 #define PMGC0_PMIE 0x40000000 /* 1: Performance Monitor Interrupt Enable */ 458 #define PMGC0_FCECE 0x40000000 /* 1: Freeze count on enabled condition or event */ 459 #define PMGC0_TBSEL 0x00001800 /* 19..20: Time base selector */ 460 #define PMGC0_TBEE 0x00000100 /* 23: Time base transition event exception enable */ 461 462 #define PMR_UPMC0 (PMR_PMC0 - 16) 463 #define PMR_UPMC1 (PMR_PMC1 - 16) 464 #define PMR_UPMC2 (PMR_PMC2 - 16) 465 #define PMR_UPMC3 (PMR_PMC3 - 16) 466 #define PMR_UPMLCa0 (PMR_PMLCa0 - 16) 467 #define PMR_UPMLCa1 (PMR_PMLCa1 - 16) 468 #define PMR_UPMLCa2 (PMR_PMLCa2 - 16) 469 #define PMR_UPMLCa3 (PMR_PMLCa3 - 16) 470 #define PMR_UPMLCb0 (PMR_PMLCb0 - 16) 471 #define PMR_UPMLCb1 (PMR_PMLCb1 - 16) 472 #define PMR_UPMLCb2 (PMR_PMLCb2 - 16) 473 #define PMR_UPMLCb3 (PMR_PMLCb3 - 16) 474 #define PMR_UPMGC0 (PMR_PMGC0 - 16) 475 476 #endif /* !_POWERPC_BOOKE_SPR_H_ */ 477
Indexes created Thu Sep 25 16:09:42 GMT 2025