fenv.h revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: fenv.h,v 1.1.2.2 2015/12/27 12:09:40 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.1.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 1.1.2.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.1.2.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.1.2.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1.2.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.1.2.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll * 28 1.1.2.2 skrll * $FreeBSD: head/lib/msun/powerpc/fenv.h 226218 2011-10-10 15:43:09Z das $ 29 1.1.2.2 skrll */ 30 1.1.2.2 skrll 31 1.1.2.2 skrll #ifndef _POWERPC_FENV_H_ 32 1.1.2.2 skrll #define _POWERPC_FENV_H_ 33 1.1.2.2 skrll 34 1.1.2.2 skrll #include <sys/stdint.h> 35 1.1.2.2 skrll 36 1.1.2.2 skrll #ifndef __fenv_static 37 1.1.2.2 skrll #define __fenv_static static 38 1.1.2.2 skrll #endif 39 1.1.2.2 skrll 40 1.1.2.2 skrll typedef uint32_t fenv_t; 41 1.1.2.2 skrll typedef uint32_t fexcept_t; 42 1.1.2.2 skrll 43 1.1.2.2 skrll /* Exception flags */ 44 1.1.2.2 skrll #define FE_INEXACT 0x02000000 45 1.1.2.2 skrll #define FE_DIVBYZERO 0x04000000 46 1.1.2.2 skrll #define FE_UNDERFLOW 0x08000000 47 1.1.2.2 skrll #define FE_OVERFLOW 0x10000000 48 1.1.2.2 skrll #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 49 1.1.2.2 skrll 50 1.1.2.2 skrll /* 51 1.1.2.2 skrll * The PowerPC architecture has extra invalid flags that indicate the 52 1.1.2.2 skrll * specific type of invalid operation occurred. These flags may be 53 1.1.2.2 skrll * tested, set, and cleared---but not masked---separately. All of 54 1.1.2.2 skrll * these bits are cleared when FE_INVALID is cleared, but only 55 1.1.2.2 skrll * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 56 1.1.2.2 skrll */ 57 1.1.2.2 skrll #define FE_VXCVI 0x00000100 /* invalid integer convert */ 58 1.1.2.2 skrll #define FE_VXSQRT 0x00000200 /* square root of a negative */ 59 1.1.2.2 skrll #define FE_VXSOFT 0x00000400 /* software-requested exception */ 60 1.1.2.2 skrll #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 61 1.1.2.2 skrll #define FE_VXIMZ 0x00100000 /* inf * 0 */ 62 1.1.2.2 skrll #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 63 1.1.2.2 skrll #define FE_VXIDI 0x00400000 /* inf / inf */ 64 1.1.2.2 skrll #define FE_VXISI 0x00800000 /* inf - inf */ 65 1.1.2.2 skrll #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 66 1.1.2.2 skrll #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 67 1.1.2.2 skrll FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 68 1.1.2.2 skrll FE_VXSNAN | FE_INVALID) 69 1.1.2.2 skrll #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 70 1.1.2.2 skrll FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 71 1.1.2.2 skrll 72 1.1.2.2 skrll /* Rounding modes */ 73 1.1.2.2 skrll #define FE_TONEAREST 0x0000 74 1.1.2.2 skrll #define FE_TOWARDZERO 0x0001 75 1.1.2.2 skrll #define FE_UPWARD 0x0002 76 1.1.2.2 skrll #define FE_DOWNWARD 0x0003 77 1.1.2.2 skrll #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 78 1.1.2.2 skrll FE_UPWARD | FE_TOWARDZERO) 79 1.1.2.2 skrll 80 1.1.2.2 skrll #ifndef _KERNEL 81 1.1.2.2 skrll __BEGIN_DECLS 82 1.1.2.2 skrll 83 1.1.2.2 skrll /* Default floating-point environment */ 84 1.1.2.2 skrll extern const fenv_t __fe_dfl_env; 85 1.1.2.2 skrll #define FE_DFL_ENV (&__fe_dfl_env) 86 1.1.2.2 skrll 87 1.1.2.2 skrll /* We need to be able to map status flag positions to mask flag positions */ 88 1.1.2.2 skrll #define _FPUSW_SHIFT 22 89 1.1.2.2 skrll #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 90 1.1.2.2 skrll FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 91 1.1.2.2 skrll 92 1.1.2.2 skrll #ifndef _SOFT_FLOAT 93 1.1.2.2 skrll #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 94 1.1.2.2 skrll #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 95 1.1.2.2 skrll #else 96 1.1.2.2 skrll #define __mffs(__env) 97 1.1.2.2 skrll #define __mtfsf(__env) 98 1.1.2.2 skrll #endif 99 1.1.2.2 skrll 100 1.1.2.2 skrll union __fpscr { 101 1.1.2.2 skrll double __d; 102 1.1.2.2 skrll struct { 103 1.1.2.2 skrll uint32_t __junk; 104 1.1.2.2 skrll fenv_t __reg; 105 1.1.2.2 skrll } __bits; 106 1.1.2.2 skrll }; 107 1.1.2.2 skrll 108 1.1.2.2 skrll __fenv_static inline int 109 1.1.2.2 skrll feclearexcept(int __excepts) 110 1.1.2.2 skrll { 111 1.1.2.2 skrll union __fpscr __r; 112 1.1.2.2 skrll 113 1.1.2.2 skrll if (__excepts & FE_INVALID) 114 1.1.2.2 skrll __excepts |= FE_ALL_INVALID; 115 1.1.2.2 skrll __mffs(&__r.__d); 116 1.1.2.2 skrll __r.__bits.__reg &= ~__excepts; 117 1.1.2.2 skrll __mtfsf(__r.__d); 118 1.1.2.2 skrll return (0); 119 1.1.2.2 skrll } 120 1.1.2.2 skrll 121 1.1.2.2 skrll __fenv_static inline int 122 1.1.2.2 skrll fegetexceptflag(fexcept_t *__flagp, int __excepts) 123 1.1.2.2 skrll { 124 1.1.2.2 skrll union __fpscr __r; 125 1.1.2.2 skrll 126 1.1.2.2 skrll __mffs(&__r.__d); 127 1.1.2.2 skrll *__flagp = __r.__bits.__reg & __excepts; 128 1.1.2.2 skrll return (0); 129 1.1.2.2 skrll } 130 1.1.2.2 skrll 131 1.1.2.2 skrll __fenv_static inline int 132 1.1.2.2 skrll fesetexceptflag(const fexcept_t *__flagp, int __excepts) 133 1.1.2.2 skrll { 134 1.1.2.2 skrll union __fpscr __r; 135 1.1.2.2 skrll 136 1.1.2.2 skrll if (__excepts & FE_INVALID) 137 1.1.2.2 skrll __excepts |= FE_ALL_EXCEPT; 138 1.1.2.2 skrll __mffs(&__r.__d); 139 1.1.2.2 skrll __r.__bits.__reg &= ~__excepts; 140 1.1.2.2 skrll __r.__bits.__reg |= *__flagp & __excepts; 141 1.1.2.2 skrll __mtfsf(__r.__d); 142 1.1.2.2 skrll return (0); 143 1.1.2.2 skrll } 144 1.1.2.2 skrll 145 1.1.2.2 skrll __fenv_static inline int 146 1.1.2.2 skrll feraiseexcept(int __excepts) 147 1.1.2.2 skrll { 148 1.1.2.2 skrll union __fpscr __r; 149 1.1.2.2 skrll 150 1.1.2.2 skrll if (__excepts & FE_INVALID) 151 1.1.2.2 skrll __excepts |= FE_VXSOFT; 152 1.1.2.2 skrll __mffs(&__r.__d); 153 1.1.2.2 skrll __r.__bits.__reg |= __excepts; 154 1.1.2.2 skrll __mtfsf(__r.__d); 155 1.1.2.2 skrll return (0); 156 1.1.2.2 skrll } 157 1.1.2.2 skrll 158 1.1.2.2 skrll __fenv_static inline int 159 1.1.2.2 skrll fetestexcept(int __excepts) 160 1.1.2.2 skrll { 161 1.1.2.2 skrll union __fpscr __r; 162 1.1.2.2 skrll 163 1.1.2.2 skrll __mffs(&__r.__d); 164 1.1.2.2 skrll return (__r.__bits.__reg & __excepts); 165 1.1.2.2 skrll } 166 1.1.2.2 skrll 167 1.1.2.2 skrll __fenv_static inline int 168 1.1.2.2 skrll fegetround(void) 169 1.1.2.2 skrll { 170 1.1.2.2 skrll union __fpscr __r; 171 1.1.2.2 skrll 172 1.1.2.2 skrll __mffs(&__r.__d); 173 1.1.2.2 skrll return (__r.__bits.__reg & _ROUND_MASK); 174 1.1.2.2 skrll } 175 1.1.2.2 skrll 176 1.1.2.2 skrll __fenv_static inline int 177 1.1.2.2 skrll fesetround(int __round) 178 1.1.2.2 skrll { 179 1.1.2.2 skrll union __fpscr __r; 180 1.1.2.2 skrll 181 1.1.2.2 skrll if (__round & ~_ROUND_MASK) 182 1.1.2.2 skrll return (-1); 183 1.1.2.2 skrll __mffs(&__r.__d); 184 1.1.2.2 skrll __r.__bits.__reg &= ~_ROUND_MASK; 185 1.1.2.2 skrll __r.__bits.__reg |= __round; 186 1.1.2.2 skrll __mtfsf(__r.__d); 187 1.1.2.2 skrll return (0); 188 1.1.2.2 skrll } 189 1.1.2.2 skrll 190 1.1.2.2 skrll __fenv_static inline int 191 1.1.2.2 skrll fegetenv(fenv_t *__envp) 192 1.1.2.2 skrll { 193 1.1.2.2 skrll union __fpscr __r; 194 1.1.2.2 skrll 195 1.1.2.2 skrll __mffs(&__r.__d); 196 1.1.2.2 skrll *__envp = __r.__bits.__reg; 197 1.1.2.2 skrll return (0); 198 1.1.2.2 skrll } 199 1.1.2.2 skrll 200 1.1.2.2 skrll __fenv_static inline int 201 1.1.2.2 skrll feholdexcept(fenv_t *__envp) 202 1.1.2.2 skrll { 203 1.1.2.2 skrll union __fpscr __r; 204 1.1.2.2 skrll 205 1.1.2.2 skrll __mffs(&__r.__d); 206 1.1.2.2 skrll *__envp = __r.__d; 207 1.1.2.2 skrll __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 208 1.1.2.2 skrll __mtfsf(__r.__d); 209 1.1.2.2 skrll return (0); 210 1.1.2.2 skrll } 211 1.1.2.2 skrll 212 1.1.2.2 skrll __fenv_static inline int 213 1.1.2.2 skrll fesetenv(const fenv_t *__envp) 214 1.1.2.2 skrll { 215 1.1.2.2 skrll union __fpscr __r; 216 1.1.2.2 skrll 217 1.1.2.2 skrll __r.__bits.__reg = *__envp; 218 1.1.2.2 skrll __mtfsf(__r.__d); 219 1.1.2.2 skrll return (0); 220 1.1.2.2 skrll } 221 1.1.2.2 skrll 222 1.1.2.2 skrll __fenv_static inline int 223 1.1.2.2 skrll feupdateenv(const fenv_t *__envp) 224 1.1.2.2 skrll { 225 1.1.2.2 skrll union __fpscr __r; 226 1.1.2.2 skrll 227 1.1.2.2 skrll __mffs(&__r.__d); 228 1.1.2.2 skrll __r.__bits.__reg &= FE_ALL_EXCEPT; 229 1.1.2.2 skrll __r.__bits.__reg |= *__envp; 230 1.1.2.2 skrll __mtfsf(__r.__d); 231 1.1.2.2 skrll return (0); 232 1.1.2.2 skrll } 233 1.1.2.2 skrll 234 1.1.2.2 skrll #if defined(_NETBSD_SOURCE) || defined(_GNU_SOURCE) 235 1.1.2.2 skrll 236 1.1.2.2 skrll /* We currently provide no external definitions of the functions below. */ 237 1.1.2.2 skrll 238 1.1.2.2 skrll static inline int 239 1.1.2.2 skrll feenableexcept(int __mask) 240 1.1.2.2 skrll { 241 1.1.2.2 skrll union __fpscr __r; 242 1.1.2.2 skrll fenv_t __oldmask; 243 1.1.2.2 skrll 244 1.1.2.2 skrll __mffs(&__r.__d); 245 1.1.2.2 skrll __oldmask = __r.__bits.__reg; 246 1.1.2.2 skrll __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 247 1.1.2.2 skrll __mtfsf(__r.__d); 248 1.1.2.2 skrll return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 249 1.1.2.2 skrll } 250 1.1.2.2 skrll 251 1.1.2.2 skrll static inline int 252 1.1.2.2 skrll fedisableexcept(int __mask) 253 1.1.2.2 skrll { 254 1.1.2.2 skrll union __fpscr __r; 255 1.1.2.2 skrll fenv_t __oldmask; 256 1.1.2.2 skrll 257 1.1.2.2 skrll __mffs(&__r.__d); 258 1.1.2.2 skrll __oldmask = __r.__bits.__reg; 259 1.1.2.2 skrll __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 260 1.1.2.2 skrll __mtfsf(__r.__d); 261 1.1.2.2 skrll return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 262 1.1.2.2 skrll } 263 1.1.2.2 skrll 264 1.1.2.2 skrll static inline int 265 1.1.2.2 skrll fegetexcept(void) 266 1.1.2.2 skrll { 267 1.1.2.2 skrll union __fpscr __r; 268 1.1.2.2 skrll 269 1.1.2.2 skrll __mffs(&__r.__d); 270 1.1.2.2 skrll return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 271 1.1.2.2 skrll } 272 1.1.2.2 skrll 273 1.1.2.2 skrll #endif /* _NETBSD_SOURCE || _GNU_SOURCE */ 274 1.1.2.2 skrll 275 1.1.2.2 skrll __END_DECLS 276 1.1.2.2 skrll #endif 277 1.1.2.2 skrll 278 1.1.2.2 skrll #endif /* !_POWERPC_FENV_H_ */ 279
Indexes created Wed Oct 15 16:09:53 GMT 2025