fenv.h revision 1.1.2.2
1 /* $NetBSD: fenv.h,v 1.1.2.2 2015/12/27 12:09:40 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2004-2005 David Schultz <das (at) FreeBSD.ORG> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/lib/msun/powerpc/fenv.h 226218 2011-10-10 15:43:09Z das $ 29 */ 30 31 #ifndef _POWERPC_FENV_H_ 32 #define _POWERPC_FENV_H_ 33 34 #include <sys/stdint.h> 35 36 #ifndef __fenv_static 37 #define __fenv_static static 38 #endif 39 40 typedef uint32_t fenv_t; 41 typedef uint32_t fexcept_t; 42 43 /* Exception flags */ 44 #define FE_INEXACT 0x02000000 45 #define FE_DIVBYZERO 0x04000000 46 #define FE_UNDERFLOW 0x08000000 47 #define FE_OVERFLOW 0x10000000 48 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 49 50 /* 51 * The PowerPC architecture has extra invalid flags that indicate the 52 * specific type of invalid operation occurred. These flags may be 53 * tested, set, and cleared---but not masked---separately. All of 54 * these bits are cleared when FE_INVALID is cleared, but only 55 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 56 */ 57 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 58 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 59 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 60 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 61 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 62 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 63 #define FE_VXIDI 0x00400000 /* inf / inf */ 64 #define FE_VXISI 0x00800000 /* inf - inf */ 65 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 66 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 67 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 68 FE_VXSNAN | FE_INVALID) 69 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 70 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 71 72 /* Rounding modes */ 73 #define FE_TONEAREST 0x0000 74 #define FE_TOWARDZERO 0x0001 75 #define FE_UPWARD 0x0002 76 #define FE_DOWNWARD 0x0003 77 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 78 FE_UPWARD | FE_TOWARDZERO) 79 80 #ifndef _KERNEL 81 __BEGIN_DECLS 82 83 /* Default floating-point environment */ 84 extern const fenv_t __fe_dfl_env; 85 #define FE_DFL_ENV (&__fe_dfl_env) 86 87 /* We need to be able to map status flag positions to mask flag positions */ 88 #define _FPUSW_SHIFT 22 89 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 90 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 91 92 #ifndef _SOFT_FLOAT 93 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 94 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 95 #else 96 #define __mffs(__env) 97 #define __mtfsf(__env) 98 #endif 99 100 union __fpscr { 101 double __d; 102 struct { 103 uint32_t __junk; 104 fenv_t __reg; 105 } __bits; 106 }; 107 108 __fenv_static inline int 109 feclearexcept(int __excepts) 110 { 111 union __fpscr __r; 112 113 if (__excepts & FE_INVALID) 114 __excepts |= FE_ALL_INVALID; 115 __mffs(&__r.__d); 116 __r.__bits.__reg &= ~__excepts; 117 __mtfsf(__r.__d); 118 return (0); 119 } 120 121 __fenv_static inline int 122 fegetexceptflag(fexcept_t *__flagp, int __excepts) 123 { 124 union __fpscr __r; 125 126 __mffs(&__r.__d); 127 *__flagp = __r.__bits.__reg & __excepts; 128 return (0); 129 } 130 131 __fenv_static inline int 132 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 133 { 134 union __fpscr __r; 135 136 if (__excepts & FE_INVALID) 137 __excepts |= FE_ALL_EXCEPT; 138 __mffs(&__r.__d); 139 __r.__bits.__reg &= ~__excepts; 140 __r.__bits.__reg |= *__flagp & __excepts; 141 __mtfsf(__r.__d); 142 return (0); 143 } 144 145 __fenv_static inline int 146 feraiseexcept(int __excepts) 147 { 148 union __fpscr __r; 149 150 if (__excepts & FE_INVALID) 151 __excepts |= FE_VXSOFT; 152 __mffs(&__r.__d); 153 __r.__bits.__reg |= __excepts; 154 __mtfsf(__r.__d); 155 return (0); 156 } 157 158 __fenv_static inline int 159 fetestexcept(int __excepts) 160 { 161 union __fpscr __r; 162 163 __mffs(&__r.__d); 164 return (__r.__bits.__reg & __excepts); 165 } 166 167 __fenv_static inline int 168 fegetround(void) 169 { 170 union __fpscr __r; 171 172 __mffs(&__r.__d); 173 return (__r.__bits.__reg & _ROUND_MASK); 174 } 175 176 __fenv_static inline int 177 fesetround(int __round) 178 { 179 union __fpscr __r; 180 181 if (__round & ~_ROUND_MASK) 182 return (-1); 183 __mffs(&__r.__d); 184 __r.__bits.__reg &= ~_ROUND_MASK; 185 __r.__bits.__reg |= __round; 186 __mtfsf(__r.__d); 187 return (0); 188 } 189 190 __fenv_static inline int 191 fegetenv(fenv_t *__envp) 192 { 193 union __fpscr __r; 194 195 __mffs(&__r.__d); 196 *__envp = __r.__bits.__reg; 197 return (0); 198 } 199 200 __fenv_static inline int 201 feholdexcept(fenv_t *__envp) 202 { 203 union __fpscr __r; 204 205 __mffs(&__r.__d); 206 *__envp = __r.__d; 207 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 208 __mtfsf(__r.__d); 209 return (0); 210 } 211 212 __fenv_static inline int 213 fesetenv(const fenv_t *__envp) 214 { 215 union __fpscr __r; 216 217 __r.__bits.__reg = *__envp; 218 __mtfsf(__r.__d); 219 return (0); 220 } 221 222 __fenv_static inline int 223 feupdateenv(const fenv_t *__envp) 224 { 225 union __fpscr __r; 226 227 __mffs(&__r.__d); 228 __r.__bits.__reg &= FE_ALL_EXCEPT; 229 __r.__bits.__reg |= *__envp; 230 __mtfsf(__r.__d); 231 return (0); 232 } 233 234 #if defined(_NETBSD_SOURCE) || defined(_GNU_SOURCE) 235 236 /* We currently provide no external definitions of the functions below. */ 237 238 static inline int 239 feenableexcept(int __mask) 240 { 241 union __fpscr __r; 242 fenv_t __oldmask; 243 244 __mffs(&__r.__d); 245 __oldmask = __r.__bits.__reg; 246 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 247 __mtfsf(__r.__d); 248 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 249 } 250 251 static inline int 252 fedisableexcept(int __mask) 253 { 254 union __fpscr __r; 255 fenv_t __oldmask; 256 257 __mffs(&__r.__d); 258 __oldmask = __r.__bits.__reg; 259 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 260 __mtfsf(__r.__d); 261 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 262 } 263 264 static inline int 265 fegetexcept(void) 266 { 267 union __fpscr __r; 268 269 __mffs(&__r.__d); 270 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 271 } 272 273 #endif /* _NETBSD_SOURCE || _GNU_SOURCE */ 274 275 __END_DECLS 276 #endif 277 278 #endif /* !_POWERPC_FENV_H_ */ 279
Indexes created Wed Oct 15 16:09:53 GMT 2025