1 1.25 rin /* $NetBSD: fpu.h,v 1.25 2020/07/15 09:19:49 rin Exp $ */ 2 1.1 ws 3 1.1 ws /*- 4 1.1 ws * Copyright (C) 1996 Wolfgang Solfrank. 5 1.1 ws * Copyright (C) 1996 TooLs GmbH. 6 1.1 ws * All rights reserved. 7 1.1 ws * 8 1.1 ws * Redistribution and use in source and binary forms, with or without 9 1.1 ws * modification, are permitted provided that the following conditions 10 1.1 ws * are met: 11 1.1 ws * 1. Redistributions of source code must retain the above copyright 12 1.1 ws * notice, this list of conditions and the following disclaimer. 13 1.1 ws * 2. Redistributions in binary form must reproduce the above copyright 14 1.1 ws * notice, this list of conditions and the following disclaimer in the 15 1.1 ws * documentation and/or other materials provided with the distribution. 16 1.1 ws * 3. All advertising materials mentioning features or use of this software 17 1.1 ws * must display the following acknowledgement: 18 1.1 ws * This product includes software developed by TooLs GmbH. 19 1.1 ws * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 1.1 ws * derived from this software without specific prior written permission. 21 1.1 ws * 22 1.1 ws * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 1.1 ws * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 1.1 ws * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.1 ws * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 1.1 ws * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 1.1 ws * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 1.1 ws * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 1.1 ws * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 1.1 ws * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 1.1 ws * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 1.1 ws */ 33 1.23 rin 34 1.8 matt #ifndef _POWERPC_FPU_H_ 35 1.8 matt #define _POWERPC_FPU_H_ 36 1.1 ws 37 1.4 simonb #define FPSCR_FX 0x80000000 /* Exception Summary */ 38 1.4 simonb #define FPSCR_FEX 0x40000000 /* Enabled Exception Summary */ 39 1.4 simonb #define FPSCR_VX 0x20000000 /* Invalid Operation Exception Summary */ 40 1.4 simonb #define FPSCR_OX 0x10000000 /* Overflow Exception */ 41 1.4 simonb #define FPSCR_UX 0x08000000 /* Undrflow Exception */ 42 1.4 simonb #define FPSCR_ZX 0x04000000 /* Zero Divide Exception */ 43 1.4 simonb #define FPSCR_XX 0x02000000 /* Inexact Exception */ 44 1.4 simonb #define FPSCR_VXSNAN 0x01000000 /* Invalid Op (NAN) */ 45 1.4 simonb #define FPSCR_VXISI 0x00800000 /* Invalid Op (INF-INF) */ 46 1.4 simonb #define FPSCR_VXIDI 0x00400000 /* Invalid Op (INF/INF) */ 47 1.4 simonb #define FPSCR_VXZDZ 0x00200000 /* Invalid Op (0/0) */ 48 1.4 simonb #define FPSCR_VXIMZ 0x00100000 /* Invalid Op (INFx0) */ 49 1.4 simonb #define FPSCR_VXVC 0x00080000 /* Invalid Compare Op */ 50 1.4 simonb #define FPSCR_FR 0x00040000 /* Fraction Rounded */ 51 1.4 simonb #define FPSCR_FI 0x00020000 /* Fraction Inexact */ 52 1.19 kiyohara #define FPSCR_FPRF 0x0001f000 53 1.4 simonb #define FPSCR_C 0x00010000 /* FP Class Descriptor */ 54 1.2 danw #define FPSCR_FPCC 0x0000f000 55 1.4 simonb #define FPSCR_FL 0x00008000 /* < */ 56 1.4 simonb #define FPSCR_FG 0x00004000 /* > */ 57 1.4 simonb #define FPSCR_FE 0x00002000 /* == */ 58 1.4 simonb #define FPSCR_FU 0x00001000 /* unordered */ 59 1.4 simonb #define FPSCR_VXSOFT 0x00000400 /* Software Invalid Exception */ 60 1.4 simonb #define FPSCR_VXSQRT 0x00000200 /* Invalid Sqrt Exception */ 61 1.4 simonb #define FPSCR_VXCVI 0x00000100 /* Invalid Op Integer Cvt Exception */ 62 1.4 simonb #define FPSCR_VE 0x00000080 /* Invalid Op Exception Enable */ 63 1.4 simonb #define FPSCR_OE 0x00000040 /* Overflow Exception Enable */ 64 1.4 simonb #define FPSCR_UE 0x00000020 /* Underflow Exception Enable */ 65 1.4 simonb #define FPSCR_ZE 0x00000010 /* Zero Divide Exception Enable */ 66 1.4 simonb #define FPSCR_XE 0x00000008 /* Inexact Exception Enable */ 67 1.4 simonb #define FPSCR_NI 0x00000004 /* Non-IEEE Mode Enable */ 68 1.2 danw #define FPSCR_RN 0x00000003 69 1.3 briggs 70 1.3 briggs #ifdef _KERNEL 71 1.6 jdolecek 72 1.23 rin #ifdef _KERNEL_OPT 73 1.4 simonb #include "opt_ppcarch.h" 74 1.6 jdolecek #endif 75 1.4 simonb 76 1.18 matt #include <sys/pcu.h> 77 1.18 matt #include <powerpc/mcontext.h> 78 1.18 matt 79 1.18 matt struct lwp; 80 1.18 matt bool fpu_used_p(struct lwp *); 81 1.18 matt void fpu_mark_used(struct lwp *); 82 1.18 matt 83 1.18 matt void fpu_restore_from_mcontext(struct lwp *, const mcontext_t *); 84 1.18 matt bool fpu_save_to_mcontext(struct lwp *, mcontext_t *, unsigned int *); 85 1.18 matt 86 1.25 rin int fpu_get_fault_code(void); 87 1.25 rin 88 1.18 matt extern const pcu_ops_t fpu_ops; 89 1.18 matt 90 1.4 simonb /* List of PowerPC architectures that support FPUs. */ 91 1.15 sanjayl #if defined(PPC_OEA) || defined (PPC_OEA64) || defined (PPC_OEA64_BRIDGE) 92 1.4 simonb #define PPC_HAVE_FPU 93 1.4 simonb 94 1.17 matt struct fpreg; 95 1.17 matt 96 1.22 christos static __inline void 97 1.18 matt fpu_load(void) 98 1.18 matt { 99 1.18 matt pcu_load(&fpu_ops); 100 1.18 matt } 101 1.18 matt 102 1.22 christos static __inline void 103 1.21 chs fpu_save(lwp_t *l) 104 1.18 matt { 105 1.21 chs pcu_save(&fpu_ops, l); 106 1.18 matt } 107 1.18 matt 108 1.22 christos static __inline void 109 1.21 chs fpu_discard(lwp_t *l) 110 1.18 matt { 111 1.21 chs pcu_discard(&fpu_ops, l, false); 112 1.18 matt } 113 1.18 matt 114 1.18 matt void fpu_load_from_fpreg(const struct fpreg *); 115 1.18 matt void fpu_unload_to_fpreg(struct fpreg *); 116 1.13 matt 117 1.4 simonb #endif /* PPC_HAVE_FPU */ 118 1.4 simonb #endif /* _KERNEL */ 119 1.1 ws 120 1.8 matt #endif /* _POWERPC_FPU_H_ */ 121