amcc460ex.h revision 1.1
1 /* $NetBSD: amcc460ex.h,v 1.1 2026/06/13 19:45:50 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012, 2014, 2024, 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * AMCC/AppliedMicro 460EX system-on-chip 33 */ 34 35 #ifndef _IBM4XX_AMCC460EX_H_ 36 #define _IBM4XX_AMCC460EX_H_ 37 38 /* Upper 4 bits (ERPN) of the physical address of the I/O region */ 39 #define AMCC460EX_OPB_PA_HIGH 0x4 40 41 #define AMCC460EX_OPB_BASE 0xef600000 42 43 #define AMCC460EX_UART0_BASE 0xef600300 44 #define AMCC460EX_UART1_BASE 0xef600400 45 #define AMCC460EX_UART2_BASE 0xef600500 46 #define AMCC460EX_UART3_BASE 0xef600600 47 #define AMCC460EX_IIC0_BASE 0xef600700 48 #define AMCC460EX_IIC1_BASE 0xef600800 49 #define AMCC460EX_GPIO0_BASE 0xef600b00 50 #define AMCC460EX_ZMII0_BASE 0xef600d00 51 #define AMCC460EX_EMAC0_BASE 0xef600e00 52 #define AMCC460EX_EMAC1_BASE 0xef600f00 53 #define AMCC460EX_TAH0_BASE 0xef601350 54 #define AMCC460EX_TAH1_BASE 0xef601450 55 #define AMCC460EX_RGMII0_BASE 0xef601500 56 57 /* UARTs get freq from external 11.0592 MHz osc */ 58 #define AMCC460EX_COM_FREQ 11059200 59 60 /* 61 * PLB-PCIX host bridge. 62 */ 63 #define AMCC460EX_PCIX0_CFG_PLBA 0x0ec00000 /* ERPN 0xc */ 64 #define AMCC460EX_PCIX0_REGS_PLBA 0x0ec80000 /* ERPN 0xc */ 65 #define AMCC460EX_PCIX0_CFG_PA_HIGH 0xc 66 #define AMCC460EX_PCIX0_IO_PLBA 0x08000000 /* ERPN 0xc */ 67 #define AMCC460EX_PCIX0_IO_PA_HIGH 0xc 68 #define AMCC460EX_PCIX0_MEM_BASE 0x80000000 /* ERPN 0xd */ 69 #define AMCC460EX_PCIX0_MEM_PLBA_H 0xd 70 /* How much of the (128MB) outbound memory window has pinned mappings */ 71 #define AMCC460EX_PCIX0_MEM_SIZE 0x05000000 /* 80MB */ 72 73 /* 74 * PCI Express root complexes (PCIE0/PCIE1). 75 */ 76 #define AMCC460EX_PCIE0_DCR_BASE 0x100 /* PEGPL register block */ 77 #define AMCC460EX_PCIE1_DCR_BASE 0x120 78 79 #define AMCC460EX_PCIE_CFG_PA_HIGH 0xd /* ERPN of config windows */ 80 #define AMCC460EX_PCIE0_CFG_PLBA 0x30000000 81 #define AMCC460EX_PCIE1_CFG_PLBA 0x38000000 82 #define AMCC460EX_PCIE_CFG_SIZE 0x01000000 /* buses 0-15 */ 83 84 #define AMCC460EX_PCIE_MEM_PA_HIGH 0xe /* ERPN of memory windows */ 85 #define AMCC460EX_PCIE0_MEM_PLBA 0x10000000 86 #define AMCC460EX_PCIE1_MEM_PLBA 0x90000000 87 #define AMCC460EX_PCIE_MEM_BASE 0xa0000000 /* PCI-side base */ 88 #define AMCC460EX_PCIE_MEM_SIZE 0x01000000 89 90 /* INTA-INTD, flat irq numbers (UIC3 bits 12-15 and 16-19) */ 91 #define AMCC460EX_PCIE0_INTA_IRQ 108 92 #define AMCC460EX_PCIE1_INTA_IRQ 112 93 94 /* 95 * AHB peripherals (USB). 96 */ 97 #define AMCC460EX_AHB_PA_HIGH 0x4 /* ERPN */ 98 #define AMCC460EX_AHB_BASE 0xbf000000 99 #define AMCC460EX_AHB_SIZE 0x01000000 100 101 #define AMCC460EX_USB_OTG_BASE 0xbff80000 /* DWC OTG, 256KB */ 102 #define AMCC460EX_USB_OTG_SIZE 0x00040000 103 #define AMCC460EX_USB_OHCI_BASE 0xbffd0000 104 #define AMCC460EX_USB_OHCI_SIZE 0x00000400 105 #define AMCC460EX_USB_EHCI_BASE 0xbffd0400 106 #define AMCC460EX_USB_EHCI_SIZE 0x00000400 107 108 /* 109 * On-chip SATA, the lousy DWC SATA-II core 110 */ 111 #define AMCC460EX_SATA_DMA_BASE 0xbffd0800 112 #define AMCC460EX_SATA_DMA_SIZE 0x00000400 113 #define AMCC460EX_SATA_BASE 0xbffd1000 114 #define AMCC460EX_SATA_SIZE 0x00000800 115 116 /* 117 * Per-port PCIe SDR registers 118 */ 119 #define AMCC460EX_PESDR0_LOOP 0x303 120 #define AMCC460EX_PESDR0_RCSSET 0x304 121 #define AMCC460EX_PESDR0_RCSSTS 0x305 122 #define AMCC460EX_PESDR1_LOOP 0x343 123 #define AMCC460EX_PESDR1_RCSSET 0x344 124 #define AMCC460EX_PESDR1_RCSSTS 0x345 125 126 #define AMCC460EX_PESDR_LOOP_LNKUP 0x00001000 /* link trained */ 127 128 /* 129 * Interrupt numbers in the flat PIC space: 130 * UIC0 : irqs 0-31 131 * UIC1 : cascaded via UIC0 bit 30) is irqs 32-63 132 * UIC2 : (UIC0 bit 10) is irqs 64-95 133 * UIC3 : (UIC0 bit 16) is irqs 96-127 134 */ 135 #define AMCC460EX_UART0_IRQ 33 /* UIC1 bit 1 */ 136 #define AMCC460EX_UART1_IRQ 1 /* UIC0 bit 1 */ 137 #define AMCC460EX_IIC0_IRQ 2 /* UIC0 bit 2 */ 138 #define AMCC460EX_IIC1_IRQ 3 /* UIC0 bit 3 */ 139 #define AMCC460EX_PCI_IRQ 32 /* UIC1 bit 0: PCI INTA */ 140 #define AMCC460EX_MAL_TXEOB_IRQ 70 /* UIC2 bit 6 */ 141 #define AMCC460EX_MAL_RXEOB_IRQ 71 /* UIC2 bit 7 */ 142 #define AMCC460EX_EMAC0_IRQ 80 /* UIC2 bit 16 */ 143 #define AMCC460EX_EMAC1_IRQ 81 /* UIC2 bit 17 */ 144 #define AMCC460EX_USB_EHCI_IRQ 93 /* UIC2 bit 29 */ 145 #define AMCC460EX_USB_OHCI_IRQ 94 /* UIC2 bit 30 */ 146 #define AMCC460EX_SATA_IRQ 96 /* UIC3 bit 0 */ 147 #define AMCC460EX_SATA_DMA_IRQ 101 /* UIC3 bit 5: AHB DMAC */ 148 149 #endif /* _IBM4XX_AMCC460EX_H_ */ 150
Indexes created Tue Jul 07 00:25:39 UTC 2026