ibm405gp.h revision 1.6
1 /* $NetBSD: ibm405gp.h,v 1.6 2002/08/11 13:32:20 simonb Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _IBM4XX_IBM405GP_H_ 39 #define _IBM4XX_IBM405GP_H_ 40 41 /* 42 * Memory and PCI addresses 43 */ 44 45 /* Local Memory and Peripherals */ 46 #define LOCAL_MEM_START 0x00000000 47 #define LOCAL_MEM_END 0x7fffffff 48 49 /* PCI Memory - 1.625GB */ 50 #define PCI_MEM_START 0x80000000 51 #define PCI_MEM_END 0xe7ffffff 52 53 /* PCI I/O - PCI I/O accesses from 0 to 64kB-1 (64kB) */ 54 #define PCI_IO_LOW_START 0xe8000000 55 #define PCI_IO_LOW_END 0xe800ffff 56 57 /* PCI I/O - PCI I/O accesses from 8MB to 64MB-1 (56MB) */ 58 #define PCI_IO_HIGH_START 0xe8800000 59 #define PCI_IO_HIGH_END 0xebffffff 60 61 /* PCI Configuaration Registers */ 62 #define PCIC0_BASE 0xeec00000 63 #define PCIC0_CFGADDR 0x00 64 #define PCIC0_CFGDATA 0x04 65 66 #define PCIC0_VENDID 0x00 67 #define PCIC0_DEVID 0x02 68 #define PCIC0_CMD 0x04 69 #define PCIC0_STATUS 0x06 70 #define PCIC0_REVID 0x08 71 #define PCIC0_CLS 0x09 72 #define PCIC0_CACHELS 0x0c 73 #define PCIC0_LATTIM 0x0d 74 #define PCIC0_HDTYPE 0x0e 75 #define PCIC0_BIST 0x0f 76 #define PCIC0_BAR0 0x10 77 #define PCIC0_BAR1 0x14 /* PCI name */ 78 #define PCIC0_PTM1BAR PCIC0_BAR1 /* 405GP name */ 79 #define PCIC0_BAR2 0x18 /* PCI name */ 80 #define PCIC0_PTM2BAR PCIC0_BAR2 /* 405GP name */ 81 #define PCIC0_BAR3 0x1C 82 #define PCIC0_BAR4 0x20 83 #define PCIC0_BAR5 0x24 84 #define PCIC0_SBSYSVID 0x2c 85 #define PCIC0_SBSYSID 0x2e 86 #define PCIC0_CAP 0x34 87 #define PCIC0_INTLN 0x3c 88 #define PCIC0_INTPN 0x3d 89 #define PCIC0_MINGNT 0x3e 90 #define PCIC0_MAXLTNCY 0x3f 91 92 #define PCIC0_ICS 0x44 /* 405GP specific parameters */ 93 #define PCIC0_ERREN 0x48 94 #define PCIC0_ERRSTS 0x49 95 #define PCIC0_BRDGOPT1 0x4a 96 #define PCIC0_PLBBESR0 0x4c 97 #define PCIC0_PLBBESR1 0x50 98 #define PCIC0_PLBBEAR 0x54 99 #define PCIC0_CAPID 0x58 100 #define PCIC0_NEXTIPTR 0x59 101 #define PCIC0_PMC 0x5a 102 #define PCIC0_PMCSR 0x5c 103 #define PCIC0_PMCSRBSE 0x5e 104 #define PCIC0_DATA 0x5f 105 #define PCIC0_BRDGOPT2 0x60 106 #define PCIC0_PMSCRR 0x64 107 108 109 /* PCI Interrupt Acknowledge (read: 0xeed00000 0xeed00003 - 4 bytes) */ 110 #define PCIIA0 0xeed00000 111 112 /* PCI Special Cycle (write: 0xeed00000 0xeed00003 - 4 bytes) */ 113 #define PCISC0 0xeed00000 114 115 /* PCI Bridge Local Configuation Registers (0xef400000 0xef40003f - 64 bytes) */ 116 #define PCIL0_BASE 0xef400000 117 #define PCIL0_PMM0LA 0x00 /* PCI Master Map 0: Local Address */ 118 #define PCIL0_PMM0MA 0x04 /* Mask/Attribute */ 119 #define PCIL0_PMM0PCILA 0x08 /* PCI Low Address */ 120 #define PCIL0_PMM0PCIHA 0x0c /* PCI High Address */ 121 #define PCIL0_PMM1LA 0x10 122 #define PCIL0_PMM1MA 0x14 123 #define PCIL0_PMM1PCILA 0x18 124 #define PCIL0_PMM1PCIHA 0x1c 125 #define PCIL0_PMM2LA 0x20 126 #define PCIL0_PMM2MA 0x24 127 #define PCIL0_PMM2PCILA 0x28 128 #define PCIL0_PMM2PCIHA 0x2c 129 #define PCIL0_PTM1MS 0x30 130 #define PCIL0_PTM1LA 0x34 131 #define PCIL0_PTM2MS 0x38 132 #define PCIL0_PTM2LA 0x3c 133 134 /* 135 * Internal Peripherals 136 */ 137 138 /* UART0 Registers */ 139 #define UART0_BASE 0xef600300 140 #define UART0_RBR 0x00 /* R Receiver Buffer Register */ 141 #define UART0_THR 0x00 /* W Transmitter Holding Register */ 142 #define UART0_IER 0x01 /* R/W Interrupt Enable Register */ 143 #define UART0_IIR 0x02 /* R Interrupt Identification Register */ 144 #define UART0_FCR 0x02 /* W FIFO Control Register */ 145 #define UART0_LCR 0x03 /* R/W Line Control Register */ 146 #define UART0_MCR 0x04 /* R/W Modem Control Register */ 147 #define UART0_LSR 0x05 /* R/W Line Status Register */ 148 #define UART0_MSR 0x06 /* R/W Modem Status Register */ 149 #define UART0_SCR 0x07 /* R/W Scratch Register */ 150 #define UART0_DLL 0x00 /* R/W* Divisor Latch (LSB) */ 151 #define UART0_DLM 0x01 /* R/W* Divisor Latch (MSB) */ 152 153 /* UART1 Registers */ 154 #define UART1_BASE 0xef600400 155 #define UART1_RBR UART0_RBR /* R Receiver Buffer Register */ 156 #define UART1_THR UART0_THR /* W Transmitter Holding Register */ 157 #define UART1_IER UART0_IER /* R/W Interrupt Enable Register */ 158 #define UART1_IIR UART0_IIR /* R Interrupt Identification Register */ 159 #define UART1_FCR UART0_FCR /* W FIFO Control Register */ 160 #define UART1_LCR UART0_LCR /* R/W Line Control Register */ 161 #define UART1_MCR UART0_MCR /* R/W Modem Control Register */ 162 #define UART1_LSR UART0_LSR /* R/W Line Status Register */ 163 #define UART1_MSR UART0_MSR /* R/W Modem Status Register */ 164 #define UART1_SCR UART0_SCR /* R/W Scratch Register */ 165 #define UART1_DLL UART0_DLL /* R/W* Divisor Latch (LSB) */ 166 #define UART1_DLM UART0_DLM /* R/W* Divisor Latch (MSB) */ 167 168 /* IIC Registers */ 169 #define IIC0_BASE 0xef600500 170 #define IIC0_MDBUF 0x00 /* Master Data Buffer */ 171 #define IIC0_SDBUF 0x02 /* Slave Data Buffer */ 172 #define IIC0_LMADR 0x04 /* Low Master Address */ 173 #define IIC0_HMADR 0x05 /* High Master Address */ 174 #define IIC0_CNTL 0x06 /* Control */ 175 #define IIC0_MDCNTL 0x07 /* Mode Control */ 176 #define IIC0_STS 0x08 /* Status */ 177 #define IIC0_EXTSTS 0x09 /* Extended Status */ 178 #define IIC0_LSADR 0x0a /* Low Slave Address */ 179 #define IIC0_HSADR 0x0b /* High Slave Address */ 180 #define IIC0_CLKDIV 0x0c /* Clock Divide */ 181 #define IIC0_INTRMSK 0x0d /* Interrupt Mask */ 182 #define IIC0_XFRCNT 0x0e /* Transfer Count */ 183 #define IIC0_XTCNTLSS 0x0f /* Extended Control and Slave Status */ 184 #define IIC0_DIRECTCNTL 0x10 /* Direct Control */ 185 186 /* OPB Arbiter Registers */ 187 #define OPBA0_BASE 0xef600600 188 #define OPBA0_PR 0x00 /* Priority Register */ 189 #define OPBA0_CR 0x01 /* Control Register */ 190 191 /* GPIO Registers */ 192 #define GPIO0_BASE 0xef600700 193 #define GPIO0_OR 0x00 /* Output */ 194 #define GPIO0_TCR 0x04 /* Three-State Control */ 195 #define GPIO0_ODR 0x18 /* Open Drain */ 196 #define GPIO0_IR 0x1c /* Input */ 197 198 /* Ethernet MAC Registers */ 199 #define EMAC0_BASE 0xef600800 200 201 #define EMAC0_MR0 0x00 /* Mode Register 0 */ 202 #define MR0_RXI 0x80000000 /* Receive MAC Idle */ 203 #define MR0_TXI 0x40000000 /* Transmit MAC Idle */ 204 #define MR0_SRST 0x20000000 /* Soft Reset */ 205 #define MR0_TXE 0x10000000 /* Transmit MAC Enable */ 206 #define MR0_RXE 0x08000000 /* Receive MAC Enable */ 207 #define MR0_WKE 0x04000000 /* Wake-up Enable */ 208 209 #define EMAC0_MR1 0x04 /* Mode Register 1 */ 210 #define MR1_FDE 0x80000000 /* Full-Duplex Enable */ 211 #define MR1_ILE 0x40000000 /* Internal Loop-back Enable */ 212 #define MR1_VLE 0x20000000 /* VLAN Enable */ 213 #define MR1_EIFC 0x10000000 /* Enable Integrated Flow Control */ 214 #define MR1_APP 0x08000000 /* Allow Pause Packet */ 215 #define MR1_IST 0x01000000 /* Ignore SQE Test */ 216 #define MR1_MF_MASK 0x00c00000 /* Medium Frequency mask */ 217 #define MR1_MF_10MBS 0x00000000 /* 10MB/sec */ 218 #define MR1_MF_100MBS 0x00400000 /* 100MB/sec */ 219 #define MR1_RFS_MASK 0x00300000 /* Receive FIFO size */ 220 #define MR1_RFS_512 0x00000000 /* 512 bytes */ 221 #define MR1_RFS_1KB 0x00100000 /* 1kByte */ 222 #define MR1_RFS_2KB 0x00200000 /* 2kByte */ 223 #define MR1_RFS_4KB 0x00300000 /* 4kByte */ 224 #define MR1_TFS_MASK 0x000c0000 /* Transmit FIFO size */ 225 #define MR1_TFS_1KB 0x00040000 /* 1kByte */ 226 #define MR1_TFS_2KB 0x00080000 /* 2kByte */ 227 #define MR1_TR0_MASK 0x00018000 /* Transmit Request 0 */ 228 #define MR1_TR0_SINGLE 0x00000000 /* Single Packet mode */ 229 #define MR1_TR0_MULTIPLE 0x00008000 /* Multiple Packet mode */ 230 #define MR1_TR0_DEPENDANT 0x00010000 /* Dependent Mode */ 231 #define MR1_TR1_MASK 0x00006000 /* Transmit Request 1 */ 232 #define MR1_TR1_SINGLE 0x00000000 /* Single Packet mode */ 233 #define MR1_TR1_MULTIPLE 0x00002000 /* Multiply Packet mode */ 234 #define MR1_TR1_DEPENDANT 0x00004000 /* Dependent Mode */ 235 236 #define EMAC0_TMR0 0x08 /* Transmit Mode Register 0 */ 237 #define TMR0_GNP0 0x80000000 /* Get New Packet for Channel 0 */ 238 #define TMR0_GNP1 0x40000000 /* Get New Packet for Channel 1 */ 239 #define TMR0_GNPD 0x20000000 /* Get New Packet for Dependent mode */ 240 #define TMR0_FC_MASK 0x10000000 /* First Channel */ 241 #define TMR0_FC_CHAN0 0x00000000 /* Channel 0 */ 242 #define TMR0_FC_CHAN1 0x10000000 /* Channel 1 */ 243 244 #define EMAC0_TMR1 0x0c /* Transmit Mode Register 1 */ 245 #define TMR1_TLR_MASK 0xf8000000 /* Transmit Low Request */ 246 #define TMR1_TLR_SHIFT 27 247 #define TMR1_TUR_MASK 0x00ff0000 /* Transmit Urgent Request */ 248 #define TMR1_TUR_SHIFT 16 249 250 #define EMAC0_RMR 0x10 /* Receive Mode Register */ 251 #define RMR_SP 0x80000000 /* Strip Padding */ 252 #define RMR_SFCS 0x40000000 /* Strip FCS */ 253 #define RMR_RRP 0x20000000 /* Receive Runt Packets */ 254 #define RMR_RFP 0x10000000 /* Receive FCS Packets */ 255 #define RMR_ROP 0x08000000 /* Receive Oversize Packets */ 256 #define RMR_RPIR 0x04000000 /* Receive Packets with In Range Error */ 257 #define RMR_PPP 0x02000000 /* Propagate Pause Packet */ 258 #define RMR_PME 0x01000000 /* Promiscuous Mode Enable */ 259 #define RMR_PMME 0x00800000 /* Promiscuous Multicast Mode Enable */ 260 #define RMR_IAE 0x00400000 /* Individual Address Enable */ 261 #define RMR_MIAE 0x00200000 /* Multiple Individual Address Enable */ 262 #define RMR_BAE 0x00100000 /* Broadcast Address Enable */ 263 #define RMR_MAE 0x00080000 /* Multicast Address Enable */ 264 265 #define EMAC0_ISR 0x14 /* Interrupt Status Register */ 266 #define ISR_OVR 0x02000000 /* Overrun Error */ 267 #define ISR_PP 0x01000000 /* Pause Packet */ 268 #define ISR_BP 0x00800000 /* Bad Packet */ 269 #define ISR_RP 0x00400000 /* Runt Packet */ 270 #define ISR_SE 0x00200000 /* Short Event */ 271 #define ISR_ALE 0x00100000 /* Alignment Error */ 272 #define ISR_BFCS 0x00080000 /* Bad FCS */ 273 #define ISR_PTLE 0x00040000 /* Packet Too Long Error */ 274 #define ISR_ORE 0x00020000 /* Out of Range Error */ 275 #define ISR_IRE 0x00010000 /* In Range Error */ 276 #define ISR_DBDM 0x00000200 /* Dead Bit Dependent Mode */ 277 #define ISR_DB0 0x00000100 /* Dead Bit 0 */ 278 #define ISR_SE0 0x00000080 /* SQE Error 0 */ 279 #define ISR_TE0 0x00000040 /* Transmit Error 0 */ 280 #define ISR_DB1 0x00000020 /* Dead Bit 1 */ 281 #define ISR_SE1 0x00000010 /* SQE Error 1 */ 282 #define ISR_TE1 0x00000008 /* Transmit Error 1 */ 283 #define ISR_MOS 0x00000002 /* MMA Operation Succeeded */ 284 #define ISR_MOF 0x00000001 /* MMA Operation Failed */ 285 286 #define EMAC0_ISER 0x18 /* Interrupt Status Enable Register */ 287 #define ISER_OVR ISR_OVR 288 #define ISER_PP ISR_PP 289 #define ISER_BP ISR_BP 290 #define ISER_RP ISR_RP 291 #define ISER_SE ISR_SE 292 #define ISER_ALE ISR_ALE 293 #define ISER_BFCS ISR_BFCS 294 #define ISER_PTLE ISR_PTLE 295 #define ISER_ORE ISR_ORE 296 #define ISER_IRE ISR_IRE 297 #define ISER_DBDM ISR_DBDM 298 #define ISER_DB0 ISR_DB0 299 #define ISER_SE0 ISR_SE0 300 #define ISER_TE0 ISR_TE0 301 #define ISER_DB1 ISR_DB1 302 #define ISER_SE1 ISR_SE1 303 #define ISER_TE1 ISR_TE1 304 #define ISER_MOS ISR_MOS 305 #define ISER_MOF ISR_MOF 306 307 #define EMAC0_IAHR 0x1c /* Individual Address High Register */ 308 #define EMAC0_IALR 0x20 /* Individual Address Low Register */ 309 #define EMAC0_VTPID 0x24 /* VLAN TPID Register */ 310 #define EMAC0_VTCI 0x28 /* VLAN TCI Register */ 311 #define EMAC0_PTR 0x2c /* Pause Timer Register */ 312 #define EMAC0_IAHT1 0x30 /* Individual Address Hash Table 1 */ 313 #define EMAC0_IAHT2 0x34 /* Individual Address Hash Table 2 */ 314 #define EMAC0_IAHT3 0x38 /* Individual Address Hash Table 3 */ 315 #define EMAC0_IAHT4 0x3c /* Individual Address Hash Table 4 */ 316 #define EMAC0_GAHT1 0x40 /* Group Address Hash Table 1 */ 317 #define EMAC0_GAHT2 0x44 /* Group Address Hash Table 2 */ 318 #define EMAC0_GAHT3 0x48 /* Group Address Hash Table 3 */ 319 #define EMAC0_GAHT4 0x4c /* Group Address Hash Table 4 */ 320 #define EMAC0_LSAH 0x50 /* Last Source Address High */ 321 #define EMAC0_LSAL 0x54 /* Last Source Address Low */ 322 #define EMAC0_IPGVR 0x58 /* Inter-Packet Gap Value Register */ 323 324 #define EMAC0_STACR 0x5c /* STA Control Register */ 325 #define STACR_PHYD 0xffff0000 /* PHY data mask */ 326 #define STACR_PHYDSHIFT 16 327 #define STACR_OC 0x00008000 /* operation complete */ 328 #define STACR_PHYE 0x00004000 /* PHY error */ 329 #define STACR_WRITE 0x00002000 /* STA command - write */ 330 #define STACR_READ 0x00001000 /* STA command - read */ 331 #define STACR_OPBC_MASK 0x00000c00 /* OPB bus clock freq mask */ 332 #define STACR_OPBC_50MHZ 0x00000000 /* OPB bus clock freq - 50MHz */ 333 #define STACR_OPBC_66MHZ 0x00000400 /* OPB bus clock freq - 66MHz */ 334 #define STACR_OPBC_83MHZ 0x00000800 /* OPB bus clock freq - 83MHz */ 335 #define STACR_OPBC_100MHZ 0x00000c00 /* OPB bus clock freq - 100MHz */ 336 #define STACR_PCDA 0x000003e0 /* PHY cmd dest address mask */ 337 #define STACR_PCDASHIFT 5 338 #define STACR_PRA 0x0000001f /* PHY register address mask */ 339 #define STACR_PRASHIFT 0 340 341 #define EMAC0_TRTR 0x60 /* Transmit Request Threshold Register */ 342 #define TRTR_64 0x00000000 /* 64 bytes */ 343 #define TRTR_128 0x08000000 /* 128 bytes */ 344 #define TRTR_192 0x10000000 /* 192 bytes */ 345 #define TRTR_256 0x18000000 /* 256 bytes */ 346 /* ... and so on +64 until ... */ 347 #define TRTR_2048 0xf8000000 /* 2048 bytes */ 348 349 #define EMAC0_RWMR 0x64 /* Receive Low/High Water Mark Register */ 350 #define RWMR_RLWM_MASK 0xff800000 /* Receive Low Water Mark */ 351 #define RWMR_RLWM_SHIFT 23 352 #define RWMR_RHWM_MASK 0x0000ff80 /* Receive High Water Mark */ 353 #define RWMR_RHWM_SHIFT 7 354 355 #define EMAC0_OCTX 0x68 /* Number of Octets Transmitted */ 356 #define EMAC0_OCRX 0x6c /* Number of Octets Received */ 357 358 359 /* Expansion ROM - 254MB */ 360 #define EXPANSION_ROM_START 0xf0000000 361 #define EXPANSION_ROM_END 0xffdfffff 362 363 /* Boot ROM - 2MB */ 364 #define BOOT_ROM_START 0xffe00000 365 #define BOOT_ROM_END 0xffffffff 366 367 #ifndef _LOCORE 368 void galaxy_show_pci_map(void); 369 void galaxy_setup_pci(void); 370 #endif /* _LOCORE */ 371 #endif /* _IBM4XX_IBM405GP_H_ */ 372
Indexes created Thu Oct 02 14:10:14 GMT 2025