lock.h revision 1.16
11.16Srin/*	$NetBSD: lock.h,v 1.16 2021/09/13 11:54:42 rin Exp $	*/
21.1Sthorpej
31.1Sthorpej/*-
41.9Sad * Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
51.1Sthorpej * All rights reserved.
61.1Sthorpej *
71.1Sthorpej * This code is derived from software contributed to The NetBSD Foundation
81.9Sad * by Jason R. Thorpe and Andrew Doran.
91.1Sthorpej *
101.1Sthorpej * Redistribution and use in source and binary forms, with or without
111.1Sthorpej * modification, are permitted provided that the following conditions
121.1Sthorpej * are met:
131.1Sthorpej * 1. Redistributions of source code must retain the above copyright
141.1Sthorpej *    notice, this list of conditions and the following disclaimer.
151.1Sthorpej * 2. Redistributions in binary form must reproduce the above copyright
161.1Sthorpej *    notice, this list of conditions and the following disclaimer in the
171.1Sthorpej *    documentation and/or other materials provided with the distribution.
181.1Sthorpej *
191.1Sthorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
201.1Sthorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
211.1Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
221.1Sthorpej * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
231.1Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
241.1Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
251.1Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
261.1Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
271.1Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
281.1Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
291.1Sthorpej * POSSIBILITY OF SUCH DAMAGE.
301.1Sthorpej */
311.1Sthorpej
321.1Sthorpej/*
331.1Sthorpej * Machine-dependent spin lock operations.
341.1Sthorpej */
351.1Sthorpej
361.1Sthorpej#ifndef _POWERPC_LOCK_H_
371.3Stsubai#define _POWERPC_LOCK_H_
381.3Stsubai
391.10Sskrllstatic __inline int
401.13Schristos__SIMPLELOCK_LOCKED_P(const __cpu_simple_lock_t *__ptr)
411.10Sskrll{
421.10Sskrll	return *__ptr == __SIMPLELOCK_LOCKED;
431.10Sskrll}
441.10Sskrll
451.10Sskrllstatic __inline int
461.13Schristos__SIMPLELOCK_UNLOCKED_P(const __cpu_simple_lock_t *__ptr)
471.10Sskrll{
481.10Sskrll	return *__ptr == __SIMPLELOCK_UNLOCKED;
491.10Sskrll}
501.10Sskrll
511.10Sskrllstatic __inline void
521.10Sskrll__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
531.10Sskrll{
541.10Sskrll	*__ptr = __SIMPLELOCK_UNLOCKED;
551.10Sskrll}
561.10Sskrll
571.10Sskrllstatic __inline void
581.10Sskrll__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
591.10Sskrll{
601.10Sskrll	*__ptr = __SIMPLELOCK_LOCKED;
611.10Sskrll}
621.10Sskrll
631.8Sperrystatic __inline void
641.3Stsubai__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
651.3Stsubai{
661.3Stsubai	*alp = __SIMPLELOCK_UNLOCKED;
671.7Sperry	__asm volatile ("sync");
681.3Stsubai}
691.3Stsubai
701.8Sperrystatic __inline void
711.3Stsubai__cpu_simple_lock(__cpu_simple_lock_t *alp)
721.3Stsubai{
731.3Stsubai	int old;
741.3Stsubai
751.7Sperry	__asm volatile ("	\
761.3Stsubai				\n\
771.3Stsubai1:	lwarx	%0,0,%1		\n\
781.3Stsubai	cmpwi	%0,%2		\n\
791.3Stsubai	beq+	3f		\n\
801.4Stsubai2:	lwzx	%0,0,%1		\n\
811.3Stsubai	cmpwi	%0,%2		\n\
821.3Stsubai	beq+	1b		\n\
831.16Srin	b	2b		\n\
841.16Srin3:				\n"
851.15Srin#ifdef IBM405_ERRATA77
861.15Srin	"dcbt	0,%1		\n"
871.15Srin#endif
881.16Srin	"stwcx.	%3,0,%1		\n\
891.3Stsubai	bne-	1b		\n\
901.3Stsubai	isync			\n\
911.3Stsubai				\n"
921.3Stsubai	: "=&r"(old)
931.3Stsubai	: "r"(alp), "I"(__SIMPLELOCK_UNLOCKED), "r"(__SIMPLELOCK_LOCKED)
941.3Stsubai	: "memory");
951.3Stsubai}
961.3Stsubai
971.8Sperrystatic __inline int
981.3Stsubai__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
991.3Stsubai{
1001.4Stsubai	int old, dummy;
1011.3Stsubai
1021.7Sperry	__asm volatile ("	\
1031.3Stsubai				\n\
1041.3Stsubai1:	lwarx	%0,0,%1		\n\
1051.3Stsubai	cmpwi	%0,%2		\n\
1061.15Srin	bne	2f		\n"
1071.15Srin#ifdef IBM405_ERRATA77
1081.15Srin	"dcbt	0,%1		\n"
1091.15Srin#endif
1101.15Srin	"stwcx.	%3,0,%1		\n\
1111.16Srin	bne-	1b		\n\
1121.16Srin2:				\n"
1131.15Srin#ifdef IBM405_ERRATA77
1141.15Srin	"dcbt	0,%4		\n"
1151.15Srin#endif
1161.16Srin	"stwcx.	%3,0,%4		\n\
1171.3Stsubai	isync			\n\
1181.4Stsubai				\n"
1191.3Stsubai	: "=&r"(old)
1201.4Stsubai	: "r"(alp), "I"(__SIMPLELOCK_UNLOCKED), "r"(__SIMPLELOCK_LOCKED),
1211.4Stsubai	  "r"(&dummy)
1221.3Stsubai	: "memory");
1231.3Stsubai
1241.3Stsubai	return (old == __SIMPLELOCK_UNLOCKED);
1251.3Stsubai}
1261.3Stsubai
1271.8Sperrystatic __inline void
1281.3Stsubai__cpu_simple_unlock(__cpu_simple_lock_t *alp)
1291.3Stsubai{
1301.7Sperry	__asm volatile ("sync");
1311.3Stsubai	*alp = __SIMPLELOCK_UNLOCKED;
1321.3Stsubai}
1331.1Sthorpej
1341.1Sthorpej#endif /* _POWERPC_LOCK_H_ */
135