lock.h revision 1.17
11.17Sriastrad/* $NetBSD: lock.h,v 1.17 2022/02/12 17:17:53 riastradh Exp $ */ 21.1Sthorpej 31.1Sthorpej/*- 41.9Sad * Copyright (c) 2000, 2007 The NetBSD Foundation, Inc. 51.1Sthorpej * All rights reserved. 61.1Sthorpej * 71.1Sthorpej * This code is derived from software contributed to The NetBSD Foundation 81.9Sad * by Jason R. Thorpe and Andrew Doran. 91.1Sthorpej * 101.1Sthorpej * Redistribution and use in source and binary forms, with or without 111.1Sthorpej * modification, are permitted provided that the following conditions 121.1Sthorpej * are met: 131.1Sthorpej * 1. Redistributions of source code must retain the above copyright 141.1Sthorpej * notice, this list of conditions and the following disclaimer. 151.1Sthorpej * 2. Redistributions in binary form must reproduce the above copyright 161.1Sthorpej * notice, this list of conditions and the following disclaimer in the 171.1Sthorpej * documentation and/or other materials provided with the distribution. 181.1Sthorpej * 191.1Sthorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 201.1Sthorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 211.1Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 221.1Sthorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 231.1Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 241.1Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 251.1Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 261.1Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 271.1Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 281.1Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 291.1Sthorpej * POSSIBILITY OF SUCH DAMAGE. 301.1Sthorpej */ 311.1Sthorpej 321.1Sthorpej/* 331.1Sthorpej * Machine-dependent spin lock operations. 341.1Sthorpej */ 351.1Sthorpej 361.1Sthorpej#ifndef _POWERPC_LOCK_H_ 371.3Stsubai#define _POWERPC_LOCK_H_ 381.3Stsubai 391.10Sskrllstatic __inline int 401.13Schristos__SIMPLELOCK_LOCKED_P(const __cpu_simple_lock_t *__ptr) 411.10Sskrll{ 421.10Sskrll return *__ptr == __SIMPLELOCK_LOCKED; 431.10Sskrll} 441.10Sskrll 451.10Sskrllstatic __inline int 461.13Schristos__SIMPLELOCK_UNLOCKED_P(const __cpu_simple_lock_t *__ptr) 471.10Sskrll{ 481.10Sskrll return *__ptr == __SIMPLELOCK_UNLOCKED; 491.10Sskrll} 501.10Sskrll 511.10Sskrllstatic __inline void 521.10Sskrll__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr) 531.10Sskrll{ 541.10Sskrll *__ptr = __SIMPLELOCK_UNLOCKED; 551.10Sskrll} 561.10Sskrll 571.10Sskrllstatic __inline void 581.10Sskrll__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr) 591.10Sskrll{ 601.10Sskrll *__ptr = __SIMPLELOCK_LOCKED; 611.10Sskrll} 621.10Sskrll 631.8Sperrystatic __inline void 641.3Stsubai__cpu_simple_lock_init(__cpu_simple_lock_t *alp) 651.3Stsubai{ 661.3Stsubai *alp = __SIMPLELOCK_UNLOCKED; 671.3Stsubai} 681.3Stsubai 691.8Sperrystatic __inline void 701.3Stsubai__cpu_simple_lock(__cpu_simple_lock_t *alp) 711.3Stsubai{ 721.3Stsubai int old; 731.3Stsubai 741.7Sperry __asm volatile (" \ 751.3Stsubai \n\ 761.3Stsubai1: lwarx %0,0,%1 \n\ 771.3Stsubai cmpwi %0,%2 \n\ 781.3Stsubai beq+ 3f \n\ 791.4Stsubai2: lwzx %0,0,%1 \n\ 801.3Stsubai cmpwi %0,%2 \n\ 811.3Stsubai beq+ 1b \n\ 821.16Srin b 2b \n\ 831.16Srin3: \n" 841.15Srin#ifdef IBM405_ERRATA77 851.15Srin "dcbt 0,%1 \n" 861.15Srin#endif 871.16Srin "stwcx. %3,0,%1 \n\ 881.3Stsubai bne- 1b \n\ 891.3Stsubai isync \n\ 901.3Stsubai \n" 911.3Stsubai : "=&r"(old) 921.3Stsubai : "r"(alp), "I"(__SIMPLELOCK_UNLOCKED), "r"(__SIMPLELOCK_LOCKED) 931.3Stsubai : "memory"); 941.3Stsubai} 951.3Stsubai 961.8Sperrystatic __inline int 971.3Stsubai__cpu_simple_lock_try(__cpu_simple_lock_t *alp) 981.3Stsubai{ 991.4Stsubai int old, dummy; 1001.3Stsubai 1011.7Sperry __asm volatile (" \ 1021.3Stsubai \n\ 1031.3Stsubai1: lwarx %0,0,%1 \n\ 1041.3Stsubai cmpwi %0,%2 \n\ 1051.15Srin bne 2f \n" 1061.15Srin#ifdef IBM405_ERRATA77 1071.15Srin "dcbt 0,%1 \n" 1081.15Srin#endif 1091.15Srin "stwcx. %3,0,%1 \n\ 1101.16Srin bne- 1b \n\ 1111.16Srin2: \n" 1121.15Srin#ifdef IBM405_ERRATA77 1131.15Srin "dcbt 0,%4 \n" 1141.15Srin#endif 1151.16Srin "stwcx. %3,0,%4 \n\ 1161.3Stsubai isync \n\ 1171.4Stsubai \n" 1181.3Stsubai : "=&r"(old) 1191.4Stsubai : "r"(alp), "I"(__SIMPLELOCK_UNLOCKED), "r"(__SIMPLELOCK_LOCKED), 1201.4Stsubai "r"(&dummy) 1211.3Stsubai : "memory"); 1221.3Stsubai 1231.3Stsubai return (old == __SIMPLELOCK_UNLOCKED); 1241.3Stsubai} 1251.3Stsubai 1261.8Sperrystatic __inline void 1271.3Stsubai__cpu_simple_unlock(__cpu_simple_lock_t *alp) 1281.3Stsubai{ 1291.7Sperry __asm volatile ("sync"); 1301.3Stsubai *alp = __SIMPLELOCK_UNLOCKED; 1311.3Stsubai} 1321.1Sthorpej 1331.1Sthorpej#endif /* _POWERPC_LOCK_H_ */ 134