pte.h revision 1.5
1 /* $NetBSD: pte.h,v 1.5 2003/11/21 22:57:14 matt Exp $ */ 2 3 /*- 4 * Copyright (C) 2003 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _POWERPC_OEA_PTE_H_ 36 #define _POWERPC_OEA_PTE_H_ 37 38 #include <sys/queue.h> 39 40 /* 41 * Page Table Entries 42 */ 43 #ifndef _LOCORE 44 struct pte { 45 register_t pte_hi; 46 register_t pte_lo; 47 }; 48 49 struct pteg { 50 struct pte pt[8]; 51 }; 52 #endif /* _LOCORE */ 53 54 /* High word: */ 55 #ifdef PPC_OEA64 56 #define PTE_VALID 0x00000001 57 #define PTE_HID 0x00000002 58 #define PTE_API 0x00000f80 59 #define PTE_API_SHFT 7 60 #define PTE_VSID_SHFT 12 61 #define PTE_VSID (~0xfffL) 62 #else 63 #define PTE_VALID 0x80000000 64 #define PTE_VSID 0x7fffff80 65 #define PTE_VSID_SHFT 7 66 #define PTE_VSID_LEN 24 67 #define PTE_HID 0x00000040 68 #define PTE_API 0x0000003f 69 #define PTE_API_SHFT 0 70 #endif /* PPC_OEA64 */ 71 72 73 /* Low word: */ 74 #define PTE_RPGN (~0xfffL) 75 #define PTE_RPGN_SHFT 12 76 #define PTE_REF 0x00000100 77 #define PTE_CHG 0x00000080 78 #define PTE_W 0x00000040 /* 1 = write-through, 0 = write-back */ 79 #define PTE_I 0x00000020 /* cache inhibit */ 80 #define PTE_M 0x00000010 /* memory coherency enable */ 81 #define PTE_G 0x00000008 /* guarded region (not on 601) */ 82 #define PTE_WIMG (PTE_W|PTE_I|PTE_M|PTE_G) 83 #define PTE_IG (PTE_I|PTE_G) 84 #define PTE_PP 0x00000003 85 #define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ 86 #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ 87 #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ 88 #define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ 89 #define PTE_RW PTE_BW 90 #define PTE_RO PTE_BR 91 92 #define PTE_EXEC 0x00000200 /* pseudo bit; page is exec */ 93 94 /* 95 * Extract bits from address 96 */ 97 #define ADDR_SR (~0x0fffffffL) 98 #define ADDR_SR_SHFT 28 99 #define ADDR_PIDX 0x0ffff000 100 #define ADDR_PIDX_SHFT 12 101 #ifdef PPC_OEA64 102 #define ADDR_API_SHFT 23 /* API is 5 bits */ 103 #else 104 #define ADDR_API_SHFT 22 /* API is 6 bits */ 105 #endif /* PPC_OEA64 */ 106 #define ADDR_POFF 0x00000fff 107 108 #ifdef PPC_OEA64 109 /* 110 * Segment Table Element 111 */ 112 #ifndef _LOCORE 113 struct ste { 114 register_t ste_hi; 115 register_t ste_lo; 116 }; 117 118 struct steg { 119 struct ste st[8]; 120 }; 121 #endif /* _LOCORE */ 122 123 /* High Word */ 124 #define STE_VALID 0x00000080 125 #define STE_TYPE 0x00000040 126 #define STE_SUKEY 0x00000020 /* Super-state protection */ 127 #define STE_PRKEY 0x00000010 /* User-state protection */ 128 #define STE_NOEXEC 0x00000008 /* No-execute protection bit */ 129 #define STE_ESID (~0x0fffffffL) /* Effective Segment ID */ 130 #define STE_ESID_SHFT 28 131 #define STE_ESID_MASK 0x0000001f /* low 5 bits of the ESID */ 132 133 /* Low Word */ 134 #define STE_VSID (~0xfffL) /* Virtual Segment ID */ 135 #define STE_VSID_SHFT 12 136 #defien STE_VSID_WIDTH 52 137 138 #define SR_VSID_SHFT STE_VSID_SHFT /* compatibility with PPC_OEA */ 139 #define SR_VSID_WIDTH STE_VSID_WIDTH /* compatibility with PPC_OEA */ 140 141 #define SR_KEY_LEN 9 /* 64 groups of 8 segment entries */ 142 #else /* !defined(PPC_OEA64) */ 143 144 /* 145 * Segment registers 146 */ 147 #define SR_KEY_LEN 4 /* 16 segment registers */ 148 #define SR_TYPE 0x80000000 /* T=0 selects memory format */ 149 #define SR_SUKEY 0x40000000 /* Supervisor protection key */ 150 #define SR_PRKEY 0x20000000 /* User protection key */ 151 #define SR_NOEXEC 0x10000000 /* No-execute protection bit */ 152 #define SR_VSID_SHFT 0 /* Starts at LSB */ 153 #define SR_VSID_WIDTH 24 /* Goes for 24 bits */ 154 155 #endif /* PPC_OEA64 */ 156 157 /* Virtual segment ID */ 158 #define SR_VSID (((1L << SR_VSID_WIDTH) - 1) << SR_VSID_SHFT) 159 160 #endif /* _POWERPC_OEA_PTE_H_ */ 161
Indexes created Tue Sep 30 06:09:59 GMT 2025