openpicreg.h revision 1.7.8.1
1 1.7.8.1 bouyer /* $NetBSD: openpicreg.h,v 1.7.8.1 2008/01/19 12:14:40 bouyer Exp $ */ 2 1.1 briggs 3 1.1 briggs /*- 4 1.1 briggs * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 1.1 briggs * 6 1.1 briggs * Redistribution and use in source and binary forms, with or without 7 1.1 briggs * modification, are permitted provided that the following conditions 8 1.1 briggs * are met: 9 1.1 briggs * 1. Redistributions of source code must retain the above copyright 10 1.1 briggs * notice, this list of conditions and the following disclaimer. 11 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 briggs * notice, this list of conditions and the following disclaimer in the 13 1.1 briggs * documentation and/or other materials provided with the distribution. 14 1.1 briggs * 3. The name of the author may not be used to endorse or promote products 15 1.1 briggs * derived from this software without specific prior written permission. 16 1.1 briggs * 17 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.1 briggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.1 briggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.1 briggs * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 1.1 briggs * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 1.1 briggs * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 1.1 briggs * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 1.1 briggs * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 1.1 briggs * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 1.1 briggs * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 1.1 briggs */ 28 1.1 briggs 29 1.1 briggs /* 30 1.1 briggs * GLOBAL/TIMER register (IDU base + 0x1000) 31 1.1 briggs */ 32 1.1 briggs 33 1.1 briggs /* feature reporting reg 0 */ 34 1.1 briggs #define OPENPIC_FEATURE 0x1000 35 1.1 briggs 36 1.1 briggs /* global config reg 0 */ 37 1.1 briggs #define OPENPIC_CONFIG 0x1020 38 1.1 briggs #define OPENPIC_CONFIG_RESET 0x80000000 39 1.1 briggs #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 40 1.3 briggs 41 1.3 briggs /* interrupt configuration mode (direct or serial) */ 42 1.3 briggs #define OPENPIC_ICR 0x1030 43 1.3 briggs #define OPENPIC_ICR_SERIAL_MODE (1 << 27) 44 1.3 briggs #define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 45 1.3 briggs #define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 46 1.1 briggs 47 1.1 briggs /* vendor ID */ 48 1.1 briggs #define OPENPIC_VENDOR_ID 0x1080 49 1.1 briggs 50 1.1 briggs /* processor initialization reg */ 51 1.1 briggs #define OPENPIC_PROC_INIT 0x1090 52 1.1 briggs 53 1.1 briggs /* IPI vector/priority reg */ 54 1.1 briggs #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 55 1.1 briggs 56 1.1 briggs /* spurious intr. vector */ 57 1.1 briggs #define OPENPIC_SPURIOUS_VECTOR 0x10e0 58 1.7 garbled /* Timer frequency register */ 59 1.7 garbled #define OPENPIC_TIMER_FREQ 0x10f0 60 1.1 briggs 61 1.7 garbled /* Timer current count register */ 62 1.7 garbled #define OPENPIC_TIMER_CC(timer) (0x1100 + (timer) * 0x40) 63 1.7 garbled /* Timer basecount register */ 64 1.7 garbled #define OPENPIC_TIMER_BC(timer) (0x1110 + (timer) * 0x40) 65 1.7 garbled /* Timer Vector/Priority register (uses imask,activity,priority and vector)*/ 66 1.7 garbled #define OPENPIC_TIMER_VECTOR(timer) (0x1120 + (timer) * 0x40) 67 1.7 garbled /* Timer destination register */ 68 1.7 garbled #define OPENPIC_TIMER_DEST(timer) (0x1130 + (timer) * 0x40) 69 1.1 briggs 70 1.1 briggs /* 71 1.1 briggs * INTERRUPT SOURCE register (IDU base + 0x10000) 72 1.7.8.1 bouyer * ABOVE ONLY TRUE FOR NON-DISTRIBUTED OPENPICS!! 73 1.1 briggs */ 74 1.1 briggs 75 1.7.8.1 bouyer #define OPENPIC_DSRC_VECTOR_OFFSET(irq) ((irq) * 0x20) 76 1.7.8.1 bouyer #define OPENPIC_DSRC_IDEST_OFFSET(irq) ((irq) * 0x20 + 0x10) 77 1.7.8.1 bouyer 78 1.7.8.1 bouyer 79 1.1 briggs /* interrupt vector/priority reg */ 80 1.1 briggs #ifndef OPENPIC_SRC_VECTOR 81 1.1 briggs #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 82 1.1 briggs #endif 83 1.1 briggs #define OPENPIC_SENSE_LEVEL 0x00400000 84 1.1 briggs #define OPENPIC_SENSE_EDGE 0x00000000 85 1.1 briggs #define OPENPIC_POLARITY_POSITIVE 0x00800000 86 1.1 briggs #define OPENPIC_POLARITY_NEGATIVE 0x00000000 87 1.1 briggs #define OPENPIC_IMASK 0x80000000 88 1.1 briggs #define OPENPIC_ACTIVITY 0x40000000 89 1.1 briggs #define OPENPIC_PRIORITY_MASK 0x000f0000 90 1.1 briggs #define OPENPIC_PRIORITY_SHIFT 16 91 1.1 briggs #define OPENPIC_VECTOR_MASK 0x000000ff 92 1.1 briggs 93 1.5 wiz /* interrupt destination CPU */ 94 1.1 briggs #ifndef OPENPIC_IDEST 95 1.1 briggs #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 96 1.1 briggs #endif 97 1.1 briggs 98 1.1 briggs /* 99 1.1 briggs * PROCESSOR register (IDU base + 0x20000) 100 1.1 briggs */ 101 1.1 briggs 102 1.1 briggs /* IPI command reg */ 103 1.4 chs #define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + \ 104 1.4 chs (ipi) * 0x10) 105 1.1 briggs 106 1.1 briggs /* current task priority reg */ 107 1.1 briggs #define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 108 1.1 briggs #define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 109 1.1 briggs 110 1.1 briggs /* interrupt acknowledge reg */ 111 1.1 briggs #define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 112 1.1 briggs 113 1.1 briggs /* end of interrupt reg */ 114 1.1 briggs #define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 115
Indexes created Mon Oct 27 08:10:08 GMT 2025