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psl.h revision 1.1
      1  1.1  ws /*	$NetBSD: psl.h,v 1.1 1996/09/30 16:34:32 ws Exp $	*/
      2  1.1  ws 
      3  1.1  ws /*
      4  1.1  ws  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
      5  1.1  ws  * Copyright (C) 1995, 1996 TooLs GmbH.
      6  1.1  ws  * All rights reserved.
      7  1.1  ws  *
      8  1.1  ws  * Redistribution and use in source and binary forms, with or without
      9  1.1  ws  * modification, are permitted provided that the following conditions
     10  1.1  ws  * are met:
     11  1.1  ws  * 1. Redistributions of source code must retain the above copyright
     12  1.1  ws  *    notice, this list of conditions and the following disclaimer.
     13  1.1  ws  * 2. Redistributions in binary form must reproduce the above copyright
     14  1.1  ws  *    notice, this list of conditions and the following disclaimer in the
     15  1.1  ws  *    documentation and/or other materials provided with the distribution.
     16  1.1  ws  * 3. All advertising materials mentioning features or use of this software
     17  1.1  ws  *    must display the following acknowledgement:
     18  1.1  ws  *	This product includes software developed by TooLs GmbH.
     19  1.1  ws  * 4. The name of TooLs GmbH may not be used to endorse or promote products
     20  1.1  ws  *    derived from this software without specific prior written permission.
     21  1.1  ws  *
     22  1.1  ws  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
     23  1.1  ws  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  1.1  ws  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  1.1  ws  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26  1.1  ws  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     27  1.1  ws  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     28  1.1  ws  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     29  1.1  ws  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     30  1.1  ws  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     31  1.1  ws  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  1.1  ws  */
     33  1.1  ws #ifndef	_MACHINE_PSL_H_
     34  1.1  ws #define	_MACHINE_PSL_H_
     35  1.1  ws 
     36  1.1  ws /*
     37  1.1  ws  * Flags in MSR:
     38  1.1  ws  */
     39  1.1  ws #define	PSL_POW		0x00040000
     40  1.1  ws #define	PSL_ILE		0x00010000
     41  1.1  ws #define	PSL_EE		0x00008000
     42  1.1  ws #define	PSL_PR		0x00004000
     43  1.1  ws #define	PSL_FP		0x00002000
     44  1.1  ws #define	PSL_ME		0x00001000
     45  1.1  ws #define	PSL_FE0		0x00000800
     46  1.1  ws #define	PSL_SE		0x00000400
     47  1.1  ws #define	PSL_BE		0x00000200
     48  1.1  ws #define	PSL_FE1		0x00000100
     49  1.1  ws #define	PSL_IP		0x00000040
     50  1.1  ws #define	PSL_IR		0x00000020
     51  1.1  ws #define	PSL_DR		0x00000010
     52  1.1  ws #define	PSL_RI		0x00000002
     53  1.1  ws #define	PSL_LE		0x00000001
     54  1.1  ws 
     55  1.1  ws /*
     56  1.1  ws  * Floating-point exception modes:
     57  1.1  ws  */
     58  1.1  ws #define	PSL_FE_DIS	0
     59  1.1  ws #define	PSL_FE_NONREC	PSL_FE1
     60  1.1  ws #define	PSL_FE_REC	PSL_FE0
     61  1.1  ws #define	PSL_FE_PREC	(PSL_FE0 | PSL_FE1)
     62  1.1  ws #define	PSL_FE_DFLT	PSL_FE_DIS
     63  1.1  ws 
     64  1.1  ws /*
     65  1.1  ws  * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR
     66  1.1  ws  */
     67  1.1  ws #define	PSL_MBO		0
     68  1.1  ws #define	PSL_MBZ		0
     69  1.1  ws 
     70  1.1  ws #define	PSL_USERSET	(PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
     71  1.1  ws 
     72  1.1  ws #define	PSL_USERSTATIC	(PSL_USERSET | PSL_IP | 0x87c0008c)
     73  1.1  ws 
     74  1.1  ws 
     75  1.1  ws #ifdef	_KERNEL
     76  1.1  ws /*
     77  1.1  ws  * Current processor level.
     78  1.1  ws  */
     79  1.1  ws #ifndef	_LOCORE
     80  1.1  ws extern int cpl;
     81  1.1  ws extern int clockpending, softclockpending, softnetpending;
     82  1.1  ws #endif
     83  1.1  ws #define	SPLBIO		0x01
     84  1.1  ws #define	SPLNET		0x02
     85  1.1  ws #define	SPLTTY		0x04
     86  1.1  ws #define	SPLIMP		0x08
     87  1.1  ws #define	SPLSOFTCLOCK	0x10
     88  1.1  ws #define	SPLSOFTNET	0x20
     89  1.1  ws #define	SPLCLOCK	0x80
     90  1.1  ws #define	SPLMACHINE	0x0f	/* levels handled by machine interface */
     91  1.1  ws 
     92  1.1  ws #ifndef	_LOCORE
     93  1.1  ws extern int splx __P((int));
     94  1.1  ws 
     95  1.1  ws extern int splraise __P((int));
     96  1.1  ws 
     97  1.1  ws extern __inline int
     98  1.1  ws splhigh()
     99  1.1  ws {
    100  1.1  ws 	return splraise(-1);
    101  1.1  ws }
    102  1.1  ws 
    103  1.1  ws extern __inline int
    104  1.1  ws spl0()
    105  1.1  ws {
    106  1.1  ws 	return splx(0);
    107  1.1  ws }
    108  1.1  ws 
    109  1.1  ws extern __inline int
    110  1.1  ws splbio()
    111  1.1  ws {
    112  1.1  ws 	return splraise(SPLBIO | SPLSOFTCLOCK | SPLSOFTNET);
    113  1.1  ws }
    114  1.1  ws 
    115  1.1  ws extern __inline int
    116  1.1  ws splnet()
    117  1.1  ws {
    118  1.1  ws 	return splraise(SPLNET | SPLSOFTCLOCK | SPLSOFTNET);
    119  1.1  ws }
    120  1.1  ws 
    121  1.1  ws extern __inline int
    122  1.1  ws spltty()
    123  1.1  ws {
    124  1.1  ws 	return splraise(SPLTTY | SPLSOFTCLOCK | SPLSOFTNET);
    125  1.1  ws }
    126  1.1  ws 
    127  1.1  ws extern __inline int
    128  1.1  ws splimp()
    129  1.1  ws {
    130  1.1  ws 	return splraise(SPLIMP | SPLSOFTCLOCK | SPLSOFTNET);
    131  1.1  ws }
    132  1.1  ws extern __inline int
    133  1.1  ws splclock()
    134  1.1  ws {
    135  1.1  ws 	return splraise(SPLCLOCK | SPLSOFTCLOCK | SPLSOFTNET);
    136  1.1  ws }
    137  1.1  ws 
    138  1.1  ws extern __inline int
    139  1.1  ws splsoftclock()
    140  1.1  ws {
    141  1.1  ws 	return splraise(SPLSOFTCLOCK);
    142  1.1  ws }
    143  1.1  ws 
    144  1.1  ws extern __inline int
    145  1.1  ws splsoftnet()
    146  1.1  ws {
    147  1.1  ws 	return splraise(SPLSOFTNET);
    148  1.1  ws }
    149  1.1  ws 
    150  1.1  ws extern __inline void
    151  1.1  ws setsoftclock()
    152  1.1  ws {
    153  1.1  ws 	softclockpending = 1;
    154  1.1  ws 	if (!(cpl & SPLSOFTCLOCK))
    155  1.1  ws 		splx(cpl);
    156  1.1  ws }
    157  1.1  ws 
    158  1.1  ws extern __inline void
    159  1.1  ws setsoftnet()
    160  1.1  ws {
    161  1.1  ws 	softnetpending = 1;
    162  1.1  ws 	if (!(cpl & SPLSOFTNET))
    163  1.1  ws 		splx(cpl);
    164  1.1  ws }
    165  1.1  ws 
    166  1.1  ws #endif	/* !_LOCORE */
    167  1.1  ws 
    168  1.1  ws #define	splstatclock()		splclock()
    169  1.1  ws 
    170  1.1  ws #endif	/* _KERNEL */
    171  1.1  ws #endif	/* _MACHINE_PSL_H_ */
    172