psl.h revision 1.22
1 /* $NetBSD: psl.h,v 1.22 2021/03/06 08:08:19 rin Exp $ */ 2 3 /* 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _POWERPC_PSL_H_ 35 #define _POWERPC_PSL_H_ 36 37 /* 38 * Machine State Register (MSR) 39 * 40 * The PowerPC 601 does not implement the following bits: 41 * 42 * VEC, POW, ILE, BE, RI, LE[*] 43 * 44 * [*] Little-endian mode on the 601 is implemented in the HID0 register. 45 */ 46 #define PSL_VEC 0x02000000 /* ..6. AltiVec vector unit available */ 47 #define PSL_SPV 0x02000000 /* B... (e500) SPE enable */ 48 #define PSL_UCLE 0x00400000 /* B... user-mode cache lock enable */ 49 #define PSL_POW 0x00040000 /* ..6. power management */ 50 #define PSL_WE PSL_POW /* B4.. wait state enable */ 51 #define PSL_TGPR 0x00020000 /* ..6. temp. gpr remapping (mpc603e) */ 52 #define PSL_CE PSL_TGPR /* B4.. critical interrupt enable */ 53 #define PSL_ILE 0x00010000 /* ..6. interrupt endian mode (1 == le) */ 54 #define PSL_EE 0x00008000 /* B468 external interrupt enable */ 55 #define PSL_PR 0x00004000 /* B468 privilege mode (1 == user) */ 56 #define PSL_FP 0x00002000 /* B.6. floating point enable */ 57 #define PSL_ME 0x00001000 /* B468 machine check enable */ 58 #define PSL_FE0 0x00000800 /* B.6. floating point mode 0 */ 59 #define PSL_SE 0x00000400 /* ..6. single-step trace enable */ 60 #define PSL_DWE PSL_SE /* .4.. debug wait enable */ 61 #define PSL_UBLE PSL_SE /* B... user BTB lock enable */ 62 #define PSL_BE 0x00000200 /* ..6. branch trace enable */ 63 #define PSL_DE PSL_BE /* B4.. debug interrupt enable */ 64 #define PSL_FE1 0x00000100 /* B.6. floating point mode 1 */ 65 #define PSL_IP 0x00000040 /* ..6. interrupt prefix */ 66 #define PSL_IR 0x00000020 /* .468 instruction address relocation */ 67 #define PSL_IS PSL_IR /* B... instruction address space */ 68 #define PSL_DR 0x00000010 /* .468 data address relocation */ 69 #define PSL_DS PSL_DR /* B... data address space */ 70 #define PSL_PM 0x00000008 /* ..6. Performance monitor */ 71 #define PSL_PMM PSL_PM /* B... Performance monitor */ 72 #define PSL_RI 0x00000002 /* ..6. recoverable interrupt */ 73 #define PSL_LE 0x00000001 /* ..6. endian mode (1 == le) */ 74 75 #define PSL_601_MASK ~(PSL_VEC|PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE) 76 77 /* The IBM 970 series does not implemnt LE mode */ 78 #define PSL_970_MASK ~(PSL_ILE|PSL_LE) 79 80 /* 81 * Floating-point exception modes: 82 */ 83 #define PSL_FE_DIS 0 /* none */ 84 #define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */ 85 #define PSL_FE_REC PSL_FE0 /* imprecise recoverable */ 86 #define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */ 87 #define PSL_FE_DFLT PSL_FE_DIS /* default == none */ 88 89 /* 90 * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR 91 */ 92 #define PSL_MBO 0 93 #define PSL_MBZ 0 94 95 /* 96 * A user is not allowed to change any MSR bits except the following: 97 * We restrict the test to the low 16 bits of the MSR since those are the 98 * only ones preserved in the trap. Note that this means PSL_VEC needs to 99 * be restored to SRR1 in userret. 100 */ 101 #if defined(_KERNEL) && !defined(_LOCORE) 102 #ifdef _KERNEL_OPT 103 #include "opt_ppcarch.h" 104 #endif /* _KERNEL_OPT */ 105 106 #if defined(PPC_OEA) || defined (PPC_OEA64_BRIDGE) || defined (PPC_OEA64) \ 107 || defined(_MODULE) 108 extern register_t cpu_psluserset, cpu_pslusermod, cpu_pslusermask; 109 110 #define PSL_USERSET cpu_psluserset 111 #define PSL_USERMOD cpu_pslusermod 112 #define PSL_USERMASK cpu_pslusermask 113 #elif defined(PPC_BOOKE) 114 #define PSL_USERSET (PSL_EE | PSL_PR | PSL_IS | PSL_DS | PSL_ME | PSL_CE) 115 #define PSL_USERMASK (PSL_SPV | PSL_CE | 0xFFFF) 116 #define PSL_USERMOD (0) 117 #else /* PPC_IBM4XX */ 118 #ifdef PPC_IBM403 119 #define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR | PSL_ME) 120 #else /* Apparently we get unexplained machine checks, so disable them. */ 121 #define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR) 122 #endif 123 #define PSL_USERMASK 0xFFFF 124 #define PSL_USERMOD (0) 125 #endif 126 127 #define PSL_USERSRR1 ((PSL_USERSET|PSL_USERMOD) & PSL_USERMASK) 128 #define PSL_USEROK_P(psl) (((psl) & ~PSL_USERMOD) == PSL_USERSET) 129 #endif /* !_LOCORE */ 130 131 #endif /* _POWERPC_PSL_H_ */ 132
Indexes created Mon Sep 22 13:09:51 GMT 2025