spr.h revision 1.21
1 /* $NetBSD: spr.h,v 1.21 2002/08/06 06:17:50 chs Exp $ */ 2 3 #ifndef _POWERPC_SPR_H_ 4 #define _POWERPC_SPR_H_ 5 6 #ifndef _LOCORE 7 #define mtspr(reg, val) \ 8 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 9 #define mfspr(reg) \ 10 ( { uint32_t val; \ 11 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 12 val; } ) 13 #endif /* _LOCORE */ 14 15 /* 16 * Special Purpose Register declarations. 17 * 18 * The first column in the comments indicates which PowerPC 19 * architectures the SPR is valid on - 4 for 4xx series, 20 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 21 */ 22 23 #define SPR_MQ 0x000 /* .6. 601 MQ register */ 24 #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 25 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ 26 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ 27 #define SPR_LR 0x008 /* 468 Link Register */ 28 #define SPR_CTR 0x009 /* 468 Count Register */ 29 #define SPR_DSISR 0x012 /* .68 DSI exception source */ 30 #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 31 #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 32 #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 33 #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 34 #define DSISR_STORE 0x02000000 /* Store operation */ 35 #define DSISR_DABR 0x00400000 /* DABR match */ 36 #define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 37 #define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 38 #define SPR_DAR 0x013 /* .68 Data Address Register */ 39 #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 40 #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 41 #define SPR_DEC 0x016 /* .68 DECrementer register */ 42 #define SPR_SDR1 0x019 /* .68 Page table base address register */ 43 #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 44 #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 45 #define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ 46 #define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ 47 #define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 48 #define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 49 #define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 50 #define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 51 #define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 52 #define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 53 #define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 54 #define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ 55 #define SPR_EAR 0x11a /* .68 External Access Register */ 56 #define SPR_TBL 0x11c /* 468 Time Base Lower */ 57 #define SPR_TBU 0x11d /* 468 Time Base Upper */ 58 #define SPR_PVR 0x11f /* 468 Processor Version Register */ 59 #define MPC601 0x0001 60 #define MPC603 0x0003 61 #define MPC604 0x0004 62 #define MPC602 0x0005 63 #define MPC603e 0x0006 64 #define MPC603ev 0x0007 65 #define MPC750 0x0008 66 #define MPC604ev 0x0009 67 #define MPC7400 0x000c 68 #define MPC620 0x0014 69 #define MPC860 0x0050 70 #define MPC8240 0x0081 71 #define IBM750FX 0x7000 72 #define MPC7450 0x8000 73 #define MPC7455 0x8001 74 #define MPC7410 0x800c 75 #define MPC8245 0x8081 76 #define IBM405GP 0x4011 77 #define IBM405L 0x4161 78 #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ 79 #define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */ 80 #define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */ 81 #define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */ 82 #define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */ 83 #define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */ 84 #define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */ 85 #define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */ 86 #define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */ 87 #define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */ 88 #define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */ 89 #define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */ 90 #define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */ 91 #define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */ 92 #define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */ 93 #define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */ 94 #define SPI_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 95 #define SPI_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 96 #define SPI_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 97 #define SPI_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 98 #define SPI_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 99 #define SPI_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 100 #define SPI_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 101 #define SPI_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 102 #define SPI_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 103 #define SPI_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 104 #define SPI_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 105 #define SPI_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 106 #define SPI_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 107 #define SPI_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 108 #define SPI_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 109 #define SPI_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 110 #define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 111 #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 112 #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 113 #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 114 #define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 115 #define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 116 #define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 117 #define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 118 #define SPR_PID 0x3b1 /* 4.. Process ID */ 119 #define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ 120 #define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ 121 #define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ 122 #define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ 123 #define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ 124 #define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ 125 #define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ 126 #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ 127 #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ 128 #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 129 #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 130 #define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 131 #define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 132 #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 133 #define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 134 #define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 135 #define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 136 #define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 137 #define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 138 #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 139 #define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 140 #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 141 #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 142 #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 143 #define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ 144 #define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ 145 #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 146 #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 147 #define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 148 #define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 149 #define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 150 #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 151 #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ 152 #define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */ 153 #define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */ 154 #define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */ 155 #define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */ 156 157 #define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ 158 #define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 159 #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ 160 #define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ 161 #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 162 #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 163 #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 164 #define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ 165 #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 166 #define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ 167 #define ESR_MCI 0x80000000 /* Machine check - instruction */ 168 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 169 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 170 #define ESR_PTR 0x02000000 /* Program interrupt - trap */ 171 #define ESR_DST 0x00800000 /* Data storage interrupt - store fault */ 172 #define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */ 173 #define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */ 174 #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 175 #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ 176 #define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ 177 #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 178 #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ 179 #define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ 180 #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 181 #define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ 182 #define SPR_TSR 0x3d8 /* 4.. Timer Status Register */ 183 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 184 #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 185 #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 186 #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 187 #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 188 #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 189 #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 190 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 191 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 192 #define SPR_TCR 0x3da /* 4.. Timer Control Register */ 193 #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 194 #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 195 #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 196 #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 197 #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 198 #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 199 #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 200 #define TCR_WRC_CORE 0x10000000 /* Core reset */ 201 #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 202 #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 203 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 204 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 205 #define TCR_FP_MASK 0x03000000 /* FIT Period */ 206 #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 207 #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 208 #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 209 #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 210 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 211 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 212 #define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 213 #define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 214 #define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 215 #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 216 #define DBSR_IC 0x80000000 /* Instruction completion debug event */ 217 #define DBSR_BT 0x40000000 /* Branch Taken debug event */ 218 #define DBSR_EDE 0x20000000 /* Exception debug event */ 219 #define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 220 #define DBSR_UDE 0x08000000 /* Unconditional debug event */ 221 #define DBSR_IA1 0x04000000 /* IAC1 debug event */ 222 #define DBSR_IA2 0x02000000 /* IAC2 debug event */ 223 #define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ 224 #define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ 225 #define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ 226 #define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ 227 #define DBSR_IDE 0x00100000 /* Imprecise debug event */ 228 #define DBSR_IA3 0x00080000 /* IAC3 debug event */ 229 #define DBSR_IA4 0x00040000 /* IAC4 debug event */ 230 #define DBSR_MRR 0x00000300 /* Most recent reset */ 231 #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 232 #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 233 #define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 234 #define DBCR0_EDM 0x80000000 /* External Debug Mode */ 235 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 236 #define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 237 #define DBCR0_RST_NONE 0x00000000 /* No action */ 238 #define DBCR0_RST_CORE 0x10000000 /* Core reset */ 239 #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 240 #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 241 #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 242 #define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 243 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 244 #define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 245 #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 246 #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 247 #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 248 #define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 249 #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 250 #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 251 #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 252 #define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 253 #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 254 #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 255 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 256 #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 257 #define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 258 #define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 259 #define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 260 #define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 261 #define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 262 #define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ 263 #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 264 #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 265 #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 266 #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 267 #define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 268 #define MSSCR0_MBO 0x00400000 /* 9: must be one */ 269 #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 270 #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 271 #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ 272 #define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 273 #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 274 #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 275 #define L2CR_L2E 0x80000000 /* 0: L2 enable */ 276 #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 277 #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 278 #define L2SIZ_2M 0x00000000 279 #define L2SIZ_256K 0x10000000 280 #define L2SIZ_512K 0x20000000 281 #define L2SIZ_1M 0x30000000 282 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 283 #define L2CLK_DIS 0x00000000 /* disable L2 clock */ 284 #define L2CLK_10 0x02000000 /* core clock / 1 */ 285 #define L2CLK_15 0x04000000 /* / 1.5 */ 286 #define L2CLK_20 0x08000000 /* / 2 */ 287 #define L2CLK_25 0x0a000000 /* / 2.5 */ 288 #define L2CLK_30 0x0c000000 /* / 3 */ 289 #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 290 #define L2RAM_FLOWTHRU_BURST 0x00000000 291 #define L2RAM_PIPELINE_BURST 0x01000000 292 #define L2RAM_PIPELINE_LATE 0x01800000 293 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 294 Setting this bit disables instruction 295 caching. */ 296 #define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 297 #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 298 Enables automatic operation of the 299 L2ZZ (low-power mode) signal. */ 300 #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 301 #define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 302 #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 303 #define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 304 #define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 305 #define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 306 #define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 307 #define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 308 #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 309 #define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 310 #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 311 #define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 312 /* progress (read only). */ 313 #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ 314 #define L3CR_L3E 0x80000000 /* 0: L3 enable */ 315 #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 316 #define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 317 #define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 318 #define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 319 #define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 320 #define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 321 #define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 322 #define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 323 #define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 324 #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 325 #define SPR_THRM_VALID 0x00000001 /* Valid bit */ 326 #define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ 327 #define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 328 #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 329 #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 330 #define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 331 332 /* Time Base Register declarations */ 333 #define TBR_TBL 0x10c /* 468 Time Base Lower */ 334 #define TBR_TBU 0x10d /* 468 Time Base Upper */ 335 336 /* Performance counter declarations */ 337 #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 338 339 /* The first five countable [non-]events are common to all the PMC's */ 340 #define PMCN_NONE 0 /* Count nothing */ 341 #define PMCN_CYCLES 1 /* Processor cycles */ 342 #define PMCN_ICOMP 2 /* Instructions completed */ 343 #define PMCN_TBLTRANS 3 /* TBL bit transitions */ 344 #define PCMN_IDISPATCH 4 /* Instructions dispatched */ 345 346 #endif /* !_POWERPC_SPR_H_ */ 347
Indexes created Wed Sep 24 05:09:52 GMT 2025