spr.h revision 1.25
1 /* $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ */ 2 3 #ifndef _POWERPC_SPR_H_ 4 #define _POWERPC_SPR_H_ 5 6 #ifndef _LOCORE 7 #define mtspr(reg, val) \ 8 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 9 #define mfspr(reg) \ 10 ( { register_t val; \ 11 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 12 val; } ) 13 #endif /* _LOCORE */ 14 15 /* 16 * Special Purpose Register declarations. 17 * 18 * The first column in the comments indicates which PowerPC 19 * architectures the SPR is valid on - 4 for 4xx series, 20 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 21 */ 22 23 #define SPR_MQ 0x000 /* .6. 601 MQ register */ 24 #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 25 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ 26 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ 27 #define SPR_LR 0x008 /* 468 Link Register */ 28 #define SPR_CTR 0x009 /* 468 Count Register */ 29 #define SPR_DSISR 0x012 /* .68 DSI exception source */ 30 #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 31 #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 32 #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 33 #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 34 #define DSISR_STORE 0x02000000 /* Store operation */ 35 #define DSISR_DABR 0x00400000 /* DABR match */ 36 #define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 37 #define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 38 #define SPR_DAR 0x013 /* .68 Data Address Register */ 39 #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 40 #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 41 #define SPR_DEC 0x016 /* .68 DECrementer register */ 42 #define SPR_SDR1 0x019 /* .68 Page table base address register */ 43 #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 44 #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 45 #define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ 46 #define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ 47 #define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ 48 #define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ 49 #define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ 50 #define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 51 #define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 52 #define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 53 #define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 54 #define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 55 #define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 56 #define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 57 #define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ 58 #define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ 59 #define SPR_EAR 0x11a /* .68 External Access Register */ 60 #define SPR_TBL 0x11c /* 468 Time Base Lower */ 61 #define SPR_TBU 0x11d /* 468 Time Base Upper */ 62 #define SPR_PVR 0x11f /* 468 Processor Version Register */ 63 #define MPC601 0x0001 64 #define MPC603 0x0003 65 #define MPC604 0x0004 66 #define MPC602 0x0005 67 #define MPC603e 0x0006 68 #define MPC603ev 0x0007 69 #define MPC750 0x0008 70 #define MPC604ev 0x0009 71 #define MPC7400 0x000c 72 #define MPC620 0x0014 73 #define IBM403 0x0020 74 #define IBM401A1 0x0021 75 #define IBM401B2 0x0022 76 #define IBM401C2 0x0023 77 #define IBM401D2 0x0024 78 #define IBM401E2 0x0025 79 #define IBM401F2 0x0026 80 #define IBM401G2 0x0027 81 #define IBMPOWER3 0x0041 82 #define MPC860 0x0050 83 #define MPC8240 0x0081 84 #define IBM405GP 0x4011 85 #define IBM405L 0x4161 86 #define IBM750FX 0x7000 87 #define MPC7450 0x8000 88 #define MPC7455 0x8001 89 #define MPC7410 0x800c 90 #define MPC8245 0x8081 91 92 #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ 93 #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ 94 #define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ 95 #define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ 96 #define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ 97 #define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ 98 #define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ 99 #define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ 100 #define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ 101 #define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ 102 #define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ 103 #define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ 104 #define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ 105 #define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ 106 #define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ 107 #define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ 108 #define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ 109 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ 110 #define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ 111 #define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ 112 #define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ 113 #define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ 114 #define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ 115 #define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ 116 #define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ 117 #define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ 118 #define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ 119 #define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ 120 #define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 121 #define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ 122 #define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 123 #define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ 124 #define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 125 #define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 126 #define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 127 #define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 128 #define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 129 #define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 130 #define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ 131 #define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ 132 #define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ 133 #define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ 134 #define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ 135 #define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ 136 #define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ 137 #define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ 138 #define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ 139 #define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ 140 #define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ 141 #define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ 142 #define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ 143 #define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ 144 #define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ 145 #define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ 146 #define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ 147 #define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ 148 #define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 149 #define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ 150 #define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 151 #define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ 152 #define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 153 #define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 154 #define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 155 #define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 156 #define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 157 #define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 158 #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ 159 #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ 160 #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ 161 #define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ 162 #define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ 163 #define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ 164 #define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ 165 #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ 166 #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ 167 #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ 168 #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ 169 #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ 170 #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ 171 #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ 172 #define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ 173 #define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ 174 #define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ 175 #define Mx_EPN_EV 0x00000020 /* Entry Valid */ 176 #define Mx_EPN_ASID 0x0000000f /* Address Space ID */ 177 #define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ 178 #define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ 179 #define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ 180 #define Mx_TWC_G 0x00000010 /* Guarded memory */ 181 #define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ 182 #define MD_TWC_WT 0x00000002 /* Write-Through */ 183 #define Mx_TWC_V 0x00000001 /* Entry Valid */ 184 #define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ 185 #define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ 186 #define Mx_RPN_PP 0x00000ff0 /* Page Protection */ 187 #define Mx_RPN_SPS 0x00000008 /* Small Page Size */ 188 #define Mx_RPN_SH 0x00000004 /* SHared page */ 189 #define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ 190 #define Mx_RPN_V 0x00000001 /* Valid */ 191 #define SPR_MD_CTR 0x318 /* ..8 DMMU control */ 192 #define SPR_M_CASID 0x319 /* ..8 CASID */ 193 #define M_CASID 0x0000000f /* Current AS Id */ 194 #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ 195 #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ 196 #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ 197 #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ 198 #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ 199 #define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ 200 #define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ 201 #define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ 202 #define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ 203 #define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ 204 #define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ 205 #define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ 206 #define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ 207 #define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ 208 #define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 209 #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 210 #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 211 #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 212 #define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 213 #define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 214 #define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 215 #define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 216 #define SPR_PID 0x3b1 /* 4.. Process ID */ 217 #define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ 218 #define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ 219 #define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ 220 #define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ 221 #define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ 222 #define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ 223 #define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ 224 #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ 225 #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ 226 #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 227 #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 228 #define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 229 #define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 230 #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 231 #define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 232 #define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 233 #define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 234 #define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 235 #define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 236 #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 237 #define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 238 #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 239 #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 240 #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 241 #define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ 242 #define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ 243 #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 244 #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 245 #define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 246 #define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 247 #define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 248 #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 249 #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ 250 #define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */ 251 #define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */ 252 #define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */ 253 #define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */ 254 255 #define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ 256 #define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 257 #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ 258 #define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ 259 #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 260 #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 261 #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 262 #define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ 263 #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 264 #define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ 265 #define ESR_MCI 0x80000000 /* Machine check - instruction */ 266 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 267 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 268 #define ESR_PTR 0x02000000 /* Program interrupt - trap */ 269 #define ESR_DST 0x00800000 /* Data storage interrupt - store fault */ 270 #define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */ 271 #define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */ 272 #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 273 #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ 274 #define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ 275 #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 276 #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ 277 #define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ 278 #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 279 #define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ 280 #define SPR_TSR 0x3d8 /* 4.. Timer Status Register */ 281 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 282 #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 283 #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 284 #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 285 #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 286 #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 287 #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 288 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 289 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 290 #define SPR_TCR 0x3da /* 4.. Timer Control Register */ 291 #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 292 #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 293 #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 294 #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 295 #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 296 #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 297 #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 298 #define TCR_WRC_CORE 0x10000000 /* Core reset */ 299 #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 300 #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 301 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 302 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 303 #define TCR_FP_MASK 0x03000000 /* FIT Period */ 304 #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 305 #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 306 #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 307 #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 308 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 309 #define TCR_ARE 0x00400000 /* Auto Reload Enable */ 310 #define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 311 #define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 312 #define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 313 #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 314 #define DBSR_IC 0x80000000 /* Instruction completion debug event */ 315 #define DBSR_BT 0x40000000 /* Branch Taken debug event */ 316 #define DBSR_EDE 0x20000000 /* Exception debug event */ 317 #define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 318 #define DBSR_UDE 0x08000000 /* Unconditional debug event */ 319 #define DBSR_IA1 0x04000000 /* IAC1 debug event */ 320 #define DBSR_IA2 0x02000000 /* IAC2 debug event */ 321 #define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ 322 #define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ 323 #define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ 324 #define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ 325 #define DBSR_IDE 0x00100000 /* Imprecise debug event */ 326 #define DBSR_IA3 0x00080000 /* IAC3 debug event */ 327 #define DBSR_IA4 0x00040000 /* IAC4 debug event */ 328 #define DBSR_MRR 0x00000300 /* Most recent reset */ 329 #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 330 #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 331 #define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 332 #define DBCR0_EDM 0x80000000 /* External Debug Mode */ 333 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 334 #define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 335 #define DBCR0_RST_NONE 0x00000000 /* No action */ 336 #define DBCR0_RST_CORE 0x10000000 /* Core reset */ 337 #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 338 #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 339 #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 340 #define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 341 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 342 #define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 343 #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 344 #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 345 #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 346 #define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 347 #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 348 #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 349 #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 350 #define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 351 #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 352 #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 353 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 354 #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 355 #define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 356 #define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 357 #define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 358 #define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 359 #define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 360 #define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ 361 #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 362 #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 363 #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 364 #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 365 #define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 366 #define MSSCR0_MBO 0x00400000 /* 9: must be one */ 367 #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 368 #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 369 #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ 370 #define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 371 #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 372 #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 373 #define L2CR_L2E 0x80000000 /* 0: L2 enable */ 374 #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 375 #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 376 #define L2SIZ_2M 0x00000000 377 #define L2SIZ_256K 0x10000000 378 #define L2SIZ_512K 0x20000000 379 #define L2SIZ_1M 0x30000000 380 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 381 #define L2CLK_DIS 0x00000000 /* disable L2 clock */ 382 #define L2CLK_10 0x02000000 /* core clock / 1 */ 383 #define L2CLK_15 0x04000000 /* / 1.5 */ 384 #define L2CLK_20 0x08000000 /* / 2 */ 385 #define L2CLK_25 0x0a000000 /* / 2.5 */ 386 #define L2CLK_30 0x0c000000 /* / 3 */ 387 #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 388 #define L2RAM_FLOWTHRU_BURST 0x00000000 389 #define L2RAM_PIPELINE_BURST 0x01000000 390 #define L2RAM_PIPELINE_LATE 0x01800000 391 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 392 Setting this bit disables instruction 393 caching. */ 394 #define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 395 #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 396 Enables automatic operation of the 397 L2ZZ (low-power mode) signal. */ 398 #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 399 #define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 400 #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 401 #define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 402 #define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 403 #define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 404 #define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 405 #define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 406 #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 407 #define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 408 #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 409 #define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 410 /* progress (read only). */ 411 #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ 412 #define L3CR_L3E 0x80000000 /* 0: L3 enable */ 413 #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 414 #define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 415 #define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 416 #define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 417 #define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 418 #define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 419 #define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 420 #define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 421 #define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 422 #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 423 #define SPR_THRM_VALID 0x00000001 /* Valid bit */ 424 #define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ 425 #define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 426 #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 427 #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 428 #define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 429 430 /* Time Base Register declarations */ 431 #define TBR_TBL 0x10c /* 468 Time Base Lower */ 432 #define TBR_TBU 0x10d /* 468 Time Base Upper */ 433 434 /* Performance counter declarations */ 435 #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 436 437 /* The first five countable [non-]events are common to all the PMC's */ 438 #define PMCN_NONE 0 /* Count nothing */ 439 #define PMCN_CYCLES 1 /* Processor cycles */ 440 #define PMCN_ICOMP 2 /* Instructions completed */ 441 #define PMCN_TBLTRANS 3 /* TBL bit transitions */ 442 #define PCMN_IDISPATCH 4 /* Instructions dispatched */ 443 444 #endif /* !_POWERPC_SPR_H_ */ 445
Indexes created Fri Sep 26 08:10:20 GMT 2025