trap.h revision 1.13 1 1.13 macallan /* $NetBSD: trap.h,v 1.13 2014/03/03 15:36:36 macallan Exp $ */
2 1.1 ws
3 1.1 ws /*
4 1.1 ws * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 1.1 ws * Copyright (C) 1995, 1996 TooLs GmbH.
6 1.1 ws * All rights reserved.
7 1.1 ws *
8 1.1 ws * Redistribution and use in source and binary forms, with or without
9 1.1 ws * modification, are permitted provided that the following conditions
10 1.1 ws * are met:
11 1.1 ws * 1. Redistributions of source code must retain the above copyright
12 1.1 ws * notice, this list of conditions and the following disclaimer.
13 1.1 ws * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 ws * notice, this list of conditions and the following disclaimer in the
15 1.1 ws * documentation and/or other materials provided with the distribution.
16 1.1 ws * 3. All advertising materials mentioning features or use of this software
17 1.1 ws * must display the following acknowledgement:
18 1.1 ws * This product includes software developed by TooLs GmbH.
19 1.1 ws * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 1.1 ws * derived from this software without specific prior written permission.
21 1.1 ws *
22 1.1 ws * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 1.1 ws * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 ws * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 ws * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 1.1 ws * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 1.1 ws * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 1.1 ws * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 1.1 ws * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 1.1 ws * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 1.1 ws * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 ws */
33 1.3 is #ifndef _POWERPC_TRAP_H_
34 1.3 is #define _POWERPC_TRAP_H_
35 1.1 ws
36 1.1 ws #define EXC_RSVD 0x0000 /* Reserved */
37 1.6 simonb #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
38 1.1 ws #define EXC_MCHK 0x0200 /* Machine Check */
39 1.1 ws #define EXC_DSI 0x0300 /* Data Storage Interrupt */
40 1.1 ws #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
41 1.1 ws #define EXC_EXI 0x0500 /* External Interrupt */
42 1.1 ws #define EXC_ALI 0x0600 /* Alignment Interrupt */
43 1.1 ws #define EXC_PGM 0x0700 /* Program Interrupt */
44 1.1 ws #define EXC_FPU 0x0800 /* Floating-point Unavailable */
45 1.1 ws #define EXC_DECR 0x0900 /* Decrementer Interrupt */
46 1.1 ws #define EXC_SC 0x0c00 /* System Call */
47 1.1 ws #define EXC_TRC 0x0d00 /* Trace */
48 1.1 ws #define EXC_FPA 0x0e00 /* Floating-point Assist */
49 1.7 kleink
50 1.13 macallan /* The following are only available on the 601: */
51 1.13 macallan #define EXC_IOC 0x0a00 /* I/O Controller Interface Exception */
52 1.7 kleink #define EXC_RUNMODETRC 0x2000 /* Run Mode/Trace Exception */
53 1.1 ws
54 1.4 matt /* The following are only available on 7400(G4): */
55 1.4 matt #define EXC_VEC 0x0f20 /* AltiVec Unavailable */
56 1.4 matt #define EXC_VECAST 0x1600 /* AltiVec Assist */
57 1.4 matt
58 1.4 matt /* The following are only available on 604/750/7400: */
59 1.1 ws #define EXC_PERF 0x0f00 /* Performance Monitoring */
60 1.1 ws #define EXC_BPT 0x1300 /* Instruction Breakpoint */
61 1.9 wiz #define EXC_SMI 0x1400 /* System Management Interrupt */
62 1.5 tsubai
63 1.5 tsubai /* The following are only available on 750/7400: */
64 1.5 tsubai #define EXC_THRM 0x1700 /* Thermal Management Interrupt */
65 1.1 ws
66 1.1 ws /* And these are only on the 603: */
67 1.1 ws #define EXC_IMISS 0x1000 /* Instruction translation miss */
68 1.1 ws #define EXC_DLMISS 0x1100 /* Data load translation miss */
69 1.1 ws #define EXC_DSMISS 0x1200 /* Data store translation miss */
70 1.6 simonb
71 1.6 simonb /* The following are only available on 405 (and 403?) */
72 1.6 simonb #define EXC_CII 0x0100 /* Critical Input Interrupt */
73 1.6 simonb #define EXC_PIT 0x1000 /* Programmable Interval Timer */
74 1.6 simonb #define EXC_FIT 0x1010 /* Fixed Interval Timer */
75 1.6 simonb #define EXC_WDOG 0x1020 /* Watchdog Timer */
76 1.6 simonb #define EXC_DTMISS 0x1100 /* Data TLB Miss */
77 1.6 simonb #define EXC_ITMISS 0x1200 /* Instruction TLB Miss */
78 1.6 simonb #define EXC_DEBUG 0x2000 /* Debug trap */
79 1.1 ws
80 1.12 matt /* The following are only available on mpc8xx */
81 1.12 matt #define EXC_SWEMUL 0x1000 /* Software Emulation */
82 1.12 matt #define EXC_ITMISS_8XX 0x1100 /* Instruction TLB Miss */
83 1.12 matt #define EXC_DTMISS_8XX 0x1200 /* Data TLB Miss */
84 1.12 matt #define EXC_ITERROR 0x1300 /* Instruction TLB Error */
85 1.12 matt #define EXC_DTERROR 0x1400 /* Data TLB Error */
86 1.12 matt #define EXC_DBREAK 0x1c00 /* data breakpoint */
87 1.12 matt #define EXC_IBREAK 0x1d00 /* instructin breakpoint */
88 1.12 matt
89 1.10 sanjayl /* The following are only present on 64 bit PPC implementations */
90 1.10 sanjayl #define EXC_DSEG 0x380
91 1.10 sanjayl #define EXC_ISEG 0x480
92 1.10 sanjayl
93 1.10 sanjayl /* The IBM 970x define the VMX assist exection to be 0x1700 */
94 1.10 sanjayl #define EXC_970_VECAST 0x1700
95 1.10 sanjayl
96 1.1 ws #define EXC_LAST 0x2f00 /* Last possible exception vector */
97 1.1 ws
98 1.1 ws #define EXC_AST 0x3000 /* Fake AST vector */
99 1.1 ws
100 1.1 ws /* Trap was in user mode */
101 1.1 ws #define EXC_USER 0x10000
102 1.2 danw
103 1.11 phx /* Exception vector base address when MSR[IP] is set */
104 1.11 phx #define EXC_HIGHVEC 0xfff00000
105 1.2 danw
106 1.2 danw /*
107 1.2 danw * EXC_ALI sets bits in the DSISR and DAR to provide enough
108 1.2 danw * information to recover from the unaligned access without needing to
109 1.2 danw * parse the offending instruction. This includes certain bits of the
110 1.2 danw * opcode, and information about what registers are used. The opcode
111 1.2 danw * indicator values below come from Appendix F of Book III of "The
112 1.2 danw * PowerPC Architecture".
113 1.2 danw */
114 1.2 danw
115 1.2 danw #define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
116 1.13 macallan
117 1.13 macallan #define EXC_ALI_LWARX_LWZ 0x00
118 1.13 macallan #define EXC_ALI_LDARX 0x01
119 1.13 macallan #define EXC_ALI_STW 0x02
120 1.13 macallan #define EXC_ALI_LHZ 0x04
121 1.13 macallan #define EXC_ALI_LHA 0x05
122 1.13 macallan #define EXC_ALI_STH 0x06
123 1.13 macallan #define EXC_ALI_LMW 0x07
124 1.13 macallan #define EXC_ALI_LFS 0x08
125 1.2 danw #define EXC_ALI_LFD 0x09
126 1.13 macallan #define EXC_ALI_STFS 0x0a
127 1.2 danw #define EXC_ALI_STFD 0x0b
128 1.13 macallan #define EXC_ALI_LD_LDU_LWA 0x0d
129 1.13 macallan #define EXC_ALI_STD_STDU 0x0f
130 1.13 macallan #define EXC_ALI_LWZU 0x10
131 1.13 macallan #define EXC_ALI_STWU 0x12
132 1.13 macallan #define EXC_ALI_LHZU 0x14
133 1.13 macallan #define EXC_ALI_LHAU 0x15
134 1.13 macallan #define EXC_ALI_STHU 0x16
135 1.13 macallan #define EXC_ALI_STMW 0x17
136 1.13 macallan #define EXC_ALI_LFSU 0x18
137 1.13 macallan #define EXC_ALI_LFDU 0x19
138 1.13 macallan #define EXC_ALI_STFSU 0x1a
139 1.13 macallan #define EXC_ALI_STFDU 0x1b
140 1.13 macallan #define EXC_ALI_LDX 0x20
141 1.13 macallan #define EXC_ALI_STDX 0x22
142 1.13 macallan #define EXC_ALI_LWAX 0x25
143 1.13 macallan #define EXC_ALI_LSWX 0x28
144 1.13 macallan #define EXC_ALI_LSWI 0x29
145 1.13 macallan #define EXC_ALI_STSWX 0x2a
146 1.13 macallan #define EXC_ALI_STSWI 0x2b
147 1.13 macallan #define EXC_ALI_LDUX 0x30
148 1.13 macallan #define EXC_ALI_STDUX 0x32
149 1.13 macallan #define EXC_ALI_LWAUX 0x35
150 1.13 macallan #define EXC_ALI_STWCX 0x42 /* stwcx. */
151 1.13 macallan #define EXC_ALI_STDCX 0x43 /* stdcx. */
152 1.13 macallan #define EXC_ALI_LWBRX 0x48
153 1.13 macallan #define EXC_ALI_STWBRX 0x4a
154 1.13 macallan #define EXC_ALI_LHBRX 0x4c
155 1.13 macallan #define EXC_ALI_STHBRX 0x4e
156 1.13 macallan #define EXC_ALI_ECIWX 0x54
157 1.13 macallan #define EXC_ALI_ECOWX 0x56
158 1.8 augustss #define EXC_ALI_DCBZ 0x5f
159 1.13 macallan #define EXC_ALI_LWZX 0x60
160 1.13 macallan #define EXC_ALI_STWX 0x62
161 1.13 macallan #define EXC_ALI_LHZX 0x64
162 1.13 macallan #define EXC_ALI_LHAX 0x65
163 1.13 macallan #define EXC_ALI_STHX 0x66
164 1.13 macallan #define EXC_ALI_LSFX 0x68
165 1.13 macallan #define EXC_ALI_LDFX 0x69
166 1.13 macallan #define EXC_ALI_STFSX 0x6a
167 1.13 macallan #define EXC_ALI_STFDX 0x6b
168 1.13 macallan #define EXC_ALI_STFIWX 0x6f
169 1.13 macallan #define EXC_ALI_LWZUX 0x70
170 1.13 macallan #define EXC_ALI_STWUX 0x72
171 1.13 macallan #define EXC_ALI_LHZUX 0x74
172 1.13 macallan #define EXC_ALI_LHAUX 0x75
173 1.13 macallan #define EXC_ALI_STHUX 0x76
174 1.13 macallan #define EXC_ALI_LFSUX 0x78
175 1.13 macallan #define EXC_ALI_LFDUX 0x79
176 1.13 macallan #define EXC_ALI_STFSUX 0x7a
177 1.13 macallan #define EXC_ALI_STFDUX 0x7b
178 1.2 danw
179 1.2 danw /* Macros to extract register information */
180 1.2 danw #define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */
181 1.2 danw #define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
182 1.1 ws
183 1.13 macallan /* Helper defines to classify EXC_ALI_ */
184 1.13 macallan #define DSI_OP_ZERO 0x0001
185 1.13 macallan #define DSI_OP_UPDATE 0x0002
186 1.13 macallan #define DSI_OP_INDEXED 0x0004
187 1.13 macallan #define DSI_OP_ALGEBRAIC 0x0008
188 1.13 macallan #define DSI_OP_REVERSED 0x0010
189 1.13 macallan
190 1.3 is #endif /* _POWERPC_TRAP_H_ */
191