marvell_intr.h revision 1.13
1 /* $NetBSD: marvell_intr.h,v 1.13 2007/12/03 15:34:13 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MVPPPC_INTR_H_ 40 #define _MVPPPC_INTR_H_ 41 42 /* 43 * Interrupt Priority Levels 44 */ 45 #define IPL_NONE 0 /* nothing */ 46 #define IPL_SOFTCLOCK 1 /* timeouts */ 47 #define IPL_SOFTBIO 2 /* block I/O */ 48 #define IPL_SOFTNET 3 /* protocol stacks */ 49 #define IPL_SOFTSERIAL 4 /* serial */ 50 #define IPL_VM 12 /* memory allocation */ 51 #define IPL_SCHED 14 /* clock */ 52 #define IPL_HIGH 15 /* everything */ 53 #define NIPL 16 54 #define IPL_PRIMASK 0xf 55 #define IPL_EE 0x10 /* enable external interrupts on splx */ 56 57 /* Interrupt sharing types. */ 58 #define IST_NONE 0 /* none */ 59 #define IST_PULSE 1 /* pulsed */ 60 #define IST_EDGE 2 /* edge-triggered */ 61 #define IST_LEVEL 3 /* level-triggered */ 62 #define IST_SOFT 4 /* software-triggered */ 63 #define IST_CLOCK 5 /* exclusive for clock */ 64 #define NIST 6 65 66 #if !defined(_LOCORE) && defined(_KERNEL) 67 68 #define CLKF_BASEPRI(frame) ((frame)->pri == IPL_NONE) 69 70 /* 71 * we support 128 IRQs: 72 * 96 (ICU_LEN) hard interrupt IRQs: 73 * - 64 Main Cause IRQs, 74 * - 32 GPP IRQs, 75 * and 32 softint IRQs 76 */ 77 #define ICU_LEN 96 /* number of HW IRQs */ 78 #define IRQ_GPP_BASE 64 /* base of GPP IRQs */ 79 #define IRQ_GPP_SUM (32+24) /* GPP[7..0] interrupt */ /* XXX */ 80 #define NIRQ 128 /* total # of HW IRQs */ 81 82 #define IMASK_ICU_LO 0 83 #define IMASK_ICU_HI 1 84 #define IMASK_ICU_GPP 2 85 #define IMASK_SOFTINT 3 86 #define IMASK_WORDSHIFT 5 /* log2(32) */ 87 #define IMASK_BITMASK ~((~0) << IMASK_WORDSHIFT) 88 89 #define IRQ_IS_GPP(irq) ((irq >= IRQ_GPP_BASE) && (irq < ICU_LEN)) 90 91 /* 92 * interrupt mask bit vector 93 */ 94 typedef struct { 95 u_int32_t bits[4]; 96 } imask_t __attribute__ ((aligned(16))); 97 98 static inline void imask_zero(imask_t *); 99 static inline void imask_zero_v(volatile imask_t *); 100 static inline void imask_dup_v(imask_t *, const volatile imask_t *); 101 static inline void imask_and(imask_t *, const imask_t *); 102 static inline void imask_andnot_v(volatile imask_t *, const imask_t *); 103 static inline void imask_andnot_icu_vv(volatile imask_t *, const volatile imask_t *); 104 static inline int imask_empty(const imask_t *); 105 static inline void imask_orbit(imask_t *, int); 106 static inline void imask_orbit_v(volatile imask_t *, int); 107 static inline void imask_clrbit(imask_t *, int); 108 static inline void imask_clrbit_v(volatile imask_t *, int); 109 static inline u_int32_t imask_andbit_v(const volatile imask_t *, int); 110 static inline int imask_test_v(const volatile imask_t *, const imask_t *); 111 112 static inline void 113 imask_zero(imask_t *idp) 114 { 115 idp->bits[IMASK_ICU_LO] = 0; 116 idp->bits[IMASK_ICU_HI] = 0; 117 idp->bits[IMASK_ICU_GPP] = 0; 118 idp->bits[IMASK_SOFTINT] = 0; 119 } 120 121 static inline void 122 imask_zero_v(volatile imask_t *idp) 123 { 124 idp->bits[IMASK_ICU_LO] = 0; 125 idp->bits[IMASK_ICU_HI] = 0; 126 idp->bits[IMASK_ICU_GPP] = 0; 127 idp->bits[IMASK_SOFTINT] = 0; 128 } 129 130 static inline void 131 imask_dup_v(imask_t *idp, const volatile imask_t *isp) 132 { 133 *idp = *isp; 134 } 135 136 static inline void 137 imask_and(imask_t *idp, const imask_t *isp) 138 { 139 idp->bits[IMASK_ICU_LO] &= isp->bits[IMASK_ICU_LO]; 140 idp->bits[IMASK_ICU_HI] &= isp->bits[IMASK_ICU_HI]; 141 idp->bits[IMASK_ICU_GPP] &= isp->bits[IMASK_ICU_GPP]; 142 idp->bits[IMASK_SOFTINT] &= isp->bits[IMASK_SOFTINT]; 143 } 144 145 static inline void 146 imask_andnot_v(volatile imask_t *idp, const imask_t *isp) 147 { 148 idp->bits[IMASK_ICU_LO] &= ~isp->bits[IMASK_ICU_LO]; 149 idp->bits[IMASK_ICU_HI] &= ~isp->bits[IMASK_ICU_HI]; 150 idp->bits[IMASK_ICU_GPP] &= ~isp->bits[IMASK_ICU_GPP]; 151 idp->bits[IMASK_SOFTINT] &= ~isp->bits[IMASK_SOFTINT]; 152 } 153 154 static inline void 155 imask_andnot_icu_vv(volatile imask_t *idp, const volatile imask_t *isp) 156 { 157 idp->bits[IMASK_ICU_LO] &= ~isp->bits[IMASK_ICU_LO]; 158 idp->bits[IMASK_ICU_HI] &= ~isp->bits[IMASK_ICU_HI]; 159 idp->bits[IMASK_ICU_GPP] &= ~isp->bits[IMASK_ICU_GPP]; 160 } 161 162 static inline int 163 imask_empty(const imask_t *isp) 164 { 165 return (! (isp->bits[IMASK_ICU_LO] | isp->bits[IMASK_ICU_HI] | 166 isp->bits[IMASK_ICU_GPP]| isp->bits[IMASK_SOFTINT])); 167 } 168 169 static inline void 170 imask_orbit(imask_t *idp, int bitno) 171 { 172 idp->bits[bitno>>IMASK_WORDSHIFT] |= (1 << (bitno&IMASK_BITMASK)); 173 } 174 175 static inline void 176 imask_orbit_v(volatile imask_t *idp, int bitno) 177 { 178 idp->bits[bitno>>IMASK_WORDSHIFT] |= (1 << (bitno&IMASK_BITMASK)); 179 } 180 181 static inline void 182 imask_clrbit(imask_t *idp, int bitno) 183 { 184 idp->bits[bitno>>IMASK_WORDSHIFT] &= ~(1 << (bitno&IMASK_BITMASK)); 185 } 186 187 static inline void 188 imask_clrbit_v(volatile imask_t *idp, int bitno) 189 { 190 idp->bits[bitno>>IMASK_WORDSHIFT] &= ~(1 << (bitno&IMASK_BITMASK)); 191 } 192 193 static inline u_int32_t 194 imask_andbit_v(const volatile imask_t *idp, int bitno) 195 { 196 return idp->bits[bitno>>IMASK_WORDSHIFT] & (1 << (bitno&IMASK_BITMASK)); 197 } 198 199 static inline int 200 imask_test_v(const volatile imask_t *idp, const imask_t *isp) 201 { 202 return ((idp->bits[IMASK_ICU_LO] & isp->bits[IMASK_ICU_LO]) || 203 (idp->bits[IMASK_ICU_HI] & isp->bits[IMASK_ICU_HI]) || 204 (idp->bits[IMASK_ICU_GPP] & isp->bits[IMASK_ICU_GPP])|| 205 (idp->bits[IMASK_SOFTINT] & isp->bits[IMASK_SOFTINT])); 206 } 207 208 #ifdef EXT_INTR_STATS 209 /* 210 * ISR timing stats 211 */ 212 213 typedef struct ext_intr_hist { 214 u_int64_t tcause; 215 u_int64_t tcommit; 216 u_int64_t tstart; 217 u_int64_t tfin; 218 } ext_intr_hist_t __attribute__ ((aligned(32))); 219 220 typedef struct ext_intr_stat { 221 struct ext_intr_hist *histp; 222 unsigned int histix; 223 u_int64_t cnt; 224 u_int64_t sum; 225 u_int64_t min; 226 u_int64_t max; 227 u_int64_t pnd; 228 u_int64_t borrowed; 229 struct ext_intr_stat *save; 230 unsigned long preempted[NIRQ]; /* XXX */ 231 } ext_intr_stat_t __attribute__ ((aligned(32))); 232 233 extern int intr_depth_max; 234 extern int ext_intr_stats_enb; 235 extern ext_intr_stat_t ext_intr_stats[]; 236 extern ext_intr_stat_t *ext_intr_statp; 237 238 extern void ext_intr_stats_init __P((void)); 239 extern void ext_intr_stats_cause 240 __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 241 extern void ext_intr_stats_pend 242 __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 243 extern void ext_intr_stats_commit __P((imask_t *)); 244 extern void ext_intr_stats_commit_m __P((imask_t *)); 245 extern void ext_intr_stats_commit_irq __P((u_int)); 246 extern u_int64_t ext_intr_stats_pre __P((int)); 247 extern void ext_intr_stats_post __P((int, u_int64_t)); 248 249 #define EXT_INTR_STATS_INIT() ext_intr_stats_init() 250 #define EXT_INTR_STATS_CAUSE(l, h, g, s) ext_intr_stats_cause(l, h, g, s) 251 #define EXT_INTR_STATS_COMMIT_M(m) ext_intr_stats_commit_m(m) 252 #define EXT_INTR_STATS_COMMIT_IRQ(i) ext_intr_stats_commit_irq(i) 253 #define EXT_INTR_STATS_DECL(t) u_int64_t t 254 #define EXT_INTR_STATS_PRE(i, t) t = ext_intr_stats_pre(i) 255 #define EXT_INTR_STATS_POST(i, t) ext_intr_stats_post(i, t) 256 #define EXT_INTR_STATS_PEND(l, h, g, s) ext_intr_stats_pend(l, h, g, s) 257 #define EXT_INTR_STATS_PEND_IRQ(i) ext_intr_stats[i].pnd++ 258 #define EXT_INTR_STATS_DEPTH() \ 259 intr_depth_max = (intr_depth > intr_depth_max) ? \ 260 intr_depth : intr_depth_max 261 262 #else /* EXT_INTR_STATS */ 263 264 #define EXT_INTR_STATS_INIT() 265 #define EXT_INTR_STATS_CAUSE(l, h, g, s) 266 #define EXT_INTR_STATS_COMMIT_M(m) 267 #define EXT_INTR_STATS_COMMIT_IRQ(i) 268 #define EXT_INTR_STATS_DECL(t) 269 #define EXT_INTR_STATS_PRE(irq, t) 270 #define EXT_INTR_STATS_POST(i, t) 271 #define EXT_INTR_STATS_PEND(l, h, g, s) 272 #define EXT_INTR_STATS_PEND_IRQ(i) 273 #define EXT_INTR_STATS_DEPTH() 274 275 #endif /* EXT_INTR_STATS */ 276 277 278 #ifdef SPL_STATS 279 typedef struct spl_hist { 280 int level; 281 void *addr; 282 u_int64_t time; 283 } spl_hist_t; 284 285 extern void spl_stats_init(); 286 extern void spl_stats_log(); 287 extern unsigned int spl_stats_enb; 288 289 #define SPL_STATS_INIT() spl_stats_init() 290 #define SPL_STATS_LOG(ipl, cc) spl_stats_log((ipl), (cc)) 291 292 #else 293 294 #define SPL_STATS_INIT() 295 #define SPL_STATS_LOG(ipl, cc) 296 297 #endif /* SPL_STATS */ 298 299 300 void intr_dispatch __P((void)); 301 #ifdef SPL_INLINE 302 static inline int splraise __P((int)); 303 static inline int spllower __P((int)); 304 static inline void splx __P((int)); 305 #else 306 extern int splraise __P((int)); 307 extern int spllower __P((int)); 308 extern void splx __P((int)); 309 #endif 310 311 extern volatile int tickspending; 312 313 extern volatile imask_t ipending; 314 extern imask_t imask[]; 315 316 /* 317 * inlines for manipulating PSL_EE 318 */ 319 static inline void 320 extintr_restore(register_t omsr) 321 { 322 __asm volatile ("sync; mtmsr %0;" :: "r"(omsr)); 323 } 324 325 static inline register_t 326 extintr_enable(void) 327 { 328 register_t omsr; 329 330 __asm volatile("sync;"); 331 __asm volatile("mfmsr %0;" : "=r"(omsr)); 332 __asm volatile("mtmsr %0;" :: "r"(omsr | PSL_EE)); 333 334 return omsr; 335 } 336 337 static inline register_t 338 extintr_disable(void) 339 { 340 register_t omsr; 341 342 __asm volatile("mfmsr %0;" : "=r"(omsr)); 343 __asm volatile("mtmsr %0;" :: "r"(omsr & ~PSL_EE)); 344 __asm volatile("isync;"); 345 346 return omsr; 347 } 348 349 #ifdef SPL_INLINE 350 static inline int 351 splraise(int ncpl) 352 { 353 int ocpl; 354 register_t omsr; 355 356 omsr = extintr_disable(); 357 ocpl = cpl; 358 if (ncpl > cpl) { 359 SPL_STATS_LOG(ncpl, 0); 360 cpl = ncpl; 361 if ((ncpl == IPL_HIGH) && ((omsr & PSL_EE) != 0)) { 362 /* leave external interrupts disabled */ 363 return (ocpl | IPL_EE); 364 } 365 } 366 extintr_restore(omsr); 367 return (ocpl); 368 } 369 370 static inline void 371 splx(int xcpl) 372 { 373 imask_t *ncplp; 374 register_t omsr; 375 int ncpl = xcpl & IPL_PRIMASK; 376 377 ncplp = &imask[ncpl]; 378 379 omsr = extintr_disable(); 380 if (ncpl < cpl) { 381 cpl = ncpl; 382 SPL_STATS_LOG(ncpl, 0); 383 if (imask_test_v(&ipending, ncplp)) 384 intr_dispatch(); 385 } 386 if (xcpl & IPL_EE) 387 omsr |= PSL_EE; 388 extintr_restore(omsr); 389 } 390 391 static inline int 392 spllower(int ncpl) 393 { 394 int ocpl; 395 imask_t *ncplp; 396 register_t omsr; 397 398 ncpl &= IPL_PRIMASK; 399 ncplp = &imask[ncpl]; 400 401 omsr = extintr_disable(); 402 ocpl = cpl; 403 cpl = ncpl; 404 SPL_STATS_LOG(ncpl, 0); 405 #ifdef EXT_INTR_STATS 406 ext_intr_statp = 0; 407 #endif 408 if (imask_test_v(&ipending, ncplp)) 409 intr_dispatch(); 410 411 if (ncpl < IPL_HIGH) 412 omsr |= PSL_EE; 413 extintr_restore(omsr); 414 415 return (ocpl); 416 } 417 #endif /* SPL_INLINE */ 418 419 420 /* 421 * Soft interrupt IRQs 422 * see also intrnames[] in locore.S 423 */ 424 #define SIR_BASE (NIRQ-32) 425 #define SIXBIT(ipl) ((ipl) - SIR_BASE) /* XXX rennovate later */ 426 #define SIR_SOFTCLOCK (NIRQ-5) 427 #define SIR_CLOCK SIXBIT(SIR_SOFTCLOCK) /* XXX rennovate later */ 428 #define SIR_SOFTNET (NIRQ-4) 429 #define SIR_SOFTBIO (NIRQ-3) 430 #define SIR_SOFTSERIAL (NIRQ-2) 431 #define SIR_HWCLOCK (NIRQ-1) 432 #define SPL_CLOCK SIXBIT(SIR_HWCLOCK) /* XXX rennovate later */ 433 #define SIR_RES ~(SIBIT(SIR_SOFTCLOCK)|\ 434 SIBIT(SIR_SOFTNET)|\ 435 SIBIT(SIR_SOFTBIO)|\ 436 SIBIT(SIR_SOFTSERIAL)|\ 437 SIBIT(SIR_HWCLOCK)) 438 439 struct intrhand; 440 441 /* 442 * Miscellaneous 443 */ 444 #define spl0() spllower(IPL_NONE) 445 446 typedef int ipl_t; 447 typedef struct { 448 ipl_t _ipl; 449 } ipl_cookie_t; 450 451 static inline ipl_cookie_t 452 makeiplcookie(ipl_t ipl) 453 { 454 455 return (ipl_cookie_t){._ipl = ipl}; 456 } 457 458 static inline int 459 splraiseipl(ipl_cookie_t icookie) 460 { 461 462 return splraise(icookie._ipl); 463 } 464 465 #include <sys/spl.h> 466 467 #define SIBIT(ipl) (1 << ((ipl) - SIR_BASE)) 468 469 void *intr_establish(int, int, int, int (*)(void *), void *); 470 void intr_disestablish(void *); 471 void init_interrupt(void); 472 const char * intr_typename(int); 473 const char * intr_string(int); 474 const struct evcnt * intr_evcnt(int); 475 void ext_intr(struct intrframe *); 476 477 /* the following are needed to compile until this port is properly 478 * converted to ppcoea-rennovation. 479 */ 480 void genppc_cpu_configure(void); 481 482 void strayintr(int); 483 484 /* 485 * defines for indexing intrcnt 486 */ 487 #define CNT_IRQ0 0 488 #define CNT_CLOCK SIR_HWCLOCK 489 #define CNT_SOFTCLOCK SIR_SOFTCLOCK 490 #define CNT_SOFTNET SIR_NET 491 #define CNT_SOFTSERIAL SIR_SOFTSERIAL 492 #define CNT_SOFTBIO SIR_BIO 493 494 #endif /* !_LOCORE */ 495 496 #endif /* _MVPPPC_INTR_H_ */ 497
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