marvell_intr.h revision 1.6
1 /* $NetBSD: marvell_intr.h,v 1.6 2003/09/03 21:33:36 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MVPPPC_INTR_H_ 40 #define _MVPPPC_INTR_H_ 41 42 /* 43 * Interrupt Priority Levels 44 */ 45 #define IPL_NONE 0 /* nothing */ 46 #define IPL_SOFTCLOCK 1 /* timeouts */ 47 #define IPL_SOFTNET 2 /* protocol stacks */ 48 #define IPL_BIO 3 /* block I/O */ 49 #define IPL_NET 4 /* network */ 50 #define IPL_NCP 5 /* network processors */ 51 #define IPL_SOFTI2C 6 /* i2c */ 52 #define IPL_SOFTSERIAL 7 /* serial */ 53 #define IPL_TTY 8 /* terminal */ 54 #define IPL_AUDIO 9 /* boom box */ 55 #define IPL_EJECT 10 /* card eject */ 56 #define IPL_GTERR 10 /* GT-64260 errors */ 57 #define IPL_I2C 11 /* i2c */ 58 #define IPL_VM 12 /* memory allocation */ 59 #define IPL_SERIAL 13 /* serial */ 60 #define IPL_CLOCK 14 /* clock */ 61 #define IPL_SCHED 14 /* schedular */ 62 #define IPL_LOCK 14 /* same as high for now */ 63 #define IPL_HIGH 15 /* everything */ 64 #define NIPL 16 65 #define IPL_PRIMASK 0xf 66 #define IPL_EE 0x10 /* enable external interrupts on splx */ 67 68 /* Interrupt sharing types. */ 69 #define IST_NONE 0 /* none */ 70 #define IST_PULSE 1 /* pulsed */ 71 #define IST_EDGE 2 /* edge-triggered */ 72 #define IST_LEVEL 3 /* level-triggered */ 73 #define IST_SOFT 4 /* software-triggered */ 74 #define IST_CLOCK 5 /* exclusive for clock */ 75 #define NIST 6 76 77 #if !defined(_LOCORE) && defined(_KERNEL) 78 79 #define CLKF_BASEPRI(frame) ((frame)->pri == IPL_NONE) 80 81 /* 82 * we support 128 IRQs: 83 * 96 (ICU_LEN) hard interrupt IRQs: 84 * - 64 Main Cause IRQs, 85 * - 32 GPP IRQs, 86 * and 32 softint IRQs 87 */ 88 #define ICU_LEN 96 /* number of HW IRQs */ 89 #define IRQ_GPP_BASE 64 /* base of GPP IRQs */ 90 #define IRQ_GPP_SUM (32+24) /* GPP[7..0] interrupt */ /* XXX */ 91 #define NIRQ 128 /* total # of HW IRQs */ 92 93 #define IMASK_ICU_LO 0 94 #define IMASK_ICU_HI 1 95 #define IMASK_ICU_GPP 2 96 #define IMASK_SOFTINT 3 97 #define IMASK_WORDSHIFT 5 /* log2(32) */ 98 #define IMASK_BITMASK ~((~0) << IMASK_WORDSHIFT) 99 100 #define IRQ_IS_GPP(irq) ((irq >= IRQ_GPP_BASE) && (irq < ICU_LEN)) 101 102 /* 103 * interrupt mask bit vector 104 */ 105 typedef struct { 106 u_int32_t bits[4]; 107 } imask_t __attribute__ ((aligned(16))); 108 109 static __inline void imask_zero(imask_t *); 110 static __inline void imask_zero_v(volatile imask_t *); 111 static __inline void imask_dup_v(imask_t *, const volatile imask_t *); 112 static __inline void imask_and(imask_t *, const imask_t *); 113 static __inline void imask_andnot_v(volatile imask_t *, const imask_t *); 114 static __inline void imask_andnot_icu_vv(volatile imask_t *, const volatile imask_t *); 115 static __inline int imask_empty(const imask_t *); 116 static __inline void imask_orbit(imask_t *, int); 117 static __inline void imask_orbit_v(volatile imask_t *, int); 118 static __inline void imask_clrbit(imask_t *, int); 119 static __inline void imask_clrbit_v(volatile imask_t *, int); 120 static __inline u_int32_t imask_andbit_v(const volatile imask_t *, int); 121 static __inline int imask_test_v(const volatile imask_t *, const imask_t *); 122 123 static __inline void 124 imask_zero(imask_t *idp) 125 { 126 idp->bits[IMASK_ICU_LO] = 0; 127 idp->bits[IMASK_ICU_HI] = 0; 128 idp->bits[IMASK_ICU_GPP] = 0; 129 idp->bits[IMASK_SOFTINT] = 0; 130 } 131 132 static __inline void 133 imask_zero_v(volatile imask_t *idp) 134 { 135 idp->bits[IMASK_ICU_LO] = 0; 136 idp->bits[IMASK_ICU_HI] = 0; 137 idp->bits[IMASK_ICU_GPP] = 0; 138 idp->bits[IMASK_SOFTINT] = 0; 139 } 140 141 static __inline void 142 imask_dup_v(imask_t *idp, const volatile imask_t *isp) 143 { 144 *idp = *isp; 145 } 146 147 static __inline void 148 imask_and(imask_t *idp, const imask_t *isp) 149 { 150 idp->bits[IMASK_ICU_LO] &= isp->bits[IMASK_ICU_LO]; 151 idp->bits[IMASK_ICU_HI] &= isp->bits[IMASK_ICU_HI]; 152 idp->bits[IMASK_ICU_GPP] &= isp->bits[IMASK_ICU_GPP]; 153 idp->bits[IMASK_SOFTINT] &= isp->bits[IMASK_SOFTINT]; 154 } 155 156 static __inline void 157 imask_andnot_v(volatile imask_t *idp, const imask_t *isp) 158 { 159 idp->bits[IMASK_ICU_LO] &= ~isp->bits[IMASK_ICU_LO]; 160 idp->bits[IMASK_ICU_HI] &= ~isp->bits[IMASK_ICU_HI]; 161 idp->bits[IMASK_ICU_GPP] &= ~isp->bits[IMASK_ICU_GPP]; 162 idp->bits[IMASK_SOFTINT] &= ~isp->bits[IMASK_SOFTINT]; 163 } 164 165 static __inline void 166 imask_andnot_icu_vv(volatile imask_t *idp, const volatile imask_t *isp) 167 { 168 idp->bits[IMASK_ICU_LO] &= ~isp->bits[IMASK_ICU_LO]; 169 idp->bits[IMASK_ICU_HI] &= ~isp->bits[IMASK_ICU_HI]; 170 idp->bits[IMASK_ICU_GPP] &= ~isp->bits[IMASK_ICU_GPP]; 171 } 172 173 static __inline int 174 imask_empty(const imask_t *isp) 175 { 176 return (! (isp->bits[IMASK_ICU_LO] | isp->bits[IMASK_ICU_HI] | 177 isp->bits[IMASK_ICU_GPP]| isp->bits[IMASK_SOFTINT])); 178 } 179 180 static __inline void 181 imask_orbit(imask_t *idp, int bitno) 182 { 183 idp->bits[bitno>>IMASK_WORDSHIFT] |= (1 << (bitno&IMASK_BITMASK)); 184 } 185 186 static __inline void 187 imask_orbit_v(volatile imask_t *idp, int bitno) 188 { 189 idp->bits[bitno>>IMASK_WORDSHIFT] |= (1 << (bitno&IMASK_BITMASK)); 190 } 191 192 static __inline void 193 imask_clrbit(imask_t *idp, int bitno) 194 { 195 idp->bits[bitno>>IMASK_WORDSHIFT] &= ~(1 << (bitno&IMASK_BITMASK)); 196 } 197 198 static __inline void 199 imask_clrbit_v(volatile imask_t *idp, int bitno) 200 { 201 idp->bits[bitno>>IMASK_WORDSHIFT] &= ~(1 << (bitno&IMASK_BITMASK)); 202 } 203 204 static __inline u_int32_t 205 imask_andbit_v(const volatile imask_t *idp, int bitno) 206 { 207 return idp->bits[bitno>>IMASK_WORDSHIFT] & (1 << (bitno&IMASK_BITMASK)); 208 } 209 210 static __inline int 211 imask_test_v(const volatile imask_t *idp, const imask_t *isp) 212 { 213 return ((idp->bits[IMASK_ICU_LO] & isp->bits[IMASK_ICU_LO]) || 214 (idp->bits[IMASK_ICU_HI] & isp->bits[IMASK_ICU_HI]) || 215 (idp->bits[IMASK_ICU_GPP] & isp->bits[IMASK_ICU_GPP])|| 216 (idp->bits[IMASK_SOFTINT] & isp->bits[IMASK_SOFTINT])); 217 } 218 219 #ifdef EXT_INTR_STATS 220 /* 221 * ISR timing stats 222 */ 223 224 typedef struct ext_intr_hist { 225 u_int64_t tcause; 226 u_int64_t tcommit; 227 u_int64_t tstart; 228 u_int64_t tfin; 229 } ext_intr_hist_t __attribute__ ((aligned(32))); 230 231 typedef struct ext_intr_stat { 232 struct ext_intr_hist *histp; 233 unsigned int histix; 234 u_int64_t cnt; 235 u_int64_t sum; 236 u_int64_t min; 237 u_int64_t max; 238 u_int64_t pnd; 239 u_int64_t borrowed; 240 struct ext_intr_stat *save; 241 unsigned long preempted[NIRQ]; /* XXX */ 242 } ext_intr_stat_t __attribute__ ((aligned(32))); 243 244 extern int intr_depth_max; 245 extern int ext_intr_stats_enb; 246 extern ext_intr_stat_t ext_intr_stats[]; 247 extern ext_intr_stat_t *ext_intr_statp; 248 249 extern void ext_intr_stats_init __P((void)); 250 extern void ext_intr_stats_cause 251 __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 252 extern void ext_intr_stats_pend 253 __P((u_int32_t, u_int32_t, u_int32_t, u_int32_t)); 254 extern void ext_intr_stats_commit __P((imask_t *)); 255 extern void ext_intr_stats_commit_m __P((imask_t *)); 256 extern void ext_intr_stats_commit_irq __P((u_int)); 257 extern u_int64_t ext_intr_stats_pre __P((int)); 258 extern void ext_intr_stats_post __P((int, u_int64_t)); 259 260 #define EXT_INTR_STATS_INIT() ext_intr_stats_init() 261 #define EXT_INTR_STATS_CAUSE(l, h, g, s) ext_intr_stats_cause(l, h, g, s) 262 #define EXT_INTR_STATS_COMMIT_M(m) ext_intr_stats_commit_m(m) 263 #define EXT_INTR_STATS_COMMIT_IRQ(i) ext_intr_stats_commit_irq(i) 264 #define EXT_INTR_STATS_DECL(t) u_int64_t t 265 #define EXT_INTR_STATS_PRE(i, t) t = ext_intr_stats_pre(i) 266 #define EXT_INTR_STATS_POST(i, t) ext_intr_stats_post(i, t) 267 #define EXT_INTR_STATS_PEND(l, h, g, s) ext_intr_stats_pend(l, h, g, s) 268 #define EXT_INTR_STATS_PEND_IRQ(i) ext_intr_stats[i].pnd++ 269 #define EXT_INTR_STATS_DEPTH() \ 270 intr_depth_max = (intr_depth > intr_depth_max) ? \ 271 intr_depth : intr_depth_max 272 273 #else /* EXT_INTR_STATS */ 274 275 #define EXT_INTR_STATS_INIT() 276 #define EXT_INTR_STATS_CAUSE(l, h, g, s) 277 #define EXT_INTR_STATS_COMMIT_M(m) 278 #define EXT_INTR_STATS_COMMIT_IRQ(i) 279 #define EXT_INTR_STATS_DECL(t) 280 #define EXT_INTR_STATS_PRE(irq, t) 281 #define EXT_INTR_STATS_POST(i, t) 282 #define EXT_INTR_STATS_PEND(l, h, g, s) 283 #define EXT_INTR_STATS_PEND_IRQ(i) 284 #define EXT_INTR_STATS_DEPTH() 285 286 #endif /* EXT_INTR_STATS */ 287 288 289 #ifdef SPL_STATS 290 typedef struct spl_hist { 291 int level; 292 void *addr; 293 u_int64_t time; 294 } spl_hist_t; 295 296 extern void spl_stats_init(); 297 extern void spl_stats_log(); 298 extern unsigned int spl_stats_enb; 299 300 #define SPL_STATS_INIT() spl_stats_init() 301 #define SPL_STATS_LOG(ipl, cc) spl_stats_log((ipl), (cc)) 302 303 #else 304 305 #define SPL_STATS_INIT() 306 #define SPL_STATS_LOG(ipl, cc) 307 308 #endif /* SPL_STATS */ 309 310 311 void setsoftclock __P((void)); 312 void clearsoftclock __P((void)); 313 int splsoftclock __P((void)); 314 void setsoftnet __P((void)); 315 void clearsoftnet __P((void)); 316 int splsoftnet __P((void)); 317 318 void intr_dispatch __P((void)); 319 #ifdef SPL_INLINE 320 static __inline int splraise __P((int)); 321 static __inline int spllower __P((int)); 322 static __inline void splx __P((int)); 323 #else 324 extern int splraise __P((int)); 325 extern int spllower __P((int)); 326 extern void splx __P((int)); 327 #endif 328 329 extern volatile int tickspending; 330 331 extern volatile imask_t ipending; 332 extern imask_t imask[]; 333 334 /* 335 * inlines for manipulating PSL_EE 336 */ 337 static __inline void 338 extintr_restore(register_t omsr) 339 { 340 __asm __volatile ("sync; mtmsr %0;" :: "r"(omsr)); 341 } 342 343 static __inline register_t 344 extintr_enable(void) 345 { 346 register_t omsr; 347 348 __asm __volatile("sync;"); 349 __asm __volatile("mfmsr %0;" : "=r"(omsr)); 350 __asm __volatile("mtmsr %0;" :: "r"(omsr | PSL_EE)); 351 352 return omsr; 353 } 354 355 static __inline register_t 356 extintr_disable(void) 357 { 358 register_t omsr; 359 360 __asm __volatile("mfmsr %0;" : "=r"(omsr)); 361 __asm __volatile("mtmsr %0;" :: "r"(omsr & ~PSL_EE)); 362 __asm __volatile("isync;"); 363 364 return omsr; 365 } 366 367 #ifdef SPL_INLINE 368 static __inline int 369 splraise(int ncpl) 370 { 371 int ocpl; 372 register_t omsr; 373 374 omsr = extintr_disable(); 375 ocpl = cpl; 376 if (ncpl > cpl) { 377 SPL_STATS_LOG(ncpl, 0); 378 cpl = ncpl; 379 if ((ncpl == IPL_HIGH) && ((omsr & PSL_EE) != 0)) { 380 /* leave external interrupts disabled */ 381 return (ocpl | IPL_EE); 382 } 383 } 384 extintr_restore(omsr); 385 return (ocpl); 386 } 387 388 static __inline void 389 splx(int xcpl) 390 { 391 imask_t *ncplp; 392 register_t omsr; 393 int ncpl = xcpl & IPL_PRIMASK; 394 395 ncplp = &imask[ncpl]; 396 397 omsr = extintr_disable(); 398 if (ncpl < cpl) { 399 cpl = ncpl; 400 SPL_STATS_LOG(ncpl, 0); 401 if (imask_test_v(&ipending, ncplp)) 402 intr_dispatch(); 403 } 404 if (xcpl & IPL_EE) 405 omsr |= PSL_EE; 406 extintr_restore(omsr); 407 } 408 409 static __inline int 410 spllower(int ncpl) 411 { 412 int ocpl; 413 imask_t *ncplp; 414 register_t omsr; 415 416 ncpl &= IPL_PRIMASK; 417 ncplp = &imask[ncpl]; 418 419 omsr = extintr_disable(); 420 ocpl = cpl; 421 cpl = ncpl; 422 SPL_STATS_LOG(ncpl, 0); 423 #ifdef EXT_INTR_STATS 424 ext_intr_statp = 0; 425 #endif 426 if (imask_test_v(&ipending, ncplp)) 427 intr_dispatch(); 428 429 if (ncpl < IPL_HIGH) 430 omsr |= PSL_EE; 431 extintr_restore(omsr); 432 433 return (ocpl); 434 } 435 #endif /* SPL_INLINE */ 436 437 438 /* 439 * Soft interrupt IRQs 440 * see also intrnames[] in locore.S 441 */ 442 #define SIR_BASE (NIRQ-32) 443 #define SIR_SOFTCLOCK (NIRQ-5) 444 #define SIR_SOFTNET (NIRQ-4) 445 #define SIR_SOFTI2C (NIRQ-3) 446 #define SIR_SOFTSERIAL (NIRQ-2) 447 #define SIR_HWCLOCK (NIRQ-1) 448 #define SIR_RES ~(SIBIT(SIR_SOFTCLOCK)|\ 449 SIBIT(SIR_SOFTNET)|\ 450 SIBIT(SIR_SOFTI2C)|\ 451 SIBIT(SIR_SOFTSERIAL)|\ 452 SIBIT(SIR_HWCLOCK)) 453 454 /* 455 * standard hardware interrupt spl's 456 */ 457 #define splbio() splraise(IPL_BIO) 458 #define splnet() splraise(IPL_NET) 459 #define spltty() splraise(IPL_TTY) 460 #define splaudio() splraise(IPL_AUDIO) 461 #define splsched() splraise(IPL_SCHED) 462 #define splclock() splraise(IPL_CLOCK) 463 #define splstatclock() splclock() 464 #define splserial() splraise(IPL_SERIAL) 465 466 #define spllpt() spltty() 467 468 /* 469 * Software interrupt spl's 470 * 471 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 472 * clock to softclock before it calls softclock(). 473 */ 474 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 475 #define splsoftclock() splraise(IPL_SOFTCLOCK) 476 #define splsoftnet() splraise(IPL_SOFTNET) 477 #define splsoftserial() splraise(IPL_SOFTSERIAL) 478 479 #define __HAVE_GENERIC_SOFT_INTERRUPTS /* should be in <machine/types.h> */ 480 void *softintr_establish(int level, void (*fun)(void *), void *arg); 481 void softintr_disestablish(void *cookie); 482 void softintr_schedule(void *cookie); 483 484 485 /* 486 * Miscellaneous 487 */ 488 #define splvm() splraise(IPL_VM) 489 #define spllock() splraise(IPL_LOCK) 490 #define splhigh() splraise(IPL_HIGH) 491 #define spl0() spllower(IPL_NONE) 492 493 #define SIBIT(ipl) (1 << ((ipl) - SIR_BASE)) 494 #if 0 495 #define setsoftclock() softintr(SIBIT(SIR_SOFTCLOCK)) 496 #define setsoftnet() softintr(SIBIT(SIR_SOFTNET)) 497 #define setsoftserial() softintr(SIBIT(SIR_SOFTSERIAL)) 498 #define setsofti2c() softintr(SIBIT(SIR_SOFTI2C)) 499 #endif 500 501 extern void *softnet_si; 502 void *intr_establish(int, int, int, int (*)(void *), void *); 503 void intr_disestablish(void *); 504 void init_interrupt(void); 505 const char * intr_typename(int); 506 const char * intr_string(int); 507 const struct evcnt * intr_evcnt(int); 508 void ext_intr(struct intrframe *); 509 510 #if 0 511 void softserial(void); 512 #endif 513 void strayintr(int); 514 515 #define schednetisr(isr) do { \ 516 __asm __volatile( \ 517 "1: lwarx 0,0,%1\n" \ 518 " or 0,0,%0\n" \ 519 " stwcx. 0,0,%1\n" \ 520 " bne- 1b" \ 521 : \ 522 : "r"(1 << (isr)), "b"(&netisr) \ 523 : "cr0", "r0"); \ 524 softintr_schedule(softnet_si); \ 525 } while (/*CONSTCOND*/ 0) 526 527 /* 528 * defines for indexing intrcnt 529 */ 530 #define CNT_IRQ0 0 531 #define CNT_CLOCK SIR_HWCLOCK 532 #define CNT_SOFTCLOCK SIR_SOFTCLOCK 533 #define CNT_SOFTNET SIR_NET 534 #define CNT_SOFTSERIAL SIR_SOFTSERIAL 535 #define CNT_SOFTI2C SIR_I2C 536 537 #endif /* !_LOCORE */ 538 539 #endif /* _MVPPPC_INTR_H_ */ 540
Indexes created Tue Sep 30 10:09:55 GMT 2025