oea_machdep.c revision 1.24
1 /* $NetBSD: oea_machdep.c,v 1.24 2005/12/24 20:07:28 perry Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.24 2005/12/24 20:07:28 perry Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/sa.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/trap.h> 82 #include <powerpc/stdarg.h> 83 #include <powerpc/spr.h> 84 #include <powerpc/pte.h> 85 #include <powerpc/altivec.h> 86 #include <machine/powerpc.h> 87 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 91 struct vm_map *exec_map = NULL; 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 struct bat battable[512]; 101 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 102 paddr_t msgbuf_paddr; 103 104 void 105 oea_init(void (*handler)(void)) 106 { 107 extern int trapstart[], trapend[]; 108 extern int trapcode[], trapsize[]; 109 extern int sctrap[], scsize[]; 110 extern int alitrap[], alisize[]; 111 extern int dsitrap[], dsisize[]; 112 extern int dsi601trap[], dsi601size[]; 113 extern int decrint[], decrsize[]; 114 extern int tlbimiss[], tlbimsize[]; 115 extern int tlbdlmiss[], tlbdlmsize[]; 116 extern int tlbdsmiss[], tlbdsmsize[]; 117 #if defined(DDB) || defined(KGDB) 118 extern int ddblow[], ddbsize[]; 119 #endif 120 #ifdef IPKDB 121 extern int ipkdblow[], ipkdbsize[]; 122 #endif 123 #ifdef ALTIVEC 124 register_t msr; 125 #endif 126 uintptr_t exc; 127 register_t scratch; 128 unsigned int cpuvers; 129 size_t size; 130 struct cpu_info * const ci = &cpu_info[0]; 131 132 mtspr(SPR_SPRG0, ci); 133 cpuvers = mfpvr() >> 16; 134 135 136 /* 137 * Initialize proc0 and current pcb and pmap pointers. 138 */ 139 KASSERT(ci != NULL); 140 KASSERT(curcpu() == ci); 141 lwp0.l_cpu = ci; 142 lwp0.l_addr = proc0paddr; 143 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 144 KASSERT(lwp0.l_cpu != NULL); 145 146 curpcb = &proc0paddr->u_pcb; 147 memset(curpcb, 0, sizeof(*curpcb)); 148 #ifdef ALTIVEC 149 /* 150 * Initialize the vectors with NaNs 151 */ 152 for (scratch = 0; scratch < 32; scratch++) { 153 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 154 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 155 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 156 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 157 } 158 curpcb->pcb_vr.vscr = 0; 159 curpcb->pcb_vr.vrsave = 0; 160 #endif 161 curpm = curpcb->pcb_pm = pmap_kernel(); 162 163 /* 164 * Cause a PGM trap if we branch to 0. 165 */ 166 memset(0, 0, 0x100); 167 168 /* 169 * Set up trap vectors. Don't assume vectors are on 0x100. 170 */ 171 for (exc = 0; exc <= EXC_LAST; exc += 0x100) { 172 switch (exc) { 173 default: 174 size = (size_t)trapsize; 175 memcpy((void *)exc, trapcode, size); 176 break; 177 #if 0 178 case EXC_EXI: 179 /* 180 * This one is (potentially) installed during autoconf 181 */ 182 break; 183 #endif 184 case EXC_SC: 185 size = (size_t)scsize; 186 memcpy((void *)EXC_SC, sctrap, size); 187 break; 188 case EXC_ALI: 189 size = (size_t)alisize; 190 memcpy((void *)EXC_ALI, alitrap, size); 191 break; 192 case EXC_DSI: 193 if (cpuvers == MPC601) { 194 size = (size_t)dsi601size; 195 memcpy((void *)EXC_DSI, dsi601trap, size); 196 } else { 197 size = (size_t)dsisize; 198 memcpy((void *)EXC_DSI, dsitrap, size); 199 } 200 break; 201 case EXC_DECR: 202 size = (size_t)decrsize; 203 memcpy((void *)EXC_DECR, decrint, size); 204 break; 205 case EXC_IMISS: 206 size = (size_t)tlbimsize; 207 memcpy((void *)EXC_IMISS, tlbimiss, size); 208 break; 209 case EXC_DLMISS: 210 size = (size_t)tlbdlmsize; 211 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 212 break; 213 case EXC_DSMISS: 214 size = (size_t)tlbdsmsize; 215 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 216 break; 217 case EXC_PERF: 218 size = (size_t)trapsize; 219 memcpy((void *)EXC_PERF, trapcode, size); 220 memcpy((void *)EXC_VEC, trapcode, size); 221 break; 222 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 223 case EXC_RUNMODETRC: 224 if (cpuvers != MPC601) { 225 size = (size_t)trapsize; 226 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 227 break; 228 } 229 /* FALLTHROUGH */ 230 case EXC_PGM: 231 case EXC_TRC: 232 case EXC_BPT: 233 #if defined(DDB) || defined(KGDB) 234 size = (size_t)ddbsize; 235 memcpy((void *)exc, ddblow, size); 236 #if defined(IPKDB) 237 #error "cannot enable IPKDB with DDB or KGDB" 238 #endif 239 #else 240 size = (size_t)ipkdbsize; 241 memcpy((void *)exc, ipkdblow, size); 242 #endif 243 break; 244 #endif /* DDB || IPKDB || KGDB */ 245 } 246 #if 0 247 exc += roundup(size, 32); 248 #endif 249 } 250 251 /* 252 * Get the cache sizes because install_extint calls __syncicache. 253 */ 254 cpu_probe_cache(); 255 256 #define MxSPR_MASK 0x7c1fffff 257 #define MFSPR_MQ 0x7c0002a6 258 #define MTSPR_MQ 0x7c0003a6 259 #define MTSPR_IBAT0L 0x7c1183a6 260 #define MTSPR_IBAT1L 0x7c1383a6 261 #define NOP 0x60000000 262 #define B 0x48000000 263 #define TLBSYNC 0x7c00046c 264 #define SYNC 0x7c0004ac 265 266 #ifdef ALTIVEC 267 #define MFSPR_VRSAVE 0x7c0042a6 268 #define MTSPR_VRSAVE 0x7c0043a6 269 270 /* 271 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 272 * not on a AltiVec capable processor. 273 */ 274 __asm volatile ( 275 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 276 "mfmsr %1; mtmsr %0; isync" 277 : "=r"(msr), "=r"(scratch) 278 : "J"(PSL_VEC)); 279 280 /* 281 * If we aren't on an AltiVec capable processor, we need to zap any of 282 * the sequences we save/restore the VRSAVE SPR into NOPs. 283 */ 284 if (scratch & PSL_VEC) { 285 cpu_altivec = 1; 286 } else { 287 int *ip = trapstart; 288 289 for (; ip < trapend; ip++) { 290 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 291 ip[0] = NOP; /* mfspr */ 292 ip[1] = NOP; /* stw */ 293 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 294 ip[-1] = NOP; /* lwz */ 295 ip[0] = NOP; /* mtspr */ 296 } 297 } 298 } 299 #endif 300 301 /* 302 * If we aren't on a MPC601 processor, we need to zap any of the 303 * sequences we save/restore the MQ SPR into NOPs, and skip over the 304 * sequences where we zap/restore BAT registers on kernel exit/entry. 305 */ 306 if (cpuvers != MPC601) { 307 int *ip = trapstart; 308 309 for (; ip < trapend; ip++) { 310 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 311 ip[0] = NOP; /* mfspr */ 312 ip[1] = NOP; /* stw */ 313 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 314 ip[-1] = NOP; /* lwz */ 315 ip[0] = NOP; /* mtspr */ 316 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 317 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 318 ip[-1] = B | 0x14; /* li */ 319 else 320 ip[-4] = B | 0x24; /* lis */ 321 } 322 } 323 } 324 325 /* 326 * Sync the changed instructions. 327 */ 328 __syncicache((void *) trapstart, 329 (uintptr_t) trapend - (uintptr_t) trapstart); 330 331 /* 332 * If we are on a MPC601 processor, we need to zap any tlbsync 333 * instructions into sync. This differs from the above in 334 * examing all kernel text, as opposed to just the exception handling. 335 * We sync the icache on every instruction found since there are 336 * only very few of them. 337 */ 338 if (cpuvers == MPC601) { 339 extern int kernel_text[], etext[]; 340 int *ip; 341 342 for (ip = kernel_text; ip < etext; ip++) 343 if (*ip == TLBSYNC) { 344 *ip = SYNC; 345 __syncicache(ip, sizeof(*ip)); 346 } 347 } 348 349 /* 350 * Configure a PSL user mask matching this processor. 351 */ 352 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 353 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 354 if (cpuvers == MPC601) { 355 cpu_psluserset &= PSL_601_MASK; 356 cpu_pslusermod &= PSL_601_MASK; 357 } 358 #ifdef ALTIVEC 359 if (cpu_altivec) 360 cpu_pslusermod |= PSL_VEC; 361 #endif 362 363 /* 364 * external interrupt handler install 365 */ 366 if (handler) 367 oea_install_extint(handler); 368 369 __syncicache(0, EXC_LAST + 0x100); 370 371 /* 372 * Now enable translation (and machine checks/recoverable interrupts). 373 */ 374 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 375 : "=r"(scratch) 376 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 377 378 KASSERT(curcpu() == ci); 379 } 380 381 void 382 mpc601_ioseg_add(paddr_t pa, register_t len) 383 { 384 const u_int i = pa >> ADDR_SR_SHFT; 385 386 if (len != BAT_BL_256M) 387 panic("mpc601_ioseg_add: len != 256M"); 388 389 /* 390 * Translate into an I/O segment, load it, and stash away for use 391 * in pmap_bootstrap(). 392 */ 393 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 394 __asm volatile ("mtsrin %0,%1" 395 :: "r"(iosrtable[i]), 396 "r"(pa)); 397 } 398 399 void 400 oea_iobat_add(paddr_t pa, register_t len) 401 { 402 static int n = 1; 403 const u_int i = pa >> 28; 404 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 405 battable[i].batu = BATU(pa, len, BAT_Vs); 406 407 /* 408 * Let's start loading the BAT registers. 409 */ 410 switch (n) { 411 case 1: 412 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 413 :: "r"(battable[i].batl), 414 "r"(battable[i].batu)); 415 n = 2; 416 break; 417 case 2: 418 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 419 :: "r"(battable[i].batl), 420 "r"(battable[i].batu)); 421 n = 3; 422 break; 423 case 3: 424 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 425 :: "r"(battable[i].batl), 426 "r"(battable[i].batu)); 427 n = 4; 428 break; 429 default: 430 break; 431 } 432 } 433 434 void 435 oea_iobat_remove(paddr_t pa) 436 { 437 register_t batu; 438 int i, n; 439 440 n = pa >> ADDR_SR_SHFT; 441 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 442 !BAT_VALID_P(battable[n].batu, PSL_PR)) 443 return; 444 battable[n].batl = 0; 445 battable[n].batu = 0; 446 #define BAT_RESET(n) \ 447 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 448 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 449 450 for (i=1 ; i<4 ; i++) { 451 switch (i) { 452 case 1: 453 BATU_GET(1, batu); 454 if (BAT_VA_MATCH_P(batu, pa) && 455 BAT_VALID_P(batu, PSL_PR)) 456 BAT_RESET(1); 457 break; 458 case 2: 459 BATU_GET(2, batu); 460 if (BAT_VA_MATCH_P(batu, pa) && 461 BAT_VALID_P(batu, PSL_PR)) 462 BAT_RESET(2); 463 break; 464 case 3: 465 BATU_GET(3, batu); 466 if (BAT_VA_MATCH_P(batu, pa) && 467 BAT_VALID_P(batu, PSL_PR)) 468 BAT_RESET(3); 469 break; 470 default: 471 break; 472 } 473 } 474 } 475 476 void 477 oea_batinit(paddr_t pa, ...) 478 { 479 struct mem_region *allmem, *availmem, *mp; 480 int i; 481 unsigned int cpuvers; 482 register_t msr = mfmsr(); 483 va_list ap; 484 485 cpuvers = mfpvr() >> 16; 486 487 /* 488 * Initialize BAT registers to unmapped to not generate 489 * overlapping mappings below. 490 * 491 * The 601's implementation differs in the Valid bit being situated 492 * in the lower BAT register, and in being a unified BAT only whose 493 * four entries are accessed through the IBAT[0-3] SPRs. 494 * 495 * Also, while the 601 does distinguish between supervisor/user 496 * protection keys, it does _not_ distinguish between validity in 497 * supervisor/user mode. 498 */ 499 if ((msr & (PSL_IR|PSL_DR)) == 0) { 500 if (cpuvers == MPC601) { 501 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 502 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 503 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 504 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 505 } else { 506 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 507 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 508 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 509 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 510 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 511 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 512 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 513 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 514 } 515 } 516 517 /* 518 * Set up BAT to map physical memory 519 */ 520 if (cpuvers == MPC601) { 521 /* 522 * Set up battable to map the lowest 256 MB area. 523 * Map the lowest 32 MB area via BAT[0-3]; 524 * BAT[01] are fixed, BAT[23] are floating. 525 */ 526 for (i = 0; i < 32; i++) { 527 battable[i].batl = BATL601(i << 23, 528 BAT601_BSM_8M, BAT601_V); 529 battable[i].batu = BATU601(i << 23, 530 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 531 } 532 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 533 :: "r"(battable[0x00000000 >> 23].batl), 534 "r"(battable[0x00000000 >> 23].batu)); 535 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 536 :: "r"(battable[0x00800000 >> 23].batl), 537 "r"(battable[0x00800000 >> 23].batu)); 538 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 539 :: "r"(battable[0x01000000 >> 23].batl), 540 "r"(battable[0x01000000 >> 23].batu)); 541 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 542 :: "r"(battable[0x01800000 >> 23].batl), 543 "r"(battable[0x01800000 >> 23].batu)); 544 } else { 545 /* 546 * Set up BAT0 to only map the lowest 256 MB area 547 */ 548 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 549 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 550 551 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 552 "mtdbatl 0,%0; mtdbatu 0,%1;" 553 :: "r"(battable[0].batl), "r"(battable[0].batu)); 554 } 555 556 /* 557 * Now setup other fixed bat registers 558 * 559 * Note that we still run in real mode, and the BAT 560 * registers were cleared above. 561 */ 562 563 va_start(ap, pa); 564 565 /* 566 * Add any I/O BATs specificed; 567 * use I/O segments on the BAT-starved 601. 568 */ 569 if (cpuvers == MPC601) { 570 while (pa != 0) { 571 register_t len = va_arg(ap, register_t); 572 mpc601_ioseg_add(pa, len); 573 pa = va_arg(ap, paddr_t); 574 } 575 } else { 576 while (pa != 0) { 577 register_t len = va_arg(ap, register_t); 578 oea_iobat_add(pa, len); 579 pa = va_arg(ap, paddr_t); 580 } 581 } 582 583 va_end(ap); 584 585 /* 586 * Set up battable to map all RAM regions. 587 * This is here because mem_regions() call needs bat0 set up. 588 */ 589 mem_regions(&allmem, &availmem); 590 if (cpuvers == MPC601) { 591 for (mp = allmem; mp->size; mp++) { 592 paddr_t paddr = mp->start & 0xff800000; 593 paddr_t end = mp->start + mp->size; 594 595 do { 596 u_int ix = paddr >> 23; 597 598 battable[ix].batl = 599 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 600 battable[ix].batu = 601 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 602 paddr += (1 << 23); 603 } while (paddr < end); 604 } 605 } else { 606 for (mp = allmem; mp->size; mp++) { 607 paddr_t paddr = mp->start & 0xf0000000; 608 paddr_t end = mp->start + mp->size; 609 610 do { 611 u_int ix = paddr >> 28; 612 613 battable[ix].batl = 614 BATL(paddr, BAT_M, BAT_PP_RW); 615 battable[ix].batu = 616 BATU(paddr, BAT_BL_256M, BAT_Vs); 617 paddr += SEGMENT_LENGTH; 618 } while (paddr < end); 619 } 620 } 621 } 622 623 void 624 oea_install_extint(void (*handler)(void)) 625 { 626 extern int extint[], extsize[]; 627 extern int extint_call[]; 628 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 629 int omsr, msr; 630 631 #ifdef DIAGNOSTIC 632 if (offset > 0x1ffffff) 633 panic("install_extint: %p too far away (%#lx)", handler, 634 (unsigned long) offset); 635 #endif 636 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 637 : "=r" (omsr), "=r" (msr) 638 : "K" ((u_short)~PSL_EE)); 639 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 640 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 641 __syncicache((void *)extint_call, sizeof extint_call[0]); 642 __syncicache((void *)EXC_EXI, (int)extsize); 643 __asm volatile ("mtmsr %0" :: "r"(omsr)); 644 } 645 646 /* 647 * Machine dependent startup code. 648 */ 649 void 650 oea_startup(const char *model) 651 { 652 uintptr_t sz; 653 caddr_t v; 654 vaddr_t minaddr, maxaddr; 655 char pbuf[9]; 656 u_int i; 657 658 KASSERT(curcpu() != NULL); 659 KASSERT(lwp0.l_cpu != NULL); 660 KASSERT(curcpu()->ci_intstk != 0); 661 KASSERT(curcpu()->ci_intrdepth == -1); 662 663 /* 664 * If the msgbuf is not in segment 0, allocate KVA for it and access 665 * it via mapped pages. [This prevents unneeded BAT switches.] 666 */ 667 sz = round_page(MSGBUFSIZE); 668 v = (caddr_t) msgbuf_paddr; 669 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 670 minaddr = 0; 671 if (uvm_map(kernel_map, &minaddr, sz, 672 NULL, UVM_UNKNOWN_OFFSET, 0, 673 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 674 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 675 panic("startup: cannot allocate VM for msgbuf"); 676 v = (caddr_t)minaddr; 677 for (i = 0; i < sz; i += PAGE_SIZE) { 678 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 679 VM_PROT_READ|VM_PROT_WRITE); 680 } 681 pmap_update(pmap_kernel()); 682 } 683 initmsgbuf(v, sz); 684 685 printf("%s%s", copyright, version); 686 if (model != NULL) 687 printf("Model: %s\n", model); 688 cpu_identify(NULL, 0); 689 690 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 691 printf("total memory = %s\n", pbuf); 692 693 /* 694 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 695 * the bufpages are allocated in case they overlap since it's not 696 * fatal if we can't allocate these. 697 */ 698 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 699 int error; 700 minaddr = 0xDEAC0000; 701 error = uvm_map(kernel_map, &minaddr, 0x30000, 702 NULL, UVM_UNKNOWN_OFFSET, 0, 703 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 704 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 705 if (error != 0 || minaddr != 0xDEAC0000) 706 printf("oea_startup: failed to allocate DEAD " 707 "ZONE: error=%d\n", error); 708 } 709 710 minaddr = 0; 711 /* 712 * Allocate a submap for exec arguments. This map effectively 713 * limits the number of processes exec'ing at any time. These 714 * submaps will be allocated after the dead zone. 715 */ 716 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 717 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 718 719 /* 720 * Allocate a submap for physio 721 */ 722 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 723 VM_PHYS_SIZE, 0, FALSE, NULL); 724 725 #ifndef PMAP_MAP_POOLPAGE 726 /* 727 * No need to allocate an mbuf cluster submap. Mbuf clusters 728 * are allocated via the pool allocator, and we use direct-mapped 729 * pool pages. 730 */ 731 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 732 mclbytes*nmbclusters, VM_MAP_INTRSAFE, FALSE, NULL); 733 #endif 734 735 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 736 printf("avail memory = %s\n", pbuf); 737 } 738 739 /* 740 * Crash dump handling. 741 */ 742 743 void 744 oea_dumpsys(void) 745 { 746 printf("dumpsys: TBD\n"); 747 } 748 749 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 750 /* 751 * Soft networking interrupts. 752 */ 753 void 754 softnet(int pendisr) 755 { 756 #define DONETISR(bit, fn) do { \ 757 if (pendisr & (1 << bit)) \ 758 (*fn)(); \ 759 } while (0) 760 761 #include <net/netisr_dispatch.h> 762 763 #undef DONETISR 764 } 765 #endif 766 767 /* 768 * Convert kernel VA to physical address 769 */ 770 paddr_t 771 kvtop(caddr_t addr) 772 { 773 vaddr_t va; 774 paddr_t pa; 775 uintptr_t off; 776 extern char end[]; 777 778 if (addr < end) 779 return (paddr_t)addr; 780 781 va = trunc_page((vaddr_t)addr); 782 off = (uintptr_t)addr - va; 783 784 if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) { 785 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 786 return (paddr_t)addr; 787 } 788 789 return(pa + off); 790 } 791 792 /* 793 * Allocate vm space and mapin the I/O address 794 */ 795 void * 796 mapiodev(paddr_t pa, psize_t len) 797 { 798 paddr_t faddr; 799 vaddr_t taddr, va; 800 int off; 801 802 faddr = trunc_page(pa); 803 off = pa - faddr; 804 len = round_page(off + len); 805 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 806 807 if (va == 0) 808 return NULL; 809 810 for (; len > 0; len -= PAGE_SIZE) { 811 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 812 faddr += PAGE_SIZE; 813 taddr += PAGE_SIZE; 814 } 815 pmap_update(pmap_kernel()); 816 return (void *)(va + off); 817 } 818
Indexes created Tue Sep 30 11:09:46 GMT 2025