oea_machdep.c revision 1.25
1 /* $NetBSD: oea_machdep.c,v 1.25 2006/06/04 07:32:20 mrg Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.25 2006/06/04 07:32:20 mrg Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/sa.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/trap.h> 82 #include <powerpc/stdarg.h> 83 #include <powerpc/spr.h> 84 #include <powerpc/pte.h> 85 #include <powerpc/altivec.h> 86 #include <machine/powerpc.h> 87 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 91 struct vm_map *exec_map = NULL; 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 struct bat battable[512]; 101 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 102 paddr_t msgbuf_paddr; 103 104 void 105 oea_init(void (*handler)(void)) 106 { 107 extern int trapstart[], trapend[]; 108 extern int trapcode[], trapsize[]; 109 extern int sctrap[], scsize[]; 110 extern int alitrap[], alisize[]; 111 extern int dsitrap[], dsisize[]; 112 extern int dsi601trap[], dsi601size[]; 113 extern int decrint[], decrsize[]; 114 extern int tlbimiss[], tlbimsize[]; 115 extern int tlbdlmiss[], tlbdlmsize[]; 116 extern int tlbdsmiss[], tlbdsmsize[]; 117 #if defined(DDB) || defined(KGDB) 118 extern int ddblow[], ddbsize[]; 119 #endif 120 #ifdef IPKDB 121 extern int ipkdblow[], ipkdbsize[]; 122 #endif 123 #ifdef ALTIVEC 124 register_t msr; 125 #endif 126 uintptr_t exc; 127 register_t scratch; 128 unsigned int cpuvers; 129 size_t size; 130 struct cpu_info * const ci = &cpu_info[0]; 131 132 mtspr(SPR_SPRG0, ci); 133 cpuvers = mfpvr() >> 16; 134 135 136 /* 137 * Initialize proc0 and current pcb and pmap pointers. 138 */ 139 KASSERT(ci != NULL); 140 KASSERT(curcpu() == ci); 141 lwp0.l_cpu = ci; 142 lwp0.l_addr = proc0paddr; 143 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 144 KASSERT(lwp0.l_cpu != NULL); 145 146 curpcb = &proc0paddr->u_pcb; 147 memset(curpcb, 0, sizeof(*curpcb)); 148 #ifdef ALTIVEC 149 /* 150 * Initialize the vectors with NaNs 151 */ 152 for (scratch = 0; scratch < 32; scratch++) { 153 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 154 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 155 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 156 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 157 } 158 curpcb->pcb_vr.vscr = 0; 159 curpcb->pcb_vr.vrsave = 0; 160 #endif 161 curpm = curpcb->pcb_pm = pmap_kernel(); 162 163 /* 164 * Cause a PGM trap if we branch to 0. 165 * 166 * XXX GCC4.1 complains about memset on address zero, so 167 * don't use the builtin. 168 */ 169 #undef memset 170 memset(0, 0, 0x100); 171 172 /* 173 * Set up trap vectors. Don't assume vectors are on 0x100. 174 */ 175 for (exc = 0; exc <= EXC_LAST; exc += 0x100) { 176 switch (exc) { 177 default: 178 size = (size_t)trapsize; 179 memcpy((void *)exc, trapcode, size); 180 break; 181 #if 0 182 case EXC_EXI: 183 /* 184 * This one is (potentially) installed during autoconf 185 */ 186 break; 187 #endif 188 case EXC_SC: 189 size = (size_t)scsize; 190 memcpy((void *)EXC_SC, sctrap, size); 191 break; 192 case EXC_ALI: 193 size = (size_t)alisize; 194 memcpy((void *)EXC_ALI, alitrap, size); 195 break; 196 case EXC_DSI: 197 if (cpuvers == MPC601) { 198 size = (size_t)dsi601size; 199 memcpy((void *)EXC_DSI, dsi601trap, size); 200 } else { 201 size = (size_t)dsisize; 202 memcpy((void *)EXC_DSI, dsitrap, size); 203 } 204 break; 205 case EXC_DECR: 206 size = (size_t)decrsize; 207 memcpy((void *)EXC_DECR, decrint, size); 208 break; 209 case EXC_IMISS: 210 size = (size_t)tlbimsize; 211 memcpy((void *)EXC_IMISS, tlbimiss, size); 212 break; 213 case EXC_DLMISS: 214 size = (size_t)tlbdlmsize; 215 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 216 break; 217 case EXC_DSMISS: 218 size = (size_t)tlbdsmsize; 219 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 220 break; 221 case EXC_PERF: 222 size = (size_t)trapsize; 223 memcpy((void *)EXC_PERF, trapcode, size); 224 memcpy((void *)EXC_VEC, trapcode, size); 225 break; 226 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 227 case EXC_RUNMODETRC: 228 if (cpuvers != MPC601) { 229 size = (size_t)trapsize; 230 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 231 break; 232 } 233 /* FALLTHROUGH */ 234 case EXC_PGM: 235 case EXC_TRC: 236 case EXC_BPT: 237 #if defined(DDB) || defined(KGDB) 238 size = (size_t)ddbsize; 239 memcpy((void *)exc, ddblow, size); 240 #if defined(IPKDB) 241 #error "cannot enable IPKDB with DDB or KGDB" 242 #endif 243 #else 244 size = (size_t)ipkdbsize; 245 memcpy((void *)exc, ipkdblow, size); 246 #endif 247 break; 248 #endif /* DDB || IPKDB || KGDB */ 249 } 250 #if 0 251 exc += roundup(size, 32); 252 #endif 253 } 254 255 /* 256 * Get the cache sizes because install_extint calls __syncicache. 257 */ 258 cpu_probe_cache(); 259 260 #define MxSPR_MASK 0x7c1fffff 261 #define MFSPR_MQ 0x7c0002a6 262 #define MTSPR_MQ 0x7c0003a6 263 #define MTSPR_IBAT0L 0x7c1183a6 264 #define MTSPR_IBAT1L 0x7c1383a6 265 #define NOP 0x60000000 266 #define B 0x48000000 267 #define TLBSYNC 0x7c00046c 268 #define SYNC 0x7c0004ac 269 270 #ifdef ALTIVEC 271 #define MFSPR_VRSAVE 0x7c0042a6 272 #define MTSPR_VRSAVE 0x7c0043a6 273 274 /* 275 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 276 * not on a AltiVec capable processor. 277 */ 278 __asm volatile ( 279 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 280 "mfmsr %1; mtmsr %0; isync" 281 : "=r"(msr), "=r"(scratch) 282 : "J"(PSL_VEC)); 283 284 /* 285 * If we aren't on an AltiVec capable processor, we need to zap any of 286 * the sequences we save/restore the VRSAVE SPR into NOPs. 287 */ 288 if (scratch & PSL_VEC) { 289 cpu_altivec = 1; 290 } else { 291 int *ip = trapstart; 292 293 for (; ip < trapend; ip++) { 294 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 295 ip[0] = NOP; /* mfspr */ 296 ip[1] = NOP; /* stw */ 297 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 298 ip[-1] = NOP; /* lwz */ 299 ip[0] = NOP; /* mtspr */ 300 } 301 } 302 } 303 #endif 304 305 /* 306 * If we aren't on a MPC601 processor, we need to zap any of the 307 * sequences we save/restore the MQ SPR into NOPs, and skip over the 308 * sequences where we zap/restore BAT registers on kernel exit/entry. 309 */ 310 if (cpuvers != MPC601) { 311 int *ip = trapstart; 312 313 for (; ip < trapend; ip++) { 314 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 315 ip[0] = NOP; /* mfspr */ 316 ip[1] = NOP; /* stw */ 317 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 318 ip[-1] = NOP; /* lwz */ 319 ip[0] = NOP; /* mtspr */ 320 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 321 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 322 ip[-1] = B | 0x14; /* li */ 323 else 324 ip[-4] = B | 0x24; /* lis */ 325 } 326 } 327 } 328 329 /* 330 * Sync the changed instructions. 331 */ 332 __syncicache((void *) trapstart, 333 (uintptr_t) trapend - (uintptr_t) trapstart); 334 335 /* 336 * If we are on a MPC601 processor, we need to zap any tlbsync 337 * instructions into sync. This differs from the above in 338 * examing all kernel text, as opposed to just the exception handling. 339 * We sync the icache on every instruction found since there are 340 * only very few of them. 341 */ 342 if (cpuvers == MPC601) { 343 extern int kernel_text[], etext[]; 344 int *ip; 345 346 for (ip = kernel_text; ip < etext; ip++) 347 if (*ip == TLBSYNC) { 348 *ip = SYNC; 349 __syncicache(ip, sizeof(*ip)); 350 } 351 } 352 353 /* 354 * Configure a PSL user mask matching this processor. 355 */ 356 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 357 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 358 if (cpuvers == MPC601) { 359 cpu_psluserset &= PSL_601_MASK; 360 cpu_pslusermod &= PSL_601_MASK; 361 } 362 #ifdef ALTIVEC 363 if (cpu_altivec) 364 cpu_pslusermod |= PSL_VEC; 365 #endif 366 367 /* 368 * external interrupt handler install 369 */ 370 if (handler) 371 oea_install_extint(handler); 372 373 __syncicache(0, EXC_LAST + 0x100); 374 375 /* 376 * Now enable translation (and machine checks/recoverable interrupts). 377 */ 378 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 379 : "=r"(scratch) 380 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 381 382 KASSERT(curcpu() == ci); 383 } 384 385 void 386 mpc601_ioseg_add(paddr_t pa, register_t len) 387 { 388 const u_int i = pa >> ADDR_SR_SHFT; 389 390 if (len != BAT_BL_256M) 391 panic("mpc601_ioseg_add: len != 256M"); 392 393 /* 394 * Translate into an I/O segment, load it, and stash away for use 395 * in pmap_bootstrap(). 396 */ 397 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 398 __asm volatile ("mtsrin %0,%1" 399 :: "r"(iosrtable[i]), 400 "r"(pa)); 401 } 402 403 void 404 oea_iobat_add(paddr_t pa, register_t len) 405 { 406 static int n = 1; 407 const u_int i = pa >> 28; 408 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 409 battable[i].batu = BATU(pa, len, BAT_Vs); 410 411 /* 412 * Let's start loading the BAT registers. 413 */ 414 switch (n) { 415 case 1: 416 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 417 :: "r"(battable[i].batl), 418 "r"(battable[i].batu)); 419 n = 2; 420 break; 421 case 2: 422 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 423 :: "r"(battable[i].batl), 424 "r"(battable[i].batu)); 425 n = 3; 426 break; 427 case 3: 428 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 429 :: "r"(battable[i].batl), 430 "r"(battable[i].batu)); 431 n = 4; 432 break; 433 default: 434 break; 435 } 436 } 437 438 void 439 oea_iobat_remove(paddr_t pa) 440 { 441 register_t batu; 442 int i, n; 443 444 n = pa >> ADDR_SR_SHFT; 445 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 446 !BAT_VALID_P(battable[n].batu, PSL_PR)) 447 return; 448 battable[n].batl = 0; 449 battable[n].batu = 0; 450 #define BAT_RESET(n) \ 451 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 452 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 453 454 for (i=1 ; i<4 ; i++) { 455 switch (i) { 456 case 1: 457 BATU_GET(1, batu); 458 if (BAT_VA_MATCH_P(batu, pa) && 459 BAT_VALID_P(batu, PSL_PR)) 460 BAT_RESET(1); 461 break; 462 case 2: 463 BATU_GET(2, batu); 464 if (BAT_VA_MATCH_P(batu, pa) && 465 BAT_VALID_P(batu, PSL_PR)) 466 BAT_RESET(2); 467 break; 468 case 3: 469 BATU_GET(3, batu); 470 if (BAT_VA_MATCH_P(batu, pa) && 471 BAT_VALID_P(batu, PSL_PR)) 472 BAT_RESET(3); 473 break; 474 default: 475 break; 476 } 477 } 478 } 479 480 void 481 oea_batinit(paddr_t pa, ...) 482 { 483 struct mem_region *allmem, *availmem, *mp; 484 int i; 485 unsigned int cpuvers; 486 register_t msr = mfmsr(); 487 va_list ap; 488 489 cpuvers = mfpvr() >> 16; 490 491 /* 492 * Initialize BAT registers to unmapped to not generate 493 * overlapping mappings below. 494 * 495 * The 601's implementation differs in the Valid bit being situated 496 * in the lower BAT register, and in being a unified BAT only whose 497 * four entries are accessed through the IBAT[0-3] SPRs. 498 * 499 * Also, while the 601 does distinguish between supervisor/user 500 * protection keys, it does _not_ distinguish between validity in 501 * supervisor/user mode. 502 */ 503 if ((msr & (PSL_IR|PSL_DR)) == 0) { 504 if (cpuvers == MPC601) { 505 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 506 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 507 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 508 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 509 } else { 510 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 511 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 512 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 513 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 514 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 515 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 516 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 517 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 518 } 519 } 520 521 /* 522 * Set up BAT to map physical memory 523 */ 524 if (cpuvers == MPC601) { 525 /* 526 * Set up battable to map the lowest 256 MB area. 527 * Map the lowest 32 MB area via BAT[0-3]; 528 * BAT[01] are fixed, BAT[23] are floating. 529 */ 530 for (i = 0; i < 32; i++) { 531 battable[i].batl = BATL601(i << 23, 532 BAT601_BSM_8M, BAT601_V); 533 battable[i].batu = BATU601(i << 23, 534 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 535 } 536 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 537 :: "r"(battable[0x00000000 >> 23].batl), 538 "r"(battable[0x00000000 >> 23].batu)); 539 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 540 :: "r"(battable[0x00800000 >> 23].batl), 541 "r"(battable[0x00800000 >> 23].batu)); 542 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 543 :: "r"(battable[0x01000000 >> 23].batl), 544 "r"(battable[0x01000000 >> 23].batu)); 545 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 546 :: "r"(battable[0x01800000 >> 23].batl), 547 "r"(battable[0x01800000 >> 23].batu)); 548 } else { 549 /* 550 * Set up BAT0 to only map the lowest 256 MB area 551 */ 552 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 553 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 554 555 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 556 "mtdbatl 0,%0; mtdbatu 0,%1;" 557 :: "r"(battable[0].batl), "r"(battable[0].batu)); 558 } 559 560 /* 561 * Now setup other fixed bat registers 562 * 563 * Note that we still run in real mode, and the BAT 564 * registers were cleared above. 565 */ 566 567 va_start(ap, pa); 568 569 /* 570 * Add any I/O BATs specificed; 571 * use I/O segments on the BAT-starved 601. 572 */ 573 if (cpuvers == MPC601) { 574 while (pa != 0) { 575 register_t len = va_arg(ap, register_t); 576 mpc601_ioseg_add(pa, len); 577 pa = va_arg(ap, paddr_t); 578 } 579 } else { 580 while (pa != 0) { 581 register_t len = va_arg(ap, register_t); 582 oea_iobat_add(pa, len); 583 pa = va_arg(ap, paddr_t); 584 } 585 } 586 587 va_end(ap); 588 589 /* 590 * Set up battable to map all RAM regions. 591 * This is here because mem_regions() call needs bat0 set up. 592 */ 593 mem_regions(&allmem, &availmem); 594 if (cpuvers == MPC601) { 595 for (mp = allmem; mp->size; mp++) { 596 paddr_t paddr = mp->start & 0xff800000; 597 paddr_t end = mp->start + mp->size; 598 599 do { 600 u_int ix = paddr >> 23; 601 602 battable[ix].batl = 603 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 604 battable[ix].batu = 605 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 606 paddr += (1 << 23); 607 } while (paddr < end); 608 } 609 } else { 610 for (mp = allmem; mp->size; mp++) { 611 paddr_t paddr = mp->start & 0xf0000000; 612 paddr_t end = mp->start + mp->size; 613 614 do { 615 u_int ix = paddr >> 28; 616 617 battable[ix].batl = 618 BATL(paddr, BAT_M, BAT_PP_RW); 619 battable[ix].batu = 620 BATU(paddr, BAT_BL_256M, BAT_Vs); 621 paddr += SEGMENT_LENGTH; 622 } while (paddr < end); 623 } 624 } 625 } 626 627 void 628 oea_install_extint(void (*handler)(void)) 629 { 630 extern int extint[], extsize[]; 631 extern int extint_call[]; 632 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 633 int omsr, msr; 634 635 #ifdef DIAGNOSTIC 636 if (offset > 0x1ffffff) 637 panic("install_extint: %p too far away (%#lx)", handler, 638 (unsigned long) offset); 639 #endif 640 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 641 : "=r" (omsr), "=r" (msr) 642 : "K" ((u_short)~PSL_EE)); 643 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 644 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 645 __syncicache((void *)extint_call, sizeof extint_call[0]); 646 __syncicache((void *)EXC_EXI, (int)extsize); 647 __asm volatile ("mtmsr %0" :: "r"(omsr)); 648 } 649 650 /* 651 * Machine dependent startup code. 652 */ 653 void 654 oea_startup(const char *model) 655 { 656 uintptr_t sz; 657 caddr_t v; 658 vaddr_t minaddr, maxaddr; 659 char pbuf[9]; 660 u_int i; 661 662 KASSERT(curcpu() != NULL); 663 KASSERT(lwp0.l_cpu != NULL); 664 KASSERT(curcpu()->ci_intstk != 0); 665 KASSERT(curcpu()->ci_intrdepth == -1); 666 667 /* 668 * If the msgbuf is not in segment 0, allocate KVA for it and access 669 * it via mapped pages. [This prevents unneeded BAT switches.] 670 */ 671 sz = round_page(MSGBUFSIZE); 672 v = (caddr_t) msgbuf_paddr; 673 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 674 minaddr = 0; 675 if (uvm_map(kernel_map, &minaddr, sz, 676 NULL, UVM_UNKNOWN_OFFSET, 0, 677 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 678 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 679 panic("startup: cannot allocate VM for msgbuf"); 680 v = (caddr_t)minaddr; 681 for (i = 0; i < sz; i += PAGE_SIZE) { 682 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 683 VM_PROT_READ|VM_PROT_WRITE); 684 } 685 pmap_update(pmap_kernel()); 686 } 687 initmsgbuf(v, sz); 688 689 printf("%s%s", copyright, version); 690 if (model != NULL) 691 printf("Model: %s\n", model); 692 cpu_identify(NULL, 0); 693 694 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 695 printf("total memory = %s\n", pbuf); 696 697 /* 698 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 699 * the bufpages are allocated in case they overlap since it's not 700 * fatal if we can't allocate these. 701 */ 702 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 703 int error; 704 minaddr = 0xDEAC0000; 705 error = uvm_map(kernel_map, &minaddr, 0x30000, 706 NULL, UVM_UNKNOWN_OFFSET, 0, 707 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 708 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 709 if (error != 0 || minaddr != 0xDEAC0000) 710 printf("oea_startup: failed to allocate DEAD " 711 "ZONE: error=%d\n", error); 712 } 713 714 minaddr = 0; 715 /* 716 * Allocate a submap for exec arguments. This map effectively 717 * limits the number of processes exec'ing at any time. These 718 * submaps will be allocated after the dead zone. 719 */ 720 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 721 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 722 723 /* 724 * Allocate a submap for physio 725 */ 726 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 727 VM_PHYS_SIZE, 0, FALSE, NULL); 728 729 #ifndef PMAP_MAP_POOLPAGE 730 /* 731 * No need to allocate an mbuf cluster submap. Mbuf clusters 732 * are allocated via the pool allocator, and we use direct-mapped 733 * pool pages. 734 */ 735 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 736 mclbytes*nmbclusters, VM_MAP_INTRSAFE, FALSE, NULL); 737 #endif 738 739 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 740 printf("avail memory = %s\n", pbuf); 741 } 742 743 /* 744 * Crash dump handling. 745 */ 746 747 void 748 oea_dumpsys(void) 749 { 750 printf("dumpsys: TBD\n"); 751 } 752 753 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 754 /* 755 * Soft networking interrupts. 756 */ 757 void 758 softnet(int pendisr) 759 { 760 #define DONETISR(bit, fn) do { \ 761 if (pendisr & (1 << bit)) \ 762 (*fn)(); \ 763 } while (0) 764 765 #include <net/netisr_dispatch.h> 766 767 #undef DONETISR 768 } 769 #endif 770 771 /* 772 * Convert kernel VA to physical address 773 */ 774 paddr_t 775 kvtop(caddr_t addr) 776 { 777 vaddr_t va; 778 paddr_t pa; 779 uintptr_t off; 780 extern char end[]; 781 782 if (addr < end) 783 return (paddr_t)addr; 784 785 va = trunc_page((vaddr_t)addr); 786 off = (uintptr_t)addr - va; 787 788 if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) { 789 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 790 return (paddr_t)addr; 791 } 792 793 return(pa + off); 794 } 795 796 /* 797 * Allocate vm space and mapin the I/O address 798 */ 799 void * 800 mapiodev(paddr_t pa, psize_t len) 801 { 802 paddr_t faddr; 803 vaddr_t taddr, va; 804 int off; 805 806 faddr = trunc_page(pa); 807 off = pa - faddr; 808 len = round_page(off + len); 809 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 810 811 if (va == 0) 812 return NULL; 813 814 for (; len > 0; len -= PAGE_SIZE) { 815 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 816 faddr += PAGE_SIZE; 817 taddr += PAGE_SIZE; 818 } 819 pmap_update(pmap_kernel()); 820 return (void *)(va + off); 821 } 822
Indexes created Thu Oct 02 01:09:59 GMT 2025