oea_machdep.c revision 1.27
1 /* $NetBSD: oea_machdep.c,v 1.27 2006/08/31 18:23:40 matt Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.27 2006/08/31 18:23:40 matt Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/sa.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/trap.h> 82 #include <powerpc/stdarg.h> 83 #include <powerpc/spr.h> 84 #include <powerpc/pte.h> 85 #include <powerpc/altivec.h> 86 #include <machine/powerpc.h> 87 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 91 struct vm_map *exec_map = NULL; 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 101 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 102 struct bat battable[512]; 103 104 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 105 paddr_t msgbuf_paddr; 106 107 void 108 oea_init(void (*handler)(void)) 109 { 110 extern int trapstart[], trapend[]; 111 extern int trapcode[], trapsize[]; 112 extern int sctrap[], scsize[]; 113 extern int alitrap[], alisize[]; 114 extern int dsitrap[], dsisize[]; 115 extern int dsi601trap[], dsi601size[]; 116 extern int decrint[], decrsize[]; 117 extern int tlbimiss[], tlbimsize[]; 118 extern int tlbdlmiss[], tlbdlmsize[]; 119 extern int tlbdsmiss[], tlbdsmsize[]; 120 #if defined(DDB) || defined(KGDB) 121 extern int ddblow[], ddbsize[]; 122 #endif 123 #ifdef IPKDB 124 extern int ipkdblow[], ipkdbsize[]; 125 #endif 126 #ifdef ALTIVEC 127 register_t msr; 128 #endif 129 uintptr_t exc; 130 register_t scratch; 131 unsigned int cpuvers; 132 size_t size; 133 struct cpu_info * const ci = &cpu_info[0]; 134 135 mtspr(SPR_SPRG0, ci); 136 cpuvers = mfpvr() >> 16; 137 138 /* 139 * Initialize proc0 and current pcb and pmap pointers. 140 */ 141 KASSERT(ci != NULL); 142 KASSERT(curcpu() == ci); 143 lwp0.l_cpu = ci; 144 lwp0.l_addr = proc0paddr; 145 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 146 KASSERT(lwp0.l_cpu != NULL); 147 148 curpcb = &proc0paddr->u_pcb; 149 memset(curpcb, 0, sizeof(*curpcb)); 150 #ifdef ALTIVEC 151 /* 152 * Initialize the vectors with NaNs 153 */ 154 for (scratch = 0; scratch < 32; scratch++) { 155 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 156 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 157 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 158 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 159 } 160 curpcb->pcb_vr.vscr = 0; 161 curpcb->pcb_vr.vrsave = 0; 162 #endif 163 curpm = curpcb->pcb_pm = pmap_kernel(); 164 165 /* 166 * Cause a PGM trap if we branch to 0. 167 * 168 * XXX GCC4.1 complains about memset on address zero, so 169 * don't use the builtin. 170 */ 171 #undef memset 172 memset(0, 0, 0x100); 173 174 /* 175 * Set up trap vectors. Don't assume vectors are on 0x100. 176 */ 177 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 178 switch (exc) { 179 default: 180 size = (size_t)trapsize; 181 memcpy((void *)exc, trapcode, size); 182 break; 183 #if 0 184 case EXC_EXI: 185 /* 186 * This one is (potentially) installed during autoconf 187 */ 188 break; 189 #endif 190 case EXC_SC: 191 size = (size_t)scsize; 192 memcpy((void *)EXC_SC, sctrap, size); 193 break; 194 case EXC_ALI: 195 size = (size_t)alisize; 196 memcpy((void *)EXC_ALI, alitrap, size); 197 break; 198 case EXC_DSI: 199 if (cpuvers == MPC601) { 200 size = (size_t)dsi601size; 201 memcpy((void *)EXC_DSI, dsi601trap, size); 202 } else { 203 size = (size_t)dsisize; 204 memcpy((void *)EXC_DSI, dsitrap, size); 205 } 206 break; 207 case EXC_DECR: 208 size = (size_t)decrsize; 209 memcpy((void *)EXC_DECR, decrint, size); 210 break; 211 case EXC_IMISS: 212 size = (size_t)tlbimsize; 213 memcpy((void *)EXC_IMISS, tlbimiss, size); 214 break; 215 case EXC_DLMISS: 216 size = (size_t)tlbdlmsize; 217 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 218 break; 219 case EXC_DSMISS: 220 size = (size_t)tlbdsmsize; 221 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 222 break; 223 case EXC_PERF: 224 size = (size_t)trapsize; 225 memcpy((void *)EXC_PERF, trapcode, size); 226 memcpy((void *)EXC_VEC, trapcode, size); 227 break; 228 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 229 case EXC_RUNMODETRC: 230 if (cpuvers != MPC601) { 231 size = (size_t)trapsize; 232 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 233 break; 234 } 235 /* FALLTHROUGH */ 236 case EXC_PGM: 237 case EXC_TRC: 238 case EXC_BPT: 239 #if defined(DDB) || defined(KGDB) 240 size = (size_t)ddbsize; 241 memcpy((void *)exc, ddblow, size); 242 #if defined(IPKDB) 243 #error "cannot enable IPKDB with DDB or KGDB" 244 #endif 245 #else 246 size = (size_t)ipkdbsize; 247 memcpy((void *)exc, ipkdblow, size); 248 #endif 249 break; 250 #endif /* DDB || IPKDB || KGDB */ 251 } 252 #if 0 253 exc += roundup(size, 32); 254 #endif 255 } 256 257 /* 258 * Get the cache sizes because install_extint calls __syncicache. 259 */ 260 cpu_probe_cache(); 261 262 #define MxSPR_MASK 0x7c1fffff 263 #define MFSPR_MQ 0x7c0002a6 264 #define MTSPR_MQ 0x7c0003a6 265 #define MTSPR_IBAT0L 0x7c1183a6 266 #define MTSPR_IBAT1L 0x7c1383a6 267 #define NOP 0x60000000 268 #define B 0x48000000 269 #define TLBSYNC 0x7c00046c 270 #define SYNC 0x7c0004ac 271 272 #ifdef ALTIVEC 273 #define MFSPR_VRSAVE 0x7c0042a6 274 #define MTSPR_VRSAVE 0x7c0043a6 275 276 /* 277 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 278 * not on a AltiVec capable processor. 279 */ 280 __asm volatile ( 281 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 282 "mfmsr %1; mtmsr %0; isync" 283 : "=r"(msr), "=r"(scratch) 284 : "J"(PSL_VEC)); 285 286 /* 287 * If we aren't on an AltiVec capable processor, we need to zap any of 288 * the sequences we save/restore the VRSAVE SPR into NOPs. 289 */ 290 if (scratch & PSL_VEC) { 291 cpu_altivec = 1; 292 } else { 293 int *ip = trapstart; 294 295 for (; ip < trapend; ip++) { 296 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 297 ip[0] = NOP; /* mfspr */ 298 ip[1] = NOP; /* stw */ 299 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 300 ip[-1] = NOP; /* lwz */ 301 ip[0] = NOP; /* mtspr */ 302 } 303 } 304 } 305 #endif 306 307 /* 308 * If we aren't on a MPC601 processor, we need to zap any of the 309 * sequences we save/restore the MQ SPR into NOPs, and skip over the 310 * sequences where we zap/restore BAT registers on kernel exit/entry. 311 */ 312 if (cpuvers != MPC601) { 313 int *ip = trapstart; 314 315 for (; ip < trapend; ip++) { 316 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 317 ip[0] = NOP; /* mfspr */ 318 ip[1] = NOP; /* stw */ 319 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 320 ip[-1] = NOP; /* lwz */ 321 ip[0] = NOP; /* mtspr */ 322 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 323 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 324 ip[-1] = B | 0x14; /* li */ 325 else 326 ip[-4] = B | 0x24; /* lis */ 327 } 328 } 329 } 330 331 /* 332 * Sync the changed instructions. 333 */ 334 __syncicache((void *) trapstart, 335 (uintptr_t) trapend - (uintptr_t) trapstart); 336 337 /* 338 * If we are on a MPC601 processor, we need to zap any tlbsync 339 * instructions into sync. This differs from the above in 340 * examing all kernel text, as opposed to just the exception handling. 341 * We sync the icache on every instruction found since there are 342 * only very few of them. 343 */ 344 if (cpuvers == MPC601) { 345 extern int kernel_text[], etext[]; 346 int *ip; 347 348 for (ip = kernel_text; ip < etext; ip++) 349 if (*ip == TLBSYNC) { 350 *ip = SYNC; 351 __syncicache(ip, sizeof(*ip)); 352 } 353 } 354 355 /* 356 * Configure a PSL user mask matching this processor. 357 */ 358 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 359 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 360 if (cpuvers == MPC601) { 361 cpu_psluserset &= PSL_601_MASK; 362 cpu_pslusermod &= PSL_601_MASK; 363 } 364 #ifdef ALTIVEC 365 if (cpu_altivec) 366 cpu_pslusermod |= PSL_VEC; 367 #endif 368 369 /* 370 * external interrupt handler install 371 */ 372 if (handler) 373 oea_install_extint(handler); 374 375 __syncicache(0, EXC_LAST + 0x100); 376 377 /* 378 * Now enable translation (and machine checks/recoverable interrupts). 379 */ 380 #ifdef PPC_OEA 381 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 382 : "=r"(scratch) 383 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 384 #endif 385 386 KASSERT(curcpu() == ci); 387 } 388 389 void 390 mpc601_ioseg_add(paddr_t pa, register_t len) 391 { 392 const u_int i = pa >> ADDR_SR_SHFT; 393 394 if (len != BAT_BL_256M) 395 panic("mpc601_ioseg_add: len != 256M"); 396 397 /* 398 * Translate into an I/O segment, load it, and stash away for use 399 * in pmap_bootstrap(). 400 */ 401 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 402 __asm volatile ("mtsrin %0,%1" 403 :: "r"(iosrtable[i]), 404 "r"(pa)); 405 } 406 407 408 #if defined (PPC_OEA) && !defined (PPC_OEA64) && !defined (PPC_OEA64_BRIDGE) 409 void 410 oea_iobat_add(paddr_t pa, register_t len) 411 { 412 static int n = 1; 413 const u_int i = pa >> 28; 414 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 415 battable[i].batu = BATU(pa, len, BAT_Vs); 416 417 /* 418 * Let's start loading the BAT registers. 419 */ 420 switch (n) { 421 case 1: 422 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 423 :: "r"(battable[i].batl), 424 "r"(battable[i].batu)); 425 n = 2; 426 break; 427 case 2: 428 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 429 :: "r"(battable[i].batl), 430 "r"(battable[i].batu)); 431 n = 3; 432 break; 433 case 3: 434 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 435 :: "r"(battable[i].batl), 436 "r"(battable[i].batu)); 437 n = 4; 438 break; 439 default: 440 break; 441 } 442 } 443 444 void 445 oea_iobat_remove(paddr_t pa) 446 { 447 register_t batu; 448 int i, n; 449 450 n = pa >> ADDR_SR_SHFT; 451 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 452 !BAT_VALID_P(battable[n].batu, PSL_PR)) 453 return; 454 battable[n].batl = 0; 455 battable[n].batu = 0; 456 #define BAT_RESET(n) \ 457 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 458 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 459 460 for (i=1 ; i<4 ; i++) { 461 switch (i) { 462 case 1: 463 BATU_GET(1, batu); 464 if (BAT_VA_MATCH_P(batu, pa) && 465 BAT_VALID_P(batu, PSL_PR)) 466 BAT_RESET(1); 467 break; 468 case 2: 469 BATU_GET(2, batu); 470 if (BAT_VA_MATCH_P(batu, pa) && 471 BAT_VALID_P(batu, PSL_PR)) 472 BAT_RESET(2); 473 break; 474 case 3: 475 BATU_GET(3, batu); 476 if (BAT_VA_MATCH_P(batu, pa) && 477 BAT_VALID_P(batu, PSL_PR)) 478 BAT_RESET(3); 479 break; 480 default: 481 break; 482 } 483 } 484 } 485 486 void 487 oea_batinit(paddr_t pa, ...) 488 { 489 struct mem_region *allmem, *availmem, *mp; 490 int i; 491 unsigned int cpuvers; 492 register_t msr = mfmsr(); 493 va_list ap; 494 495 cpuvers = mfpvr() >> 16; 496 497 /* 498 * Initialize BAT registers to unmapped to not generate 499 * overlapping mappings below. 500 * 501 * The 601's implementation differs in the Valid bit being situated 502 * in the lower BAT register, and in being a unified BAT only whose 503 * four entries are accessed through the IBAT[0-3] SPRs. 504 * 505 * Also, while the 601 does distinguish between supervisor/user 506 * protection keys, it does _not_ distinguish between validity in 507 * supervisor/user mode. 508 */ 509 if ((msr & (PSL_IR|PSL_DR)) == 0) { 510 if (cpuvers == MPC601) { 511 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 512 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 513 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 514 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 515 } else { 516 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 517 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 518 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 519 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 520 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 521 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 522 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 523 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 524 } 525 } 526 527 /* 528 * Set up BAT to map physical memory 529 */ 530 if (cpuvers == MPC601) { 531 /* 532 * Set up battable to map the lowest 256 MB area. 533 * Map the lowest 32 MB area via BAT[0-3]; 534 * BAT[01] are fixed, BAT[23] are floating. 535 */ 536 for (i = 0; i < 32; i++) { 537 battable[i].batl = BATL601(i << 23, 538 BAT601_BSM_8M, BAT601_V); 539 battable[i].batu = BATU601(i << 23, 540 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 541 } 542 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 543 :: "r"(battable[0x00000000 >> 23].batl), 544 "r"(battable[0x00000000 >> 23].batu)); 545 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 546 :: "r"(battable[0x00800000 >> 23].batl), 547 "r"(battable[0x00800000 >> 23].batu)); 548 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 549 :: "r"(battable[0x01000000 >> 23].batl), 550 "r"(battable[0x01000000 >> 23].batu)); 551 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 552 :: "r"(battable[0x01800000 >> 23].batl), 553 "r"(battable[0x01800000 >> 23].batu)); 554 } else { 555 /* 556 * Set up BAT0 to only map the lowest 256 MB area 557 */ 558 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 559 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 560 561 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 562 "mtdbatl 0,%0; mtdbatu 0,%1;" 563 :: "r"(battable[0].batl), "r"(battable[0].batu)); 564 } 565 566 /* 567 * Now setup other fixed bat registers 568 * 569 * Note that we still run in real mode, and the BAT 570 * registers were cleared above. 571 */ 572 573 va_start(ap, pa); 574 575 /* 576 * Add any I/O BATs specificed; 577 * use I/O segments on the BAT-starved 601. 578 */ 579 if (cpuvers == MPC601) { 580 while (pa != 0) { 581 register_t len = va_arg(ap, register_t); 582 mpc601_ioseg_add(pa, len); 583 pa = va_arg(ap, paddr_t); 584 } 585 } else { 586 while (pa != 0) { 587 register_t len = va_arg(ap, register_t); 588 oea_iobat_add(pa, len); 589 pa = va_arg(ap, paddr_t); 590 } 591 } 592 593 va_end(ap); 594 595 /* 596 * Set up battable to map all RAM regions. 597 * This is here because mem_regions() call needs bat0 set up. 598 */ 599 mem_regions(&allmem, &availmem); 600 if (cpuvers == MPC601) { 601 for (mp = allmem; mp->size; mp++) { 602 paddr_t paddr = mp->start & 0xff800000; 603 paddr_t end = mp->start + mp->size; 604 605 do { 606 u_int ix = paddr >> 23; 607 608 battable[ix].batl = 609 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 610 battable[ix].batu = 611 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 612 paddr += (1 << 23); 613 } while (paddr < end); 614 } 615 } else { 616 for (mp = allmem; mp->size; mp++) { 617 paddr_t paddr = mp->start & 0xf0000000; 618 paddr_t end = mp->start + mp->size; 619 620 do { 621 u_int ix = paddr >> 28; 622 623 battable[ix].batl = 624 BATL(paddr, BAT_M, BAT_PP_RW); 625 battable[ix].batu = 626 BATU(paddr, BAT_BL_256M, BAT_Vs); 627 paddr += SEGMENT_LENGTH; 628 } while (paddr < end); 629 } 630 } 631 } 632 #endif /* (PPC_OEA) && !(PPC_OEA64) && !(PPC_OEA64_BRIDGE) */ 633 634 void 635 oea_install_extint(void (*handler)(void)) 636 { 637 extern int extint[], extsize[]; 638 extern int extint_call[]; 639 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 640 int omsr, msr; 641 642 #ifdef DIAGNOSTIC 643 if (offset > 0x1ffffff) 644 panic("install_extint: %p too far away (%#lx)", handler, 645 (unsigned long) offset); 646 #endif 647 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 648 : "=r" (omsr), "=r" (msr) 649 : "K" ((u_short)~PSL_EE)); 650 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 651 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 652 __syncicache((void *)extint_call, sizeof extint_call[0]); 653 __syncicache((void *)EXC_EXI, (int)extsize); 654 __asm volatile ("mtmsr %0" :: "r"(omsr)); 655 } 656 657 /* 658 * Machine dependent startup code. 659 */ 660 void 661 oea_startup(const char *model) 662 { 663 uintptr_t sz; 664 caddr_t v; 665 vaddr_t minaddr, maxaddr; 666 char pbuf[9]; 667 u_int i; 668 669 KASSERT(curcpu() != NULL); 670 KASSERT(lwp0.l_cpu != NULL); 671 KASSERT(curcpu()->ci_intstk != 0); 672 KASSERT(curcpu()->ci_intrdepth == -1); 673 674 /* 675 * If the msgbuf is not in segment 0, allocate KVA for it and access 676 * it via mapped pages. [This prevents unneeded BAT switches.] 677 */ 678 sz = round_page(MSGBUFSIZE); 679 v = (caddr_t) msgbuf_paddr; 680 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 681 minaddr = 0; 682 if (uvm_map(kernel_map, &minaddr, sz, 683 NULL, UVM_UNKNOWN_OFFSET, 0, 684 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 685 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 686 panic("startup: cannot allocate VM for msgbuf"); 687 v = (caddr_t)minaddr; 688 for (i = 0; i < sz; i += PAGE_SIZE) { 689 printf("pmap_kenter_pa: 0x%08lx, 0x%08lx\n", 690 minaddr + i, msgbuf_paddr + i); 691 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 692 VM_PROT_READ|VM_PROT_WRITE); 693 } 694 pmap_update(pmap_kernel()); 695 } 696 initmsgbuf(v, sz); 697 698 printf("%s%s", copyright, version); 699 if (model != NULL) 700 printf("Model: %s\n", model); 701 cpu_identify(NULL, 0); 702 703 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 704 printf("total memory = %s\n", pbuf); 705 706 /* 707 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 708 * the bufpages are allocated in case they overlap since it's not 709 * fatal if we can't allocate these. 710 */ 711 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 712 int error; 713 minaddr = 0xDEAC0000; 714 error = uvm_map(kernel_map, &minaddr, 0x30000, 715 NULL, UVM_UNKNOWN_OFFSET, 0, 716 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 717 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 718 if (error != 0 || minaddr != 0xDEAC0000) 719 printf("oea_startup: failed to allocate DEAD " 720 "ZONE: error=%d\n", error); 721 } 722 723 minaddr = 0; 724 /* 725 * Allocate a submap for exec arguments. This map effectively 726 * limits the number of processes exec'ing at any time. These 727 * submaps will be allocated after the dead zone. 728 */ 729 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 730 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 731 732 /* 733 * Allocate a submap for physio 734 */ 735 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 736 VM_PHYS_SIZE, 0, FALSE, NULL); 737 738 #ifndef PMAP_MAP_POOLPAGE 739 /* 740 * No need to allocate an mbuf cluster submap. Mbuf clusters 741 * are allocated via the pool allocator, and we use direct-mapped 742 * pool pages. 743 */ 744 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 745 mclbytes*nmbclusters, VM_MAP_INTRSAFE, FALSE, NULL); 746 #endif 747 748 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 749 printf("avail memory = %s\n", pbuf); 750 } 751 752 /* 753 * Crash dump handling. 754 */ 755 756 void 757 oea_dumpsys(void) 758 { 759 printf("dumpsys: TBD\n"); 760 } 761 762 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 763 /* 764 * Soft networking interrupts. 765 */ 766 void 767 softnet(int pendisr) 768 { 769 #define DONETISR(bit, fn) do { \ 770 if (pendisr & (1 << bit)) \ 771 (*fn)(); \ 772 } while (0) 773 774 #include <net/netisr_dispatch.h> 775 776 #undef DONETISR 777 } 778 #endif 779 780 /* 781 * Convert kernel VA to physical address 782 */ 783 paddr_t 784 kvtop(caddr_t addr) 785 { 786 vaddr_t va; 787 paddr_t pa; 788 uintptr_t off; 789 extern char end[]; 790 791 if (addr < end) 792 return (paddr_t)addr; 793 794 va = trunc_page((vaddr_t)addr); 795 off = (uintptr_t)addr - va; 796 797 if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) { 798 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 799 return (paddr_t)addr; 800 } 801 802 return(pa + off); 803 } 804 805 /* 806 * Allocate vm space and mapin the I/O address 807 */ 808 void * 809 mapiodev(paddr_t pa, psize_t len) 810 { 811 paddr_t faddr; 812 vaddr_t taddr, va; 813 int off; 814 815 faddr = trunc_page(pa); 816 off = pa - faddr; 817 len = round_page(off + len); 818 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 819 820 if (va == 0) 821 return NULL; 822 823 for (; len > 0; len -= PAGE_SIZE) { 824 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 825 faddr += PAGE_SIZE; 826 taddr += PAGE_SIZE; 827 } 828 pmap_update(pmap_kernel()); 829 return (void *)(va + off); 830 } 831 832 void 833 unmapiodev(vaddr_t va, vsize_t len) 834 { 835 paddr_t faddr; 836 837 faddr = trunc_page(va); 838 len = round_page(va - faddr + len); 839 840 pmap_kremove(faddr, len); 841 pmap_update(pmap_kernel()); 842 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 843 } 844
Indexes created Tue Sep 30 17:09:57 GMT 2025