oea_machdep.c revision 1.32
1 /* $NetBSD: oea_machdep.c,v 1.32 2007/03/04 06:00:37 christos Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.32 2007/03/04 06:00:37 christos Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/syscallargs.h> 55 #include <sys/syslog.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/user.h> 59 #include <sys/boot_flag.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/netisr.h> 64 65 #ifdef DDB 66 #include <machine/db_machdep.h> 67 #include <ddb/db_extern.h> 68 #endif 69 70 #ifdef KGDB 71 #include <sys/kgdb.h> 72 #endif 73 74 #ifdef IPKDB 75 #include <ipkdb/ipkdb.h> 76 #endif 77 78 #include <powerpc/oea/bat.h> 79 #include <powerpc/oea/sr_601.h> 80 #include <powerpc/trap.h> 81 #include <powerpc/stdarg.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/pte.h> 84 #include <powerpc/altivec.h> 85 #include <machine/powerpc.h> 86 87 char machine[] = MACHINE; /* from <machine/param.h> */ 88 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 89 90 struct vm_map *exec_map = NULL; 91 struct vm_map *mb_map = NULL; 92 struct vm_map *phys_map = NULL; 93 94 /* 95 * Global variables used here and there 96 */ 97 extern struct user *proc0paddr; 98 99 100 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 101 struct bat battable[512]; 102 103 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 104 paddr_t msgbuf_paddr; 105 106 void 107 oea_init(void (*handler)(void)) 108 { 109 extern int trapstart[], trapend[]; 110 extern int trapcode[], trapsize[]; 111 extern int sctrap[], scsize[]; 112 extern int alitrap[], alisize[]; 113 extern int dsitrap[], dsisize[]; 114 extern int dsi601trap[], dsi601size[]; 115 extern int decrint[], decrsize[]; 116 extern int tlbimiss[], tlbimsize[]; 117 extern int tlbdlmiss[], tlbdlmsize[]; 118 extern int tlbdsmiss[], tlbdsmsize[]; 119 #if defined(DDB) || defined(KGDB) 120 extern int ddblow[], ddbsize[]; 121 #endif 122 #ifdef IPKDB 123 extern int ipkdblow[], ipkdbsize[]; 124 #endif 125 #ifdef ALTIVEC 126 register_t msr; 127 #endif 128 uintptr_t exc; 129 register_t scratch; 130 unsigned int cpuvers; 131 size_t size; 132 struct cpu_info * const ci = &cpu_info[0]; 133 134 mtspr(SPR_SPRG0, ci); 135 cpuvers = mfpvr() >> 16; 136 137 /* 138 * Initialize proc0 and current pcb and pmap pointers. 139 */ 140 KASSERT(ci != NULL); 141 KASSERT(curcpu() == ci); 142 lwp0.l_cpu = ci; 143 lwp0.l_addr = proc0paddr; 144 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 145 KASSERT(lwp0.l_cpu != NULL); 146 147 curpcb = &proc0paddr->u_pcb; 148 memset(curpcb, 0, sizeof(*curpcb)); 149 #ifdef ALTIVEC 150 /* 151 * Initialize the vectors with NaNs 152 */ 153 for (scratch = 0; scratch < 32; scratch++) { 154 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 155 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 156 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 157 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 158 } 159 curpcb->pcb_vr.vscr = 0; 160 curpcb->pcb_vr.vrsave = 0; 161 #endif 162 curpm = curpcb->pcb_pm = pmap_kernel(); 163 164 /* 165 * Cause a PGM trap if we branch to 0. 166 * 167 * XXX GCC4.1 complains about memset on address zero, so 168 * don't use the builtin. 169 */ 170 #undef memset 171 memset(0, 0, 0x100); 172 173 /* 174 * Set up trap vectors. Don't assume vectors are on 0x100. 175 */ 176 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 177 switch (exc) { 178 default: 179 size = (size_t)trapsize; 180 memcpy((void *)exc, trapcode, size); 181 break; 182 #if 0 183 case EXC_EXI: 184 /* 185 * This one is (potentially) installed during autoconf 186 */ 187 break; 188 #endif 189 case EXC_SC: 190 size = (size_t)scsize; 191 memcpy((void *)EXC_SC, sctrap, size); 192 break; 193 case EXC_ALI: 194 size = (size_t)alisize; 195 memcpy((void *)EXC_ALI, alitrap, size); 196 break; 197 case EXC_DSI: 198 if (cpuvers == MPC601) { 199 size = (size_t)dsi601size; 200 memcpy((void *)EXC_DSI, dsi601trap, size); 201 } else { 202 size = (size_t)dsisize; 203 memcpy((void *)EXC_DSI, dsitrap, size); 204 } 205 break; 206 case EXC_DECR: 207 size = (size_t)decrsize; 208 memcpy((void *)EXC_DECR, decrint, size); 209 break; 210 case EXC_IMISS: 211 size = (size_t)tlbimsize; 212 memcpy((void *)EXC_IMISS, tlbimiss, size); 213 break; 214 case EXC_DLMISS: 215 size = (size_t)tlbdlmsize; 216 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 217 break; 218 case EXC_DSMISS: 219 size = (size_t)tlbdsmsize; 220 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 221 break; 222 case EXC_PERF: 223 size = (size_t)trapsize; 224 memcpy((void *)EXC_PERF, trapcode, size); 225 memcpy((void *)EXC_VEC, trapcode, size); 226 break; 227 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 228 case EXC_RUNMODETRC: 229 if (cpuvers != MPC601) { 230 size = (size_t)trapsize; 231 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 232 break; 233 } 234 /* FALLTHROUGH */ 235 case EXC_PGM: 236 case EXC_TRC: 237 case EXC_BPT: 238 #if defined(DDB) || defined(KGDB) 239 size = (size_t)ddbsize; 240 memcpy((void *)exc, ddblow, size); 241 #if defined(IPKDB) 242 #error "cannot enable IPKDB with DDB or KGDB" 243 #endif 244 #else 245 size = (size_t)ipkdbsize; 246 memcpy((void *)exc, ipkdblow, size); 247 #endif 248 break; 249 #endif /* DDB || IPKDB || KGDB */ 250 } 251 #if 0 252 exc += roundup(size, 32); 253 #endif 254 } 255 256 /* 257 * Get the cache sizes because install_extint calls __syncicache. 258 */ 259 cpu_probe_cache(); 260 261 #define MxSPR_MASK 0x7c1fffff 262 #define MFSPR_MQ 0x7c0002a6 263 #define MTSPR_MQ 0x7c0003a6 264 #define MTSPR_IBAT0L 0x7c1183a6 265 #define MTSPR_IBAT1L 0x7c1383a6 266 #define NOP 0x60000000 267 #define B 0x48000000 268 #define TLBSYNC 0x7c00046c 269 #define SYNC 0x7c0004ac 270 271 #ifdef ALTIVEC 272 #define MFSPR_VRSAVE 0x7c0042a6 273 #define MTSPR_VRSAVE 0x7c0043a6 274 275 /* 276 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 277 * not on a AltiVec capable processor. 278 */ 279 __asm volatile ( 280 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 281 "mfmsr %1; mtmsr %0; isync" 282 : "=r"(msr), "=r"(scratch) 283 : "J"(PSL_VEC)); 284 285 /* 286 * If we aren't on an AltiVec capable processor, we need to zap any of 287 * the sequences we save/restore the VRSAVE SPR into NOPs. 288 */ 289 if (scratch & PSL_VEC) { 290 cpu_altivec = 1; 291 } else { 292 int *ip = trapstart; 293 294 for (; ip < trapend; ip++) { 295 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 296 ip[0] = NOP; /* mfspr */ 297 ip[1] = NOP; /* stw */ 298 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 299 ip[-1] = NOP; /* lwz */ 300 ip[0] = NOP; /* mtspr */ 301 } 302 } 303 } 304 #endif 305 306 /* 307 * If we aren't on a MPC601 processor, we need to zap any of the 308 * sequences we save/restore the MQ SPR into NOPs, and skip over the 309 * sequences where we zap/restore BAT registers on kernel exit/entry. 310 */ 311 if (cpuvers != MPC601) { 312 int *ip = trapstart; 313 314 for (; ip < trapend; ip++) { 315 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 316 ip[0] = NOP; /* mfspr */ 317 ip[1] = NOP; /* stw */ 318 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 319 ip[-1] = NOP; /* lwz */ 320 ip[0] = NOP; /* mtspr */ 321 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 322 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 323 ip[-1] = B | 0x14; /* li */ 324 else 325 ip[-4] = B | 0x24; /* lis */ 326 } 327 } 328 } 329 330 /* 331 * Sync the changed instructions. 332 */ 333 __syncicache((void *) trapstart, 334 (uintptr_t) trapend - (uintptr_t) trapstart); 335 336 /* 337 * If we are on a MPC601 processor, we need to zap any tlbsync 338 * instructions into sync. This differs from the above in 339 * examing all kernel text, as opposed to just the exception handling. 340 * We sync the icache on every instruction found since there are 341 * only very few of them. 342 */ 343 if (cpuvers == MPC601) { 344 extern int kernel_text[], etext[]; 345 int *ip; 346 347 for (ip = kernel_text; ip < etext; ip++) 348 if (*ip == TLBSYNC) { 349 *ip = SYNC; 350 __syncicache(ip, sizeof(*ip)); 351 } 352 } 353 354 /* 355 * Configure a PSL user mask matching this processor. 356 */ 357 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 358 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 359 if (cpuvers == MPC601) { 360 cpu_psluserset &= PSL_601_MASK; 361 cpu_pslusermod &= PSL_601_MASK; 362 } 363 #ifdef ALTIVEC 364 if (cpu_altivec) 365 cpu_pslusermod |= PSL_VEC; 366 #endif 367 368 /* 369 * external interrupt handler install 370 */ 371 if (handler) 372 oea_install_extint(handler); 373 374 __syncicache(0, EXC_LAST + 0x100); 375 376 /* 377 * Now enable translation (and machine checks/recoverable interrupts). 378 */ 379 #ifdef PPC_OEA 380 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 381 : "=r"(scratch) 382 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 383 #endif 384 385 KASSERT(curcpu() == ci); 386 } 387 388 void 389 mpc601_ioseg_add(paddr_t pa, register_t len) 390 { 391 const u_int i = pa >> ADDR_SR_SHFT; 392 393 if (len != BAT_BL_256M) 394 panic("mpc601_ioseg_add: len != 256M"); 395 396 /* 397 * Translate into an I/O segment, load it, and stash away for use 398 * in pmap_bootstrap(). 399 */ 400 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 401 __asm volatile ("mtsrin %0,%1" 402 :: "r"(iosrtable[i]), 403 "r"(pa)); 404 } 405 406 407 #if defined (PPC_OEA) && !defined (PPC_OEA64) && !defined (PPC_OEA64_BRIDGE) 408 void 409 oea_iobat_add(paddr_t pa, register_t len) 410 { 411 static int n = 1; 412 const u_int i = pa >> 28; 413 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 414 battable[i].batu = BATU(pa, len, BAT_Vs); 415 416 /* 417 * Let's start loading the BAT registers. 418 */ 419 switch (n) { 420 case 1: 421 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 422 :: "r"(battable[i].batl), 423 "r"(battable[i].batu)); 424 n = 2; 425 break; 426 case 2: 427 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 428 :: "r"(battable[i].batl), 429 "r"(battable[i].batu)); 430 n = 3; 431 break; 432 case 3: 433 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 434 :: "r"(battable[i].batl), 435 "r"(battable[i].batu)); 436 n = 4; 437 break; 438 default: 439 break; 440 } 441 } 442 443 void 444 oea_iobat_remove(paddr_t pa) 445 { 446 register_t batu; 447 int i, n; 448 449 n = pa >> ADDR_SR_SHFT; 450 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 451 !BAT_VALID_P(battable[n].batu, PSL_PR)) 452 return; 453 battable[n].batl = 0; 454 battable[n].batu = 0; 455 #define BAT_RESET(n) \ 456 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 457 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 458 459 for (i=1 ; i<4 ; i++) { 460 switch (i) { 461 case 1: 462 BATU_GET(1, batu); 463 if (BAT_VA_MATCH_P(batu, pa) && 464 BAT_VALID_P(batu, PSL_PR)) 465 BAT_RESET(1); 466 break; 467 case 2: 468 BATU_GET(2, batu); 469 if (BAT_VA_MATCH_P(batu, pa) && 470 BAT_VALID_P(batu, PSL_PR)) 471 BAT_RESET(2); 472 break; 473 case 3: 474 BATU_GET(3, batu); 475 if (BAT_VA_MATCH_P(batu, pa) && 476 BAT_VALID_P(batu, PSL_PR)) 477 BAT_RESET(3); 478 break; 479 default: 480 break; 481 } 482 } 483 } 484 485 void 486 oea_batinit(paddr_t pa, ...) 487 { 488 struct mem_region *allmem, *availmem, *mp; 489 int i; 490 unsigned int cpuvers; 491 register_t msr = mfmsr(); 492 va_list ap; 493 494 cpuvers = mfpvr() >> 16; 495 496 /* 497 * Initialize BAT registers to unmapped to not generate 498 * overlapping mappings below. 499 * 500 * The 601's implementation differs in the Valid bit being situated 501 * in the lower BAT register, and in being a unified BAT only whose 502 * four entries are accessed through the IBAT[0-3] SPRs. 503 * 504 * Also, while the 601 does distinguish between supervisor/user 505 * protection keys, it does _not_ distinguish between validity in 506 * supervisor/user mode. 507 */ 508 if ((msr & (PSL_IR|PSL_DR)) == 0) { 509 if (cpuvers == MPC601) { 510 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 511 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 512 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 513 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 514 } else { 515 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 516 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 517 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 518 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 519 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 520 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 521 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 522 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 523 } 524 } 525 526 /* 527 * Set up BAT to map physical memory 528 */ 529 if (cpuvers == MPC601) { 530 /* 531 * Set up battable to map the lowest 256 MB area. 532 * Map the lowest 32 MB area via BAT[0-3]; 533 * BAT[01] are fixed, BAT[23] are floating. 534 */ 535 for (i = 0; i < 32; i++) { 536 battable[i].batl = BATL601(i << 23, 537 BAT601_BSM_8M, BAT601_V); 538 battable[i].batu = BATU601(i << 23, 539 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 540 } 541 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 542 :: "r"(battable[0x00000000 >> 23].batl), 543 "r"(battable[0x00000000 >> 23].batu)); 544 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 545 :: "r"(battable[0x00800000 >> 23].batl), 546 "r"(battable[0x00800000 >> 23].batu)); 547 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 548 :: "r"(battable[0x01000000 >> 23].batl), 549 "r"(battable[0x01000000 >> 23].batu)); 550 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 551 :: "r"(battable[0x01800000 >> 23].batl), 552 "r"(battable[0x01800000 >> 23].batu)); 553 } else { 554 /* 555 * Set up BAT0 to only map the lowest 256 MB area 556 */ 557 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 558 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 559 560 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 561 "mtdbatl 0,%0; mtdbatu 0,%1;" 562 :: "r"(battable[0].batl), "r"(battable[0].batu)); 563 } 564 565 /* 566 * Now setup other fixed bat registers 567 * 568 * Note that we still run in real mode, and the BAT 569 * registers were cleared above. 570 */ 571 572 va_start(ap, pa); 573 574 /* 575 * Add any I/O BATs specificed; 576 * use I/O segments on the BAT-starved 601. 577 */ 578 if (cpuvers == MPC601) { 579 while (pa != 0) { 580 register_t len = va_arg(ap, register_t); 581 mpc601_ioseg_add(pa, len); 582 pa = va_arg(ap, paddr_t); 583 } 584 } else { 585 while (pa != 0) { 586 register_t len = va_arg(ap, register_t); 587 oea_iobat_add(pa, len); 588 pa = va_arg(ap, paddr_t); 589 } 590 } 591 592 va_end(ap); 593 594 /* 595 * Set up battable to map all RAM regions. 596 * This is here because mem_regions() call needs bat0 set up. 597 */ 598 mem_regions(&allmem, &availmem); 599 if (cpuvers == MPC601) { 600 for (mp = allmem; mp->size; mp++) { 601 paddr_t paddr = mp->start & 0xff800000; 602 paddr_t end = mp->start + mp->size; 603 604 do { 605 u_int ix = paddr >> 23; 606 607 battable[ix].batl = 608 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 609 battable[ix].batu = 610 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 611 paddr += (1 << 23); 612 } while (paddr < end); 613 } 614 } else { 615 for (mp = allmem; mp->size; mp++) { 616 paddr_t paddr = mp->start & 0xf0000000; 617 paddr_t end = mp->start + mp->size; 618 619 do { 620 u_int ix = paddr >> 28; 621 622 battable[ix].batl = 623 BATL(paddr, BAT_M, BAT_PP_RW); 624 battable[ix].batu = 625 BATU(paddr, BAT_BL_256M, BAT_Vs); 626 paddr += SEGMENT_LENGTH; 627 } while (paddr < end); 628 } 629 } 630 } 631 #endif /* (PPC_OEA) && !(PPC_OEA64) && !(PPC_OEA64_BRIDGE) */ 632 633 void 634 oea_install_extint(void (*handler)(void)) 635 { 636 extern int extint[], extsize[]; 637 extern int extint_call[]; 638 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 639 int omsr, msr; 640 641 #ifdef DIAGNOSTIC 642 if (offset > 0x1ffffff) 643 panic("install_extint: %p too far away (%#lx)", handler, 644 (unsigned long) offset); 645 #endif 646 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 647 : "=r" (omsr), "=r" (msr) 648 : "K" ((u_short)~PSL_EE)); 649 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 650 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 651 __syncicache((void *)extint_call, sizeof extint_call[0]); 652 __syncicache((void *)EXC_EXI, (int)extsize); 653 __asm volatile ("mtmsr %0" :: "r"(omsr)); 654 } 655 656 /* 657 * Machine dependent startup code. 658 */ 659 void 660 oea_startup(const char *model) 661 { 662 uintptr_t sz; 663 void *v; 664 vaddr_t minaddr, maxaddr; 665 char pbuf[9]; 666 u_int i; 667 668 KASSERT(curcpu() != NULL); 669 KASSERT(lwp0.l_cpu != NULL); 670 KASSERT(curcpu()->ci_intstk != 0); 671 KASSERT(curcpu()->ci_intrdepth == -1); 672 673 /* 674 * If the msgbuf is not in segment 0, allocate KVA for it and access 675 * it via mapped pages. [This prevents unneeded BAT switches.] 676 */ 677 sz = round_page(MSGBUFSIZE); 678 v = (void *) msgbuf_paddr; 679 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 680 minaddr = 0; 681 if (uvm_map(kernel_map, &minaddr, sz, 682 NULL, UVM_UNKNOWN_OFFSET, 0, 683 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 684 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 685 panic("startup: cannot allocate VM for msgbuf"); 686 v = (void *)minaddr; 687 for (i = 0; i < sz; i += PAGE_SIZE) { 688 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 689 VM_PROT_READ|VM_PROT_WRITE); 690 } 691 pmap_update(pmap_kernel()); 692 } 693 initmsgbuf(v, sz); 694 695 printf("%s%s", copyright, version); 696 if (model != NULL) 697 printf("Model: %s\n", model); 698 cpu_identify(NULL, 0); 699 700 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 701 printf("total memory = %s\n", pbuf); 702 703 /* 704 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 705 * the bufpages are allocated in case they overlap since it's not 706 * fatal if we can't allocate these. 707 */ 708 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 709 int error; 710 minaddr = 0xDEAC0000; 711 error = uvm_map(kernel_map, &minaddr, 0x30000, 712 NULL, UVM_UNKNOWN_OFFSET, 0, 713 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 714 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 715 if (error != 0 || minaddr != 0xDEAC0000) 716 printf("oea_startup: failed to allocate DEAD " 717 "ZONE: error=%d\n", error); 718 } 719 720 minaddr = 0; 721 /* 722 * Allocate a submap for exec arguments. This map effectively 723 * limits the number of processes exec'ing at any time. These 724 * submaps will be allocated after the dead zone. 725 */ 726 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 727 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 728 729 /* 730 * Allocate a submap for physio 731 */ 732 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 733 VM_PHYS_SIZE, 0, false, NULL); 734 735 #ifndef PMAP_MAP_POOLPAGE 736 /* 737 * No need to allocate an mbuf cluster submap. Mbuf clusters 738 * are allocated via the pool allocator, and we use direct-mapped 739 * pool pages. 740 */ 741 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 742 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 743 #endif 744 745 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 746 printf("avail memory = %s\n", pbuf); 747 } 748 749 /* 750 * Crash dump handling. 751 */ 752 753 void 754 oea_dumpsys(void) 755 { 756 printf("dumpsys: TBD\n"); 757 } 758 759 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 760 /* 761 * Soft networking interrupts. 762 */ 763 void 764 softnet(int pendisr) 765 { 766 #define DONETISR(bit, fn) do { \ 767 if (pendisr & (1 << bit)) \ 768 (*fn)(); \ 769 } while (0) 770 771 #include <net/netisr_dispatch.h> 772 773 #undef DONETISR 774 } 775 #endif 776 777 /* 778 * Convert kernel VA to physical address 779 */ 780 paddr_t 781 kvtop(void *addr) 782 { 783 vaddr_t va; 784 paddr_t pa; 785 uintptr_t off; 786 extern char end[]; 787 788 if (addr < end) 789 return (paddr_t)addr; 790 791 va = trunc_page((vaddr_t)addr); 792 off = (uintptr_t)addr - va; 793 794 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 795 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 796 return (paddr_t)addr; 797 } 798 799 return(pa + off); 800 } 801 802 /* 803 * Allocate vm space and mapin the I/O address 804 */ 805 void * 806 mapiodev(paddr_t pa, psize_t len) 807 { 808 paddr_t faddr; 809 vaddr_t taddr, va; 810 int off; 811 812 faddr = trunc_page(pa); 813 off = pa - faddr; 814 len = round_page(off + len); 815 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 816 817 if (va == 0) 818 return NULL; 819 820 for (; len > 0; len -= PAGE_SIZE) { 821 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 822 faddr += PAGE_SIZE; 823 taddr += PAGE_SIZE; 824 } 825 pmap_update(pmap_kernel()); 826 return (void *)(va + off); 827 } 828 829 void 830 unmapiodev(vaddr_t va, vsize_t len) 831 { 832 paddr_t faddr; 833 834 if (! va) 835 return; 836 837 faddr = trunc_page(va); 838 len = round_page(va - faddr + len); 839 840 pmap_kremove(faddr, len); 841 pmap_update(pmap_kernel()); 842 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 843 } 844
Indexes created Tue Sep 30 17:09:57 GMT 2025