oea_machdep.c revision 1.34
1 /* $NetBSD: oea_machdep.c,v 1.34 2007/05/17 14:51:26 yamt Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.34 2007/05/17 14:51:26 yamt Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/syscallargs.h> 55 #include <sys/syslog.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/user.h> 59 #include <sys/boot_flag.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/netisr.h> 64 65 #ifdef DDB 66 #include <machine/db_machdep.h> 67 #include <ddb/db_extern.h> 68 #endif 69 70 #ifdef KGDB 71 #include <sys/kgdb.h> 72 #endif 73 74 #ifdef IPKDB 75 #include <ipkdb/ipkdb.h> 76 #endif 77 78 #include <powerpc/oea/bat.h> 79 #include <powerpc/oea/sr_601.h> 80 #include <powerpc/trap.h> 81 #include <powerpc/stdarg.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/pte.h> 84 #include <powerpc/altivec.h> 85 #include <machine/powerpc.h> 86 87 char machine[] = MACHINE; /* from <machine/param.h> */ 88 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 89 90 struct vm_map *exec_map = NULL; 91 struct vm_map *mb_map = NULL; 92 struct vm_map *phys_map = NULL; 93 94 /* 95 * Global variables used here and there 96 */ 97 extern struct user *proc0paddr; 98 99 static void trap0(void *); 100 101 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 102 struct bat battable[512]; 103 104 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 105 paddr_t msgbuf_paddr; 106 107 void 108 oea_init(void (*handler)(void)) 109 { 110 extern int trapstart[], trapend[]; 111 extern int trapcode[], trapsize[]; 112 extern int sctrap[], scsize[]; 113 extern int alitrap[], alisize[]; 114 extern int dsitrap[], dsisize[]; 115 extern int dsi601trap[], dsi601size[]; 116 extern int decrint[], decrsize[]; 117 extern int tlbimiss[], tlbimsize[]; 118 extern int tlbdlmiss[], tlbdlmsize[]; 119 extern int tlbdsmiss[], tlbdsmsize[]; 120 #if defined(DDB) || defined(KGDB) 121 extern int ddblow[], ddbsize[]; 122 #endif 123 #ifdef IPKDB 124 extern int ipkdblow[], ipkdbsize[]; 125 #endif 126 #ifdef ALTIVEC 127 register_t msr; 128 #endif 129 uintptr_t exc; 130 register_t scratch; 131 unsigned int cpuvers; 132 size_t size; 133 struct cpu_info * const ci = &cpu_info[0]; 134 135 mtspr(SPR_SPRG0, ci); 136 cpuvers = mfpvr() >> 16; 137 138 /* 139 * Initialize proc0 and current pcb and pmap pointers. 140 */ 141 KASSERT(ci != NULL); 142 KASSERT(curcpu() == ci); 143 lwp0.l_cpu = ci; 144 lwp0.l_addr = proc0paddr; 145 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 146 KASSERT(lwp0.l_cpu != NULL); 147 148 curpcb = &proc0paddr->u_pcb; 149 memset(curpcb, 0, sizeof(*curpcb)); 150 #ifdef ALTIVEC 151 /* 152 * Initialize the vectors with NaNs 153 */ 154 for (scratch = 0; scratch < 32; scratch++) { 155 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 156 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 157 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 158 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 159 } 160 curpcb->pcb_vr.vscr = 0; 161 curpcb->pcb_vr.vrsave = 0; 162 #endif 163 curpm = curpcb->pcb_pm = pmap_kernel(); 164 165 /* 166 * Cause a PGM trap if we branch to 0. 167 * 168 * XXX GCC4.1 complains about memset on address zero, so 169 * don't use the builtin. 170 */ 171 #undef memset 172 memset(0, 0, 0x100); 173 174 /* 175 * Set up trap vectors. Don't assume vectors are on 0x100. 176 */ 177 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 178 switch (exc) { 179 default: 180 size = (size_t)trapsize; 181 memcpy((void *)exc, trapcode, size); 182 break; 183 #if 0 184 case EXC_EXI: 185 /* 186 * This one is (potentially) installed during autoconf 187 */ 188 break; 189 #endif 190 case EXC_SC: 191 size = (size_t)scsize; 192 memcpy((void *)EXC_SC, sctrap, size); 193 break; 194 case EXC_ALI: 195 size = (size_t)alisize; 196 memcpy((void *)EXC_ALI, alitrap, size); 197 break; 198 case EXC_DSI: 199 if (cpuvers == MPC601) { 200 size = (size_t)dsi601size; 201 memcpy((void *)EXC_DSI, dsi601trap, size); 202 } else { 203 size = (size_t)dsisize; 204 memcpy((void *)EXC_DSI, dsitrap, size); 205 } 206 break; 207 case EXC_DECR: 208 size = (size_t)decrsize; 209 memcpy((void *)EXC_DECR, decrint, size); 210 break; 211 case EXC_IMISS: 212 size = (size_t)tlbimsize; 213 memcpy((void *)EXC_IMISS, tlbimiss, size); 214 break; 215 case EXC_DLMISS: 216 size = (size_t)tlbdlmsize; 217 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 218 break; 219 case EXC_DSMISS: 220 size = (size_t)tlbdsmsize; 221 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 222 break; 223 case EXC_PERF: 224 size = (size_t)trapsize; 225 memcpy((void *)EXC_PERF, trapcode, size); 226 memcpy((void *)EXC_VEC, trapcode, size); 227 break; 228 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 229 case EXC_RUNMODETRC: 230 if (cpuvers != MPC601) { 231 size = (size_t)trapsize; 232 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 233 break; 234 } 235 /* FALLTHROUGH */ 236 case EXC_PGM: 237 case EXC_TRC: 238 case EXC_BPT: 239 #if defined(DDB) || defined(KGDB) 240 size = (size_t)ddbsize; 241 memcpy((void *)exc, ddblow, size); 242 #if defined(IPKDB) 243 #error "cannot enable IPKDB with DDB or KGDB" 244 #endif 245 #else 246 size = (size_t)ipkdbsize; 247 memcpy((void *)exc, ipkdblow, size); 248 #endif 249 break; 250 #endif /* DDB || IPKDB || KGDB */ 251 } 252 #if 0 253 exc += roundup(size, 32); 254 #endif 255 } 256 257 /* 258 * Install a branch absolute to trap0 to force a panic. 259 */ 260 *(uint32_t *) 0 = 0x7c6802a6; 261 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 262 263 /* 264 * Get the cache sizes because install_extint calls __syncicache. 265 */ 266 cpu_probe_cache(); 267 268 #define MxSPR_MASK 0x7c1fffff 269 #define MFSPR_MQ 0x7c0002a6 270 #define MTSPR_MQ 0x7c0003a6 271 #define MTSPR_IBAT0L 0x7c1183a6 272 #define MTSPR_IBAT1L 0x7c1383a6 273 #define NOP 0x60000000 274 #define B 0x48000000 275 #define TLBSYNC 0x7c00046c 276 #define SYNC 0x7c0004ac 277 278 #ifdef ALTIVEC 279 #define MFSPR_VRSAVE 0x7c0042a6 280 #define MTSPR_VRSAVE 0x7c0043a6 281 282 /* 283 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 284 * not on a AltiVec capable processor. 285 */ 286 __asm volatile ( 287 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 288 "mfmsr %1; mtmsr %0; isync" 289 : "=r"(msr), "=r"(scratch) 290 : "J"(PSL_VEC)); 291 292 /* 293 * If we aren't on an AltiVec capable processor, we need to zap any of 294 * the sequences we save/restore the VRSAVE SPR into NOPs. 295 */ 296 if (scratch & PSL_VEC) { 297 cpu_altivec = 1; 298 } else { 299 int *ip = trapstart; 300 301 for (; ip < trapend; ip++) { 302 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 303 ip[0] = NOP; /* mfspr */ 304 ip[1] = NOP; /* stw */ 305 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 306 ip[-1] = NOP; /* lwz */ 307 ip[0] = NOP; /* mtspr */ 308 } 309 } 310 } 311 #endif 312 313 /* 314 * If we aren't on a MPC601 processor, we need to zap any of the 315 * sequences we save/restore the MQ SPR into NOPs, and skip over the 316 * sequences where we zap/restore BAT registers on kernel exit/entry. 317 */ 318 if (cpuvers != MPC601) { 319 int *ip = trapstart; 320 321 for (; ip < trapend; ip++) { 322 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 323 ip[0] = NOP; /* mfspr */ 324 ip[1] = NOP; /* stw */ 325 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 326 ip[-1] = NOP; /* lwz */ 327 ip[0] = NOP; /* mtspr */ 328 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 329 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 330 ip[-1] = B | 0x14; /* li */ 331 else 332 ip[-4] = B | 0x24; /* lis */ 333 } 334 } 335 } 336 337 /* 338 * Sync the changed instructions. 339 */ 340 __syncicache((void *) trapstart, 341 (uintptr_t) trapend - (uintptr_t) trapstart); 342 343 /* 344 * If we are on a MPC601 processor, we need to zap any tlbsync 345 * instructions into sync. This differs from the above in 346 * examing all kernel text, as opposed to just the exception handling. 347 * We sync the icache on every instruction found since there are 348 * only very few of them. 349 */ 350 if (cpuvers == MPC601) { 351 extern int kernel_text[], etext[]; 352 int *ip; 353 354 for (ip = kernel_text; ip < etext; ip++) 355 if (*ip == TLBSYNC) { 356 *ip = SYNC; 357 __syncicache(ip, sizeof(*ip)); 358 } 359 } 360 361 /* 362 * Configure a PSL user mask matching this processor. 363 */ 364 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 365 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 366 if (cpuvers == MPC601) { 367 cpu_psluserset &= PSL_601_MASK; 368 cpu_pslusermod &= PSL_601_MASK; 369 } 370 #ifdef ALTIVEC 371 if (cpu_altivec) 372 cpu_pslusermod |= PSL_VEC; 373 #endif 374 375 /* 376 * external interrupt handler install 377 */ 378 if (handler) 379 oea_install_extint(handler); 380 381 __syncicache(0, EXC_LAST + 0x100); 382 383 /* 384 * Now enable translation (and machine checks/recoverable interrupts). 385 */ 386 #ifdef PPC_OEA 387 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 388 : "=r"(scratch) 389 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 390 #endif 391 392 KASSERT(curcpu() == ci); 393 } 394 395 void 396 mpc601_ioseg_add(paddr_t pa, register_t len) 397 { 398 const u_int i = pa >> ADDR_SR_SHFT; 399 400 if (len != BAT_BL_256M) 401 panic("mpc601_ioseg_add: len != 256M"); 402 403 /* 404 * Translate into an I/O segment, load it, and stash away for use 405 * in pmap_bootstrap(). 406 */ 407 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 408 __asm volatile ("mtsrin %0,%1" 409 :: "r"(iosrtable[i]), 410 "r"(pa)); 411 } 412 413 414 #if defined (PPC_OEA) && !defined (PPC_OEA64) && !defined (PPC_OEA64_BRIDGE) 415 void 416 oea_iobat_add(paddr_t pa, register_t len) 417 { 418 static int n = 1; 419 const u_int i = pa >> 28; 420 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 421 battable[i].batu = BATU(pa, len, BAT_Vs); 422 423 /* 424 * Let's start loading the BAT registers. 425 */ 426 switch (n) { 427 case 1: 428 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 429 :: "r"(battable[i].batl), 430 "r"(battable[i].batu)); 431 n = 2; 432 break; 433 case 2: 434 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 435 :: "r"(battable[i].batl), 436 "r"(battable[i].batu)); 437 n = 3; 438 break; 439 case 3: 440 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 441 :: "r"(battable[i].batl), 442 "r"(battable[i].batu)); 443 n = 4; 444 break; 445 default: 446 break; 447 } 448 } 449 450 void 451 oea_iobat_remove(paddr_t pa) 452 { 453 register_t batu; 454 int i, n; 455 456 n = pa >> ADDR_SR_SHFT; 457 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 458 !BAT_VALID_P(battable[n].batu, PSL_PR)) 459 return; 460 battable[n].batl = 0; 461 battable[n].batu = 0; 462 #define BAT_RESET(n) \ 463 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 464 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 465 466 for (i=1 ; i<4 ; i++) { 467 switch (i) { 468 case 1: 469 BATU_GET(1, batu); 470 if (BAT_VA_MATCH_P(batu, pa) && 471 BAT_VALID_P(batu, PSL_PR)) 472 BAT_RESET(1); 473 break; 474 case 2: 475 BATU_GET(2, batu); 476 if (BAT_VA_MATCH_P(batu, pa) && 477 BAT_VALID_P(batu, PSL_PR)) 478 BAT_RESET(2); 479 break; 480 case 3: 481 BATU_GET(3, batu); 482 if (BAT_VA_MATCH_P(batu, pa) && 483 BAT_VALID_P(batu, PSL_PR)) 484 BAT_RESET(3); 485 break; 486 default: 487 break; 488 } 489 } 490 } 491 492 void 493 oea_batinit(paddr_t pa, ...) 494 { 495 struct mem_region *allmem, *availmem, *mp; 496 int i; 497 unsigned int cpuvers; 498 register_t msr = mfmsr(); 499 va_list ap; 500 501 cpuvers = mfpvr() >> 16; 502 503 /* 504 * Initialize BAT registers to unmapped to not generate 505 * overlapping mappings below. 506 * 507 * The 601's implementation differs in the Valid bit being situated 508 * in the lower BAT register, and in being a unified BAT only whose 509 * four entries are accessed through the IBAT[0-3] SPRs. 510 * 511 * Also, while the 601 does distinguish between supervisor/user 512 * protection keys, it does _not_ distinguish between validity in 513 * supervisor/user mode. 514 */ 515 if ((msr & (PSL_IR|PSL_DR)) == 0) { 516 if (cpuvers == MPC601) { 517 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 518 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 519 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 520 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 521 } else { 522 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 523 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 524 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 525 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 526 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 527 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 528 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 529 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 530 } 531 } 532 533 /* 534 * Set up BAT to map physical memory 535 */ 536 if (cpuvers == MPC601) { 537 /* 538 * Set up battable to map the lowest 256 MB area. 539 * Map the lowest 32 MB area via BAT[0-3]; 540 * BAT[01] are fixed, BAT[23] are floating. 541 */ 542 for (i = 0; i < 32; i++) { 543 battable[i].batl = BATL601(i << 23, 544 BAT601_BSM_8M, BAT601_V); 545 battable[i].batu = BATU601(i << 23, 546 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 547 } 548 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 549 :: "r"(battable[0x00000000 >> 23].batl), 550 "r"(battable[0x00000000 >> 23].batu)); 551 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 552 :: "r"(battable[0x00800000 >> 23].batl), 553 "r"(battable[0x00800000 >> 23].batu)); 554 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 555 :: "r"(battable[0x01000000 >> 23].batl), 556 "r"(battable[0x01000000 >> 23].batu)); 557 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 558 :: "r"(battable[0x01800000 >> 23].batl), 559 "r"(battable[0x01800000 >> 23].batu)); 560 } else { 561 /* 562 * Set up BAT0 to only map the lowest 256 MB area 563 */ 564 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 565 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 566 567 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 568 "mtdbatl 0,%0; mtdbatu 0,%1;" 569 :: "r"(battable[0].batl), "r"(battable[0].batu)); 570 } 571 572 /* 573 * Now setup other fixed bat registers 574 * 575 * Note that we still run in real mode, and the BAT 576 * registers were cleared above. 577 */ 578 579 va_start(ap, pa); 580 581 /* 582 * Add any I/O BATs specificed; 583 * use I/O segments on the BAT-starved 601. 584 */ 585 if (cpuvers == MPC601) { 586 while (pa != 0) { 587 register_t len = va_arg(ap, register_t); 588 mpc601_ioseg_add(pa, len); 589 pa = va_arg(ap, paddr_t); 590 } 591 } else { 592 while (pa != 0) { 593 register_t len = va_arg(ap, register_t); 594 oea_iobat_add(pa, len); 595 pa = va_arg(ap, paddr_t); 596 } 597 } 598 599 va_end(ap); 600 601 /* 602 * Set up battable to map all RAM regions. 603 * This is here because mem_regions() call needs bat0 set up. 604 */ 605 mem_regions(&allmem, &availmem); 606 if (cpuvers == MPC601) { 607 for (mp = allmem; mp->size; mp++) { 608 paddr_t paddr = mp->start & 0xff800000; 609 paddr_t end = mp->start + mp->size; 610 611 do { 612 u_int ix = paddr >> 23; 613 614 battable[ix].batl = 615 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 616 battable[ix].batu = 617 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 618 paddr += (1 << 23); 619 } while (paddr < end); 620 } 621 } else { 622 for (mp = allmem; mp->size; mp++) { 623 paddr_t paddr = mp->start & 0xf0000000; 624 paddr_t end = mp->start + mp->size; 625 626 do { 627 u_int ix = paddr >> 28; 628 629 battable[ix].batl = 630 BATL(paddr, BAT_M, BAT_PP_RW); 631 battable[ix].batu = 632 BATU(paddr, BAT_BL_256M, BAT_Vs); 633 paddr += SEGMENT_LENGTH; 634 } while (paddr < end); 635 } 636 } 637 } 638 #endif /* (PPC_OEA) && !(PPC_OEA64) && !(PPC_OEA64_BRIDGE) */ 639 640 void 641 oea_install_extint(void (*handler)(void)) 642 { 643 extern int extint[], extsize[]; 644 extern int extint_call[]; 645 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 646 int omsr, msr; 647 648 #ifdef DIAGNOSTIC 649 if (offset > 0x1ffffff) 650 panic("install_extint: %p too far away (%#lx)", handler, 651 (unsigned long) offset); 652 #endif 653 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 654 : "=r" (omsr), "=r" (msr) 655 : "K" ((u_short)~PSL_EE)); 656 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 657 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 658 __syncicache((void *)extint_call, sizeof extint_call[0]); 659 __syncicache((void *)EXC_EXI, (int)extsize); 660 __asm volatile ("mtmsr %0" :: "r"(omsr)); 661 } 662 663 /* 664 * Machine dependent startup code. 665 */ 666 void 667 oea_startup(const char *model) 668 { 669 uintptr_t sz; 670 void *v; 671 vaddr_t minaddr, maxaddr; 672 char pbuf[9]; 673 u_int i; 674 675 KASSERT(curcpu() != NULL); 676 KASSERT(lwp0.l_cpu != NULL); 677 KASSERT(curcpu()->ci_intstk != 0); 678 KASSERT(curcpu()->ci_intrdepth == -1); 679 680 /* 681 * If the msgbuf is not in segment 0, allocate KVA for it and access 682 * it via mapped pages. [This prevents unneeded BAT switches.] 683 */ 684 sz = round_page(MSGBUFSIZE); 685 v = (void *) msgbuf_paddr; 686 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 687 minaddr = 0; 688 if (uvm_map(kernel_map, &minaddr, sz, 689 NULL, UVM_UNKNOWN_OFFSET, 0, 690 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 691 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 692 panic("startup: cannot allocate VM for msgbuf"); 693 v = (void *)minaddr; 694 for (i = 0; i < sz; i += PAGE_SIZE) { 695 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 696 VM_PROT_READ|VM_PROT_WRITE); 697 } 698 pmap_update(pmap_kernel()); 699 } 700 initmsgbuf(v, sz); 701 702 printf("%s%s", copyright, version); 703 if (model != NULL) 704 printf("Model: %s\n", model); 705 cpu_identify(NULL, 0); 706 707 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 708 printf("total memory = %s\n", pbuf); 709 710 /* 711 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 712 * the bufpages are allocated in case they overlap since it's not 713 * fatal if we can't allocate these. 714 */ 715 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 716 int error; 717 minaddr = 0xDEAC0000; 718 error = uvm_map(kernel_map, &minaddr, 0x30000, 719 NULL, UVM_UNKNOWN_OFFSET, 0, 720 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 721 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 722 if (error != 0 || minaddr != 0xDEAC0000) 723 printf("oea_startup: failed to allocate DEAD " 724 "ZONE: error=%d\n", error); 725 } 726 727 minaddr = 0; 728 /* 729 * Allocate a submap for exec arguments. This map effectively 730 * limits the number of processes exec'ing at any time. These 731 * submaps will be allocated after the dead zone. 732 */ 733 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 734 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 735 736 /* 737 * Allocate a submap for physio 738 */ 739 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 740 VM_PHYS_SIZE, 0, false, NULL); 741 742 #ifndef PMAP_MAP_POOLPAGE 743 /* 744 * No need to allocate an mbuf cluster submap. Mbuf clusters 745 * are allocated via the pool allocator, and we use direct-mapped 746 * pool pages. 747 */ 748 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 749 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 750 #endif 751 752 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 753 printf("avail memory = %s\n", pbuf); 754 } 755 756 /* 757 * Crash dump handling. 758 */ 759 760 void 761 oea_dumpsys(void) 762 { 763 printf("dumpsys: TBD\n"); 764 } 765 766 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 767 /* 768 * Soft networking interrupts. 769 */ 770 void 771 softnet(int pendisr) 772 { 773 #define DONETISR(bit, fn) do { \ 774 if (pendisr & (1 << bit)) \ 775 (*fn)(); \ 776 } while (0) 777 778 #include <net/netisr_dispatch.h> 779 780 #undef DONETISR 781 } 782 #endif 783 784 /* 785 * Convert kernel VA to physical address 786 */ 787 paddr_t 788 kvtop(void *addr) 789 { 790 vaddr_t va; 791 paddr_t pa; 792 uintptr_t off; 793 extern char end[]; 794 795 if (addr < (void *)end) 796 return (paddr_t)addr; 797 798 va = trunc_page((vaddr_t)addr); 799 off = (uintptr_t)addr - va; 800 801 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 802 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 803 return (paddr_t)addr; 804 } 805 806 return(pa + off); 807 } 808 809 /* 810 * Allocate vm space and mapin the I/O address 811 */ 812 void * 813 mapiodev(paddr_t pa, psize_t len) 814 { 815 paddr_t faddr; 816 vaddr_t taddr, va; 817 int off; 818 819 faddr = trunc_page(pa); 820 off = pa - faddr; 821 len = round_page(off + len); 822 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 823 824 if (va == 0) 825 return NULL; 826 827 for (; len > 0; len -= PAGE_SIZE) { 828 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 829 faddr += PAGE_SIZE; 830 taddr += PAGE_SIZE; 831 } 832 pmap_update(pmap_kernel()); 833 return (void *)(va + off); 834 } 835 836 void 837 unmapiodev(vaddr_t va, vsize_t len) 838 { 839 paddr_t faddr; 840 841 if (! va) 842 return; 843 844 faddr = trunc_page(va); 845 len = round_page(va - faddr + len); 846 847 pmap_kremove(faddr, len); 848 pmap_update(pmap_kernel()); 849 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 850 } 851 852 void 853 trap0(void *lr) 854 { 855 panic("call to null-ptr from %p", lr); 856 } 857
Indexes created Thu Oct 02 01:09:59 GMT 2025