oea_machdep.c revision 1.35.10.3
1 /* oea_machdep.c,v 1.35.10.2 2008/01/09 01:47:51 matt Exp */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "oea_machdep.c,v 1.35.10.2 2008/01/09 01:47:51 matt Exp"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/exec.h> 49 #include <sys/malloc.h> 50 #include <sys/mbuf.h> 51 #include <sys/mount.h> 52 #include <sys/msgbuf.h> 53 #include <sys/proc.h> 54 #include <sys/reboot.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/oea/cpufeat.h> 82 #include <powerpc/trap.h> 83 #include <powerpc/stdarg.h> 84 #include <powerpc/spr.h> 85 #include <powerpc/pte.h> 86 #include <powerpc/altivec.h> 87 #include <machine/powerpc.h> 88 89 char machine[] = MACHINE; /* from <machine/param.h> */ 90 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 91 92 struct vm_map *exec_map = NULL; 93 struct vm_map *mb_map = NULL; 94 struct vm_map *phys_map = NULL; 95 96 /* 97 * Global variables used here and there 98 */ 99 extern struct user *proc0paddr; 100 101 static void trap0(void *); 102 103 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 104 struct bat battable[512]; 105 106 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 107 paddr_t msgbuf_paddr; 108 109 void 110 oea_init(void (*handler)(void)) 111 { 112 extern int trapcode[], trapsize[]; 113 extern int sctrap[], scsize[]; 114 extern int alitrap[], alisize[]; 115 extern int dsitrap[], dsisize[]; 116 extern int trapstart[], trapend[]; 117 #ifdef PPC_OEA601 118 extern int dsi601trap[], dsi601size[]; 119 #endif 120 extern int decrint[], decrsize[]; 121 extern int tlbimiss[], tlbimsize[]; 122 extern int tlbdlmiss[], tlbdlmsize[]; 123 extern int tlbdsmiss[], tlbdsmsize[]; 124 #if defined(DDB) || defined(KGDB) 125 extern int ddblow[], ddbsize[]; 126 #endif 127 #ifdef IPKDB 128 extern int ipkdblow[], ipkdbsize[]; 129 #endif 130 #ifdef ALTIVEC 131 register_t msr; 132 #endif 133 uintptr_t exc; 134 #if defined(ALTIVEC) || defined(PPC_OEA) 135 register_t scratch; 136 #endif 137 unsigned int cpuvers; 138 size_t size; 139 struct cpu_info * const ci = &cpu_info[0]; 140 141 mtspr(SPR_SPRG0, ci); 142 cpuvers = mfpvr() >> 16; 143 144 /* 145 * Initialize proc0 and current pcb and pmap pointers. 146 */ 147 KASSERT(ci != NULL); 148 KASSERT(curcpu() == ci); 149 lwp0.l_cpu = ci; 150 lwp0.l_addr = proc0paddr; 151 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 152 KASSERT(lwp0.l_cpu != NULL); 153 154 curpcb = &proc0paddr->u_pcb; 155 memset(curpcb, 0, sizeof(*curpcb)); 156 #ifdef ALTIVEC 157 /* 158 * Initialize the vectors with NaNs 159 */ 160 for (scratch = 0; scratch < 32; scratch++) { 161 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 162 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 163 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 164 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 165 } 166 curpcb->pcb_vr.vscr = 0; 167 curpcb->pcb_vr.vrsave = 0; 168 #endif 169 curpm = curpcb->pcb_pm = pmap_kernel(); 170 171 /* 172 * Cause a PGM trap if we branch to 0. 173 * 174 * XXX GCC4.1 complains about memset on address zero, so 175 * don't use the builtin. 176 */ 177 #undef memset 178 memset(0, 0, 0x100); 179 180 /* 181 * Set up trap vectors. Don't assume vectors are on 0x100. 182 */ 183 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 184 switch (exc) { 185 default: 186 size = (size_t)trapsize; 187 memcpy((void *)exc, trapcode, size); 188 break; 189 #if 0 190 case EXC_EXI: 191 /* 192 * This one is (potentially) installed during autoconf 193 */ 194 break; 195 #endif 196 case EXC_SC: 197 size = (size_t)scsize; 198 memcpy((void *)EXC_SC, sctrap, size); 199 break; 200 case EXC_ALI: 201 size = (size_t)alisize; 202 memcpy((void *)EXC_ALI, alitrap, size); 203 break; 204 case EXC_DSI: 205 #ifdef PPC_OEA601 206 if (cpuvers == MPC601) { 207 size = (size_t)dsi601size; 208 memcpy((void *)EXC_DSI, dsi601trap, size); 209 break; 210 } else 211 #endif /* PPC_OEA601 */ 212 if (oeacpufeat & OEACPU_NOBAT) { 213 size = (size_t)alisize; 214 memcpy((void *)EXC_DSI, alitrap, size); 215 } else { 216 size = (size_t)dsisize; 217 memcpy((void *)EXC_DSI, dsitrap, size); 218 } 219 break; 220 case EXC_DECR: 221 size = (size_t)decrsize; 222 memcpy((void *)EXC_DECR, decrint, size); 223 break; 224 case EXC_IMISS: 225 size = (size_t)tlbimsize; 226 memcpy((void *)EXC_IMISS, tlbimiss, size); 227 break; 228 case EXC_DLMISS: 229 size = (size_t)tlbdlmsize; 230 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 231 break; 232 case EXC_DSMISS: 233 size = (size_t)tlbdsmsize; 234 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 235 break; 236 case EXC_PERF: 237 size = (size_t)trapsize; 238 memcpy((void *)EXC_PERF, trapcode, size); 239 memcpy((void *)EXC_VEC, trapcode, size); 240 break; 241 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 242 case EXC_RUNMODETRC: 243 #ifdef PPC_OEA601 244 if (cpuvers != MPC601) { 245 #endif 246 size = (size_t)trapsize; 247 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 248 break; 249 #ifdef PPC_OEA601 250 } 251 /* FALLTHROUGH */ 252 #endif 253 case EXC_PGM: 254 case EXC_TRC: 255 case EXC_BPT: 256 #if defined(DDB) || defined(KGDB) 257 size = (size_t)ddbsize; 258 memcpy((void *)exc, ddblow, size); 259 #if defined(IPKDB) 260 #error "cannot enable IPKDB with DDB or KGDB" 261 #endif 262 #else 263 size = (size_t)ipkdbsize; 264 memcpy((void *)exc, ipkdblow, size); 265 #endif 266 break; 267 #endif /* DDB || IPKDB || KGDB */ 268 } 269 #if 0 270 exc += roundup(size, 32); 271 #endif 272 } 273 274 /* 275 * Install a branch absolute to trap0 to force a panic. 276 */ 277 *(uint32_t *) 0 = 0x7c6802a6; 278 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 279 280 /* 281 * Get the cache sizes because install_extint calls __syncicache. 282 */ 283 cpu_probe_cache(); 284 285 #define MxSPR_MASK 0x7c1fffff 286 #define MFSPR_MQ 0x7c0002a6 287 #define MTSPR_MQ 0x7c0003a6 288 #define MTSPR_IBAT0L 0x7c1183a6 289 #define MTSPR_IBAT1L 0x7c1383a6 290 #define NOP 0x60000000 291 #define B 0x48000000 292 #define TLBSYNC 0x7c00046c 293 #define SYNC 0x7c0004ac 294 295 #ifdef ALTIVEC 296 #define MFSPR_VRSAVE 0x7c0042a6 297 #define MTSPR_VRSAVE 0x7c0043a6 298 299 /* 300 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 301 * not on a AltiVec capable processor. 302 */ 303 __asm volatile ( 304 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 305 "mfmsr %1; mtmsr %0; isync" 306 : "=r"(msr), "=r"(scratch) 307 : "J"(PSL_VEC)); 308 309 /* 310 * If we aren't on an AltiVec capable processor, we need to zap any of 311 * the sequences we save/restore the VRSAVE SPR into NOPs. 312 */ 313 if (scratch & PSL_VEC) { 314 cpu_altivec = 1; 315 } else { 316 int *ip = trapstart; 317 318 for (; ip < trapend; ip++) { 319 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 320 ip[0] = NOP; /* mfspr */ 321 ip[1] = NOP; /* stw */ 322 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 323 ip[-1] = NOP; /* lwz */ 324 ip[0] = NOP; /* mtspr */ 325 } 326 } 327 } 328 #endif 329 330 /* XXX It would seem like this code could be elided ifndef 601, but 331 * doing so breaks my power3 machine. 332 */ 333 /* 334 * If we aren't on a MPC601 processor, we need to zap any of the 335 * sequences we save/restore the MQ SPR into NOPs, and skip over the 336 * sequences where we zap/restore BAT registers on kernel exit/entry. 337 */ 338 if (cpuvers != MPC601) { 339 int *ip = trapstart; 340 341 for (; ip < trapend; ip++) { 342 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 343 ip[0] = NOP; /* mfspr */ 344 ip[1] = NOP; /* stw */ 345 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 346 ip[-1] = NOP; /* lwz */ 347 ip[0] = NOP; /* mtspr */ 348 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 349 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 350 ip[-1] = B | 0x14; /* li */ 351 else 352 ip[-4] = B | 0x24; /* lis */ 353 } 354 } 355 } 356 357 /* 358 * Sync the changed instructions. 359 */ 360 __syncicache((void *) trapstart, 361 (uintptr_t) trapend - (uintptr_t) trapstart); 362 #ifdef PPC_OEA601 363 364 /* 365 * If we are on a MPC601 processor, we need to zap any tlbsync 366 * instructions into sync. This differs from the above in 367 * examing all kernel text, as opposed to just the exception handling. 368 * We sync the icache on every instruction found since there are 369 * only very few of them. 370 */ 371 if (cpuvers == MPC601) { 372 extern int kernel_text[], etext[]; 373 int *ip; 374 375 for (ip = kernel_text; ip < etext; ip++) 376 if (*ip == TLBSYNC) { 377 *ip = SYNC; 378 __syncicache(ip, sizeof(*ip)); 379 } 380 } 381 #endif /* PPC_OEA601 */ 382 383 /* 384 * Configure a PSL user mask matching this processor. 385 */ 386 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 387 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 388 #ifdef PPC_OEA601 389 if (cpuvers == MPC601) { 390 cpu_psluserset &= PSL_601_MASK; 391 cpu_pslusermod &= PSL_601_MASK; 392 } 393 #endif 394 #ifdef ALTIVEC 395 if (cpu_altivec) 396 cpu_pslusermod |= PSL_VEC; 397 #endif 398 399 /* 400 * external interrupt handler install 401 */ 402 if (handler) 403 oea_install_extint(handler); 404 405 __syncicache(0, EXC_LAST + 0x100); 406 407 /* 408 * Now enable translation (and machine checks/recoverable interrupts). 409 */ 410 #ifdef PPC_OEA 411 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 412 : "=r"(scratch) 413 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 414 #endif 415 416 KASSERT(curcpu() == ci); 417 } 418 419 #ifdef PPC_OEA601 420 void 421 mpc601_ioseg_add(paddr_t pa, register_t len) 422 { 423 const u_int i = pa >> ADDR_SR_SHFT; 424 425 if (len != BAT_BL_256M) 426 panic("mpc601_ioseg_add: len != 256M"); 427 428 /* 429 * Translate into an I/O segment, load it, and stash away for use 430 * in pmap_bootstrap(). 431 */ 432 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 433 __asm volatile ("mtsrin %0,%1" 434 :: "r"(iosrtable[i]), 435 "r"(pa)); 436 } 437 #endif /* PPC_OEA601 */ 438 439 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 440 void 441 oea_iobat_add(paddr_t pa, register_t len) 442 { 443 static int n = 1; 444 const u_int i = pa >> 28; 445 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 446 battable[i].batu = BATU(pa, len, BAT_Vs); 447 448 /* 449 * Let's start loading the BAT registers. 450 */ 451 switch (n) { 452 case 1: 453 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 454 :: "r"(battable[i].batl), 455 "r"(battable[i].batu)); 456 n = 2; 457 break; 458 case 2: 459 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 460 :: "r"(battable[i].batl), 461 "r"(battable[i].batu)); 462 n = 3; 463 break; 464 case 3: 465 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 466 :: "r"(battable[i].batl), 467 "r"(battable[i].batu)); 468 n = 4; 469 break; 470 default: 471 break; 472 } 473 } 474 475 void 476 oea_iobat_remove(paddr_t pa) 477 { 478 register_t batu; 479 int i, n; 480 481 n = pa >> ADDR_SR_SHFT; 482 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 483 !BAT_VALID_P(battable[n].batu, PSL_PR)) 484 return; 485 battable[n].batl = 0; 486 battable[n].batu = 0; 487 #define BAT_RESET(n) \ 488 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 489 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 490 491 for (i=1 ; i<4 ; i++) { 492 switch (i) { 493 case 1: 494 BATU_GET(1, batu); 495 if (BAT_VA_MATCH_P(batu, pa) && 496 BAT_VALID_P(batu, PSL_PR)) 497 BAT_RESET(1); 498 break; 499 case 2: 500 BATU_GET(2, batu); 501 if (BAT_VA_MATCH_P(batu, pa) && 502 BAT_VALID_P(batu, PSL_PR)) 503 BAT_RESET(2); 504 break; 505 case 3: 506 BATU_GET(3, batu); 507 if (BAT_VA_MATCH_P(batu, pa) && 508 BAT_VALID_P(batu, PSL_PR)) 509 BAT_RESET(3); 510 break; 511 default: 512 break; 513 } 514 } 515 } 516 517 void 518 oea_batinit(paddr_t pa, ...) 519 { 520 struct mem_region *allmem, *availmem, *mp; 521 unsigned int cpuvers; 522 register_t msr = mfmsr(); 523 va_list ap; 524 525 cpuvers = mfpvr() >> 16; 526 527 /* 528 * Initialize BAT registers to unmapped to not generate 529 * overlapping mappings below. 530 * 531 * The 601's implementation differs in the Valid bit being situated 532 * in the lower BAT register, and in being a unified BAT only whose 533 * four entries are accessed through the IBAT[0-3] SPRs. 534 * 535 * Also, while the 601 does distinguish between supervisor/user 536 * protection keys, it does _not_ distinguish between validity in 537 * supervisor/user mode. 538 */ 539 if ((msr & (PSL_IR|PSL_DR)) == 0) { 540 #ifdef PPC_OEA601 541 if (cpuvers == MPC601) { 542 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 543 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 544 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 545 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 546 } else 547 #endif /* PPC_OEA601 */ 548 { 549 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 550 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 551 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 552 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 553 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 554 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 555 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 556 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 557 } 558 } 559 560 /* 561 * Set up BAT to map physical memory 562 */ 563 #ifdef PPC_OEA601 564 if (cpuvers == MPC601) { 565 int i; 566 567 /* 568 * Set up battable to map the lowest 256 MB area. 569 * Map the lowest 32 MB area via BAT[0-3]; 570 * BAT[01] are fixed, BAT[23] are floating. 571 */ 572 for (i = 0; i < 32; i++) { 573 battable[i].batl = BATL601(i << 23, 574 BAT601_BSM_8M, BAT601_V); 575 battable[i].batu = BATU601(i << 23, 576 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 577 } 578 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 579 :: "r"(battable[0x00000000 >> 23].batl), 580 "r"(battable[0x00000000 >> 23].batu)); 581 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 582 :: "r"(battable[0x00800000 >> 23].batl), 583 "r"(battable[0x00800000 >> 23].batu)); 584 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 585 :: "r"(battable[0x01000000 >> 23].batl), 586 "r"(battable[0x01000000 >> 23].batu)); 587 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 588 :: "r"(battable[0x01800000 >> 23].batl), 589 "r"(battable[0x01800000 >> 23].batu)); 590 } else 591 #endif /* PPC_OEA601 */ 592 { 593 /* 594 * Set up BAT0 to only map the lowest 256 MB area 595 */ 596 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 597 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 598 599 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 600 "mtdbatl 0,%0; mtdbatu 0,%1;" 601 :: "r"(battable[0].batl), "r"(battable[0].batu)); 602 } 603 604 /* 605 * Now setup other fixed bat registers 606 * 607 * Note that we still run in real mode, and the BAT 608 * registers were cleared above. 609 */ 610 611 va_start(ap, pa); 612 613 /* 614 * Add any I/O BATs specificed; 615 * use I/O segments on the BAT-starved 601. 616 */ 617 #ifdef PPC_OEA601 618 if (cpuvers == MPC601) { 619 while (pa != 0) { 620 register_t len = va_arg(ap, register_t); 621 mpc601_ioseg_add(pa, len); 622 pa = va_arg(ap, paddr_t); 623 } 624 } else 625 #endif 626 { 627 while (pa != 0) { 628 register_t len = va_arg(ap, register_t); 629 oea_iobat_add(pa, len); 630 pa = va_arg(ap, paddr_t); 631 } 632 } 633 634 va_end(ap); 635 636 /* 637 * Set up battable to map all RAM regions. 638 * This is here because mem_regions() call needs bat0 set up. 639 */ 640 mem_regions(&allmem, &availmem); 641 #ifdef PPC_OEA601 642 if (cpuvers == MPC601) { 643 for (mp = allmem; mp->size; mp++) { 644 paddr_t paddr = mp->start & 0xff800000; 645 paddr_t end = mp->start + mp->size; 646 647 do { 648 u_int ix = paddr >> 23; 649 650 battable[ix].batl = 651 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 652 battable[ix].batu = 653 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 654 paddr += (1 << 23); 655 } while (paddr < end); 656 } 657 } else 658 #endif 659 { 660 for (mp = allmem; mp->size; mp++) { 661 paddr_t paddr = mp->start & 0xf0000000; 662 paddr_t end = mp->start + mp->size; 663 664 do { 665 u_int ix = paddr >> 28; 666 667 battable[ix].batl = 668 BATL(paddr, BAT_M, BAT_PP_RW); 669 battable[ix].batu = 670 BATU(paddr, BAT_BL_256M, BAT_Vs); 671 paddr += SEGMENT_LENGTH; 672 } while (paddr < end); 673 } 674 } 675 } 676 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 677 678 void 679 oea_install_extint(void (*handler)(void)) 680 { 681 extern int extint[], extsize[]; 682 extern int extint_call[]; 683 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 684 int omsr, msr; 685 686 #ifdef DIAGNOSTIC 687 if (offset > 0x1ffffff) 688 panic("install_extint: %p too far away (%#lx)", handler, 689 (unsigned long) offset); 690 #endif 691 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 692 : "=r" (omsr), "=r" (msr) 693 : "K" ((u_short)~PSL_EE)); 694 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 695 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 696 __syncicache((void *)extint_call, sizeof extint_call[0]); 697 __syncicache((void *)EXC_EXI, (int)extsize); 698 __asm volatile ("mtmsr %0" :: "r"(omsr)); 699 } 700 701 /* 702 * Machine dependent startup code. 703 */ 704 void 705 oea_startup(const char *model) 706 { 707 uintptr_t sz; 708 void *v; 709 vaddr_t minaddr, maxaddr; 710 char pbuf[9]; 711 u_int i; 712 713 KASSERT(curcpu() != NULL); 714 KASSERT(lwp0.l_cpu != NULL); 715 KASSERT(curcpu()->ci_intstk != 0); 716 KASSERT(curcpu()->ci_intrdepth == -1); 717 718 /* 719 * If the msgbuf is not in segment 0, allocate KVA for it and access 720 * it via mapped pages. [This prevents unneeded BAT switches.] 721 */ 722 sz = round_page(MSGBUFSIZE); 723 v = (void *) msgbuf_paddr; 724 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 725 minaddr = 0; 726 if (uvm_map(kernel_map, &minaddr, sz, 727 NULL, UVM_UNKNOWN_OFFSET, 0, 728 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 729 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 730 panic("startup: cannot allocate VM for msgbuf"); 731 v = (void *)minaddr; 732 for (i = 0; i < sz; i += PAGE_SIZE) { 733 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 734 VM_PROT_READ|VM_PROT_WRITE); 735 } 736 pmap_update(pmap_kernel()); 737 } 738 initmsgbuf(v, sz); 739 740 printf("%s%s", copyright, version); 741 if (model != NULL) 742 printf("Model: %s\n", model); 743 cpu_identify(NULL, 0); 744 745 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 746 printf("total memory = %s\n", pbuf); 747 748 /* 749 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 750 * the bufpages are allocated in case they overlap since it's not 751 * fatal if we can't allocate these. 752 */ 753 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 754 int error; 755 minaddr = 0xDEAC0000; 756 error = uvm_map(kernel_map, &minaddr, 0x30000, 757 NULL, UVM_UNKNOWN_OFFSET, 0, 758 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 759 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 760 if (error != 0 || minaddr != 0xDEAC0000) 761 printf("oea_startup: failed to allocate DEAD " 762 "ZONE: error=%d\n", error); 763 } 764 765 minaddr = 0; 766 /* 767 * Allocate a submap for exec arguments. This map effectively 768 * limits the number of processes exec'ing at any time. These 769 * submaps will be allocated after the dead zone. 770 */ 771 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 772 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 773 774 /* 775 * Allocate a submap for physio 776 */ 777 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 778 VM_PHYS_SIZE, 0, false, NULL); 779 780 #ifndef PMAP_MAP_POOLPAGE 781 /* 782 * No need to allocate an mbuf cluster submap. Mbuf clusters 783 * are allocated via the pool allocator, and we use direct-mapped 784 * pool pages. 785 */ 786 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 787 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 788 #endif 789 790 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 791 printf("avail memory = %s\n", pbuf); 792 } 793 794 /* 795 * Crash dump handling. 796 */ 797 798 void 799 oea_dumpsys(void) 800 { 801 printf("dumpsys: TBD\n"); 802 } 803 804 /* 805 * Convert kernel VA to physical address 806 */ 807 paddr_t 808 kvtop(void *addr) 809 { 810 vaddr_t va; 811 paddr_t pa; 812 uintptr_t off; 813 extern char end[]; 814 815 if (addr < (void *)end) 816 return (paddr_t)addr; 817 818 va = trunc_page((vaddr_t)addr); 819 off = (uintptr_t)addr - va; 820 821 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 822 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 823 return (paddr_t)addr; 824 } 825 826 return(pa + off); 827 } 828 829 /* 830 * Allocate vm space and mapin the I/O address 831 */ 832 void * 833 mapiodev(paddr_t pa, psize_t len) 834 { 835 paddr_t faddr; 836 vaddr_t taddr, va; 837 int off; 838 839 faddr = trunc_page(pa); 840 off = pa - faddr; 841 len = round_page(off + len); 842 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 843 844 if (va == 0) 845 return NULL; 846 847 for (; len > 0; len -= PAGE_SIZE) { 848 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 849 faddr += PAGE_SIZE; 850 taddr += PAGE_SIZE; 851 } 852 pmap_update(pmap_kernel()); 853 return (void *)(va + off); 854 } 855 856 void 857 unmapiodev(vaddr_t va, vsize_t len) 858 { 859 paddr_t faddr; 860 861 if (! va) 862 return; 863 864 faddr = trunc_page(va); 865 len = round_page(va - faddr + len); 866 867 pmap_kremove(faddr, len); 868 pmap_update(pmap_kernel()); 869 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 870 } 871 872 void 873 trap0(void *lr) 874 { 875 panic("call to null-ptr from %p", lr); 876 } 877
Indexes created Mon Oct 20 11:09:49 GMT 2025