oea_machdep.c revision 1.38
1 /* $NetBSD: oea_machdep.c,v 1.38 2008/01/09 21:09:21 garbled Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.38 2008/01/09 21:09:21 garbled Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/syscallargs.h> 55 #include <sys/syslog.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/user.h> 59 #include <sys/boot_flag.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/netisr.h> 64 65 #ifdef DDB 66 #include <machine/db_machdep.h> 67 #include <ddb/db_extern.h> 68 #endif 69 70 #ifdef KGDB 71 #include <sys/kgdb.h> 72 #endif 73 74 #ifdef IPKDB 75 #include <ipkdb/ipkdb.h> 76 #endif 77 78 #include <powerpc/oea/bat.h> 79 #include <powerpc/oea/sr_601.h> 80 #include <powerpc/trap.h> 81 #include <powerpc/stdarg.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/pte.h> 84 #include <powerpc/altivec.h> 85 #include <machine/powerpc.h> 86 87 char machine[] = MACHINE; /* from <machine/param.h> */ 88 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 89 90 struct vm_map *exec_map = NULL; 91 struct vm_map *mb_map = NULL; 92 struct vm_map *phys_map = NULL; 93 94 /* 95 * Global variables used here and there 96 */ 97 extern struct user *proc0paddr; 98 99 static void trap0(void *); 100 101 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 102 struct bat battable[512]; 103 104 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 105 paddr_t msgbuf_paddr; 106 107 void 108 oea_init(void (*handler)(void)) 109 { 110 extern int trapstart[], trapend[]; 111 extern int trapcode[], trapsize[]; 112 extern int sctrap[], scsize[]; 113 extern int alitrap[], alisize[]; 114 extern int dsitrap[], dsisize[]; 115 extern int dsi601trap[], dsi601size[]; 116 extern int decrint[], decrsize[]; 117 extern int tlbimiss[], tlbimsize[]; 118 extern int tlbdlmiss[], tlbdlmsize[]; 119 extern int tlbdsmiss[], tlbdsmsize[]; 120 #if defined(DDB) || defined(KGDB) 121 extern int ddblow[], ddbsize[]; 122 #endif 123 #ifdef IPKDB 124 extern int ipkdblow[], ipkdbsize[]; 125 #endif 126 #ifdef ALTIVEC 127 register_t msr; 128 #endif 129 uintptr_t exc; 130 #if defined(ALTIVEC) || defined(PPC_OEA) 131 register_t scratch; 132 #endif 133 unsigned int cpuvers; 134 size_t size; 135 struct cpu_info * const ci = &cpu_info[0]; 136 137 mtspr(SPR_SPRG0, ci); 138 cpuvers = mfpvr() >> 16; 139 140 /* 141 * Initialize proc0 and current pcb and pmap pointers. 142 */ 143 KASSERT(ci != NULL); 144 KASSERT(curcpu() == ci); 145 lwp0.l_cpu = ci; 146 lwp0.l_addr = proc0paddr; 147 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 148 KASSERT(lwp0.l_cpu != NULL); 149 150 curpcb = &proc0paddr->u_pcb; 151 memset(curpcb, 0, sizeof(*curpcb)); 152 #ifdef ALTIVEC 153 /* 154 * Initialize the vectors with NaNs 155 */ 156 for (scratch = 0; scratch < 32; scratch++) { 157 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 158 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 159 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 160 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 161 } 162 curpcb->pcb_vr.vscr = 0; 163 curpcb->pcb_vr.vrsave = 0; 164 #endif 165 curpm = curpcb->pcb_pm = pmap_kernel(); 166 167 /* 168 * Cause a PGM trap if we branch to 0. 169 * 170 * XXX GCC4.1 complains about memset on address zero, so 171 * don't use the builtin. 172 */ 173 #undef memset 174 memset(0, 0, 0x100); 175 176 /* 177 * Set up trap vectors. Don't assume vectors are on 0x100. 178 */ 179 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 180 switch (exc) { 181 default: 182 size = (size_t)trapsize; 183 memcpy((void *)exc, trapcode, size); 184 break; 185 #if 0 186 case EXC_EXI: 187 /* 188 * This one is (potentially) installed during autoconf 189 */ 190 break; 191 #endif 192 case EXC_SC: 193 size = (size_t)scsize; 194 memcpy((void *)EXC_SC, sctrap, size); 195 break; 196 case EXC_ALI: 197 size = (size_t)alisize; 198 memcpy((void *)EXC_ALI, alitrap, size); 199 break; 200 case EXC_DSI: 201 if (cpuvers == MPC601) { 202 size = (size_t)dsi601size; 203 memcpy((void *)EXC_DSI, dsi601trap, size); 204 } else { 205 size = (size_t)dsisize; 206 memcpy((void *)EXC_DSI, dsitrap, size); 207 } 208 break; 209 case EXC_DECR: 210 size = (size_t)decrsize; 211 memcpy((void *)EXC_DECR, decrint, size); 212 break; 213 case EXC_IMISS: 214 size = (size_t)tlbimsize; 215 memcpy((void *)EXC_IMISS, tlbimiss, size); 216 break; 217 case EXC_DLMISS: 218 size = (size_t)tlbdlmsize; 219 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 220 break; 221 case EXC_DSMISS: 222 size = (size_t)tlbdsmsize; 223 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 224 break; 225 case EXC_PERF: 226 size = (size_t)trapsize; 227 memcpy((void *)EXC_PERF, trapcode, size); 228 memcpy((void *)EXC_VEC, trapcode, size); 229 break; 230 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 231 case EXC_RUNMODETRC: 232 if (cpuvers != MPC601) { 233 size = (size_t)trapsize; 234 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 235 break; 236 } 237 /* FALLTHROUGH */ 238 case EXC_PGM: 239 case EXC_TRC: 240 case EXC_BPT: 241 #if defined(DDB) || defined(KGDB) 242 size = (size_t)ddbsize; 243 memcpy((void *)exc, ddblow, size); 244 #if defined(IPKDB) 245 #error "cannot enable IPKDB with DDB or KGDB" 246 #endif 247 #else 248 size = (size_t)ipkdbsize; 249 memcpy((void *)exc, ipkdblow, size); 250 #endif 251 break; 252 #endif /* DDB || IPKDB || KGDB */ 253 } 254 #if 0 255 exc += roundup(size, 32); 256 #endif 257 } 258 259 /* 260 * Install a branch absolute to trap0 to force a panic. 261 */ 262 *(uint32_t *) 0 = 0x7c6802a6; 263 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 264 265 /* 266 * Get the cache sizes because install_extint calls __syncicache. 267 */ 268 cpu_probe_cache(); 269 270 #define MxSPR_MASK 0x7c1fffff 271 #define MFSPR_MQ 0x7c0002a6 272 #define MTSPR_MQ 0x7c0003a6 273 #define MTSPR_IBAT0L 0x7c1183a6 274 #define MTSPR_IBAT1L 0x7c1383a6 275 #define NOP 0x60000000 276 #define B 0x48000000 277 #define TLBSYNC 0x7c00046c 278 #define SYNC 0x7c0004ac 279 280 #ifdef ALTIVEC 281 #define MFSPR_VRSAVE 0x7c0042a6 282 #define MTSPR_VRSAVE 0x7c0043a6 283 284 /* 285 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 286 * not on a AltiVec capable processor. 287 */ 288 __asm volatile ( 289 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 290 "mfmsr %1; mtmsr %0; isync" 291 : "=r"(msr), "=r"(scratch) 292 : "J"(PSL_VEC)); 293 294 /* 295 * If we aren't on an AltiVec capable processor, we need to zap any of 296 * the sequences we save/restore the VRSAVE SPR into NOPs. 297 */ 298 if (scratch & PSL_VEC) { 299 cpu_altivec = 1; 300 } else { 301 int *ip = trapstart; 302 303 for (; ip < trapend; ip++) { 304 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 305 ip[0] = NOP; /* mfspr */ 306 ip[1] = NOP; /* stw */ 307 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 308 ip[-1] = NOP; /* lwz */ 309 ip[0] = NOP; /* mtspr */ 310 } 311 } 312 } 313 #endif 314 315 /* 316 * If we aren't on a MPC601 processor, we need to zap any of the 317 * sequences we save/restore the MQ SPR into NOPs, and skip over the 318 * sequences where we zap/restore BAT registers on kernel exit/entry. 319 */ 320 if (cpuvers != MPC601) { 321 int *ip = trapstart; 322 323 for (; ip < trapend; ip++) { 324 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 325 ip[0] = NOP; /* mfspr */ 326 ip[1] = NOP; /* stw */ 327 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 328 ip[-1] = NOP; /* lwz */ 329 ip[0] = NOP; /* mtspr */ 330 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 331 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 332 ip[-1] = B | 0x14; /* li */ 333 else 334 ip[-4] = B | 0x24; /* lis */ 335 } 336 } 337 } 338 339 /* 340 * Sync the changed instructions. 341 */ 342 __syncicache((void *) trapstart, 343 (uintptr_t) trapend - (uintptr_t) trapstart); 344 345 /* 346 * If we are on a MPC601 processor, we need to zap any tlbsync 347 * instructions into sync. This differs from the above in 348 * examing all kernel text, as opposed to just the exception handling. 349 * We sync the icache on every instruction found since there are 350 * only very few of them. 351 */ 352 if (cpuvers == MPC601) { 353 extern int kernel_text[], etext[]; 354 int *ip; 355 356 for (ip = kernel_text; ip < etext; ip++) 357 if (*ip == TLBSYNC) { 358 *ip = SYNC; 359 __syncicache(ip, sizeof(*ip)); 360 } 361 } 362 363 /* 364 * Configure a PSL user mask matching this processor. 365 */ 366 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 367 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 368 if (cpuvers == MPC601) { 369 cpu_psluserset &= PSL_601_MASK; 370 cpu_pslusermod &= PSL_601_MASK; 371 } 372 #ifdef ALTIVEC 373 if (cpu_altivec) 374 cpu_pslusermod |= PSL_VEC; 375 #endif 376 377 /* 378 * external interrupt handler install 379 */ 380 if (handler) 381 oea_install_extint(handler); 382 383 __syncicache(0, EXC_LAST + 0x100); 384 385 /* 386 * Now enable translation (and machine checks/recoverable interrupts). 387 */ 388 #ifdef PPC_OEA 389 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 390 : "=r"(scratch) 391 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 392 #endif 393 394 KASSERT(curcpu() == ci); 395 } 396 397 void 398 mpc601_ioseg_add(paddr_t pa, register_t len) 399 { 400 const u_int i = pa >> ADDR_SR_SHFT; 401 402 if (len != BAT_BL_256M) 403 panic("mpc601_ioseg_add: len != 256M"); 404 405 /* 406 * Translate into an I/O segment, load it, and stash away for use 407 * in pmap_bootstrap(). 408 */ 409 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 410 __asm volatile ("mtsrin %0,%1" 411 :: "r"(iosrtable[i]), 412 "r"(pa)); 413 } 414 415 416 #if defined (PPC_OEA) && !defined (PPC_OEA64) && !defined (PPC_OEA64_BRIDGE) 417 void 418 oea_iobat_add(paddr_t pa, register_t len) 419 { 420 static int n = 1; 421 const u_int i = pa >> 28; 422 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 423 battable[i].batu = BATU(pa, len, BAT_Vs); 424 425 /* 426 * Let's start loading the BAT registers. 427 */ 428 switch (n) { 429 case 1: 430 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 431 :: "r"(battable[i].batl), 432 "r"(battable[i].batu)); 433 n = 2; 434 break; 435 case 2: 436 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 437 :: "r"(battable[i].batl), 438 "r"(battable[i].batu)); 439 n = 3; 440 break; 441 case 3: 442 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 443 :: "r"(battable[i].batl), 444 "r"(battable[i].batu)); 445 n = 4; 446 break; 447 default: 448 break; 449 } 450 } 451 452 void 453 oea_iobat_remove(paddr_t pa) 454 { 455 register_t batu; 456 int i, n; 457 458 n = pa >> ADDR_SR_SHFT; 459 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 460 !BAT_VALID_P(battable[n].batu, PSL_PR)) 461 return; 462 battable[n].batl = 0; 463 battable[n].batu = 0; 464 #define BAT_RESET(n) \ 465 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 466 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 467 468 for (i=1 ; i<4 ; i++) { 469 switch (i) { 470 case 1: 471 BATU_GET(1, batu); 472 if (BAT_VA_MATCH_P(batu, pa) && 473 BAT_VALID_P(batu, PSL_PR)) 474 BAT_RESET(1); 475 break; 476 case 2: 477 BATU_GET(2, batu); 478 if (BAT_VA_MATCH_P(batu, pa) && 479 BAT_VALID_P(batu, PSL_PR)) 480 BAT_RESET(2); 481 break; 482 case 3: 483 BATU_GET(3, batu); 484 if (BAT_VA_MATCH_P(batu, pa) && 485 BAT_VALID_P(batu, PSL_PR)) 486 BAT_RESET(3); 487 break; 488 default: 489 break; 490 } 491 } 492 } 493 494 void 495 oea_batinit(paddr_t pa, ...) 496 { 497 struct mem_region *allmem, *availmem, *mp; 498 int i; 499 unsigned int cpuvers; 500 register_t msr = mfmsr(); 501 va_list ap; 502 503 cpuvers = mfpvr() >> 16; 504 505 /* 506 * Initialize BAT registers to unmapped to not generate 507 * overlapping mappings below. 508 * 509 * The 601's implementation differs in the Valid bit being situated 510 * in the lower BAT register, and in being a unified BAT only whose 511 * four entries are accessed through the IBAT[0-3] SPRs. 512 * 513 * Also, while the 601 does distinguish between supervisor/user 514 * protection keys, it does _not_ distinguish between validity in 515 * supervisor/user mode. 516 */ 517 if ((msr & (PSL_IR|PSL_DR)) == 0) { 518 if (cpuvers == MPC601) { 519 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 520 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 521 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 522 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 523 } else { 524 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 525 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 526 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 527 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 528 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 529 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 530 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 531 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 532 } 533 } 534 535 /* 536 * Set up BAT to map physical memory 537 */ 538 if (cpuvers == MPC601) { 539 /* 540 * Set up battable to map the lowest 256 MB area. 541 * Map the lowest 32 MB area via BAT[0-3]; 542 * BAT[01] are fixed, BAT[23] are floating. 543 */ 544 for (i = 0; i < 32; i++) { 545 battable[i].batl = BATL601(i << 23, 546 BAT601_BSM_8M, BAT601_V); 547 battable[i].batu = BATU601(i << 23, 548 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 549 } 550 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 551 :: "r"(battable[0x00000000 >> 23].batl), 552 "r"(battable[0x00000000 >> 23].batu)); 553 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 554 :: "r"(battable[0x00800000 >> 23].batl), 555 "r"(battable[0x00800000 >> 23].batu)); 556 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 557 :: "r"(battable[0x01000000 >> 23].batl), 558 "r"(battable[0x01000000 >> 23].batu)); 559 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 560 :: "r"(battable[0x01800000 >> 23].batl), 561 "r"(battable[0x01800000 >> 23].batu)); 562 } else { 563 /* 564 * Set up BAT0 to only map the lowest 256 MB area 565 */ 566 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 567 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 568 569 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 570 "mtdbatl 0,%0; mtdbatu 0,%1;" 571 :: "r"(battable[0].batl), "r"(battable[0].batu)); 572 } 573 574 /* 575 * Now setup other fixed bat registers 576 * 577 * Note that we still run in real mode, and the BAT 578 * registers were cleared above. 579 */ 580 581 va_start(ap, pa); 582 583 /* 584 * Add any I/O BATs specificed; 585 * use I/O segments on the BAT-starved 601. 586 */ 587 if (cpuvers == MPC601) { 588 while (pa != 0) { 589 register_t len = va_arg(ap, register_t); 590 mpc601_ioseg_add(pa, len); 591 pa = va_arg(ap, paddr_t); 592 } 593 } else { 594 while (pa != 0) { 595 register_t len = va_arg(ap, register_t); 596 oea_iobat_add(pa, len); 597 pa = va_arg(ap, paddr_t); 598 } 599 } 600 601 va_end(ap); 602 603 /* 604 * Set up battable to map all RAM regions. 605 * This is here because mem_regions() call needs bat0 set up. 606 */ 607 mem_regions(&allmem, &availmem); 608 if (cpuvers == MPC601) { 609 for (mp = allmem; mp->size; mp++) { 610 paddr_t paddr = mp->start & 0xff800000; 611 paddr_t end = mp->start + mp->size; 612 613 do { 614 u_int ix = paddr >> 23; 615 616 battable[ix].batl = 617 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 618 battable[ix].batu = 619 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 620 paddr += (1 << 23); 621 } while (paddr < end); 622 } 623 } else { 624 for (mp = allmem; mp->size; mp++) { 625 paddr_t paddr = mp->start & 0xf0000000; 626 paddr_t end = mp->start + mp->size; 627 628 do { 629 u_int ix = paddr >> 28; 630 631 battable[ix].batl = 632 BATL(paddr, BAT_M, BAT_PP_RW); 633 battable[ix].batu = 634 BATU(paddr, BAT_BL_256M, BAT_Vs); 635 paddr += SEGMENT_LENGTH; 636 } while (paddr < end); 637 } 638 } 639 } 640 #endif /* (PPC_OEA) && !(PPC_OEA64) && !(PPC_OEA64_BRIDGE) */ 641 642 void 643 oea_install_extint(void (*handler)(void)) 644 { 645 extern int extint[], extsize[]; 646 extern int extint_call[]; 647 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 648 int omsr, msr; 649 650 #ifdef DIAGNOSTIC 651 if (offset > 0x1ffffff) 652 panic("install_extint: %p too far away (%#lx)", handler, 653 (unsigned long) offset); 654 #endif 655 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 656 : "=r" (omsr), "=r" (msr) 657 : "K" ((u_short)~PSL_EE)); 658 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 659 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 660 __syncicache((void *)extint_call, sizeof extint_call[0]); 661 __syncicache((void *)EXC_EXI, (int)extsize); 662 __asm volatile ("mtmsr %0" :: "r"(omsr)); 663 } 664 665 /* 666 * Machine dependent startup code. 667 */ 668 void 669 oea_startup(const char *model) 670 { 671 uintptr_t sz; 672 void *v; 673 vaddr_t minaddr, maxaddr; 674 char pbuf[9]; 675 u_int i; 676 677 KASSERT(curcpu() != NULL); 678 KASSERT(lwp0.l_cpu != NULL); 679 KASSERT(curcpu()->ci_intstk != 0); 680 KASSERT(curcpu()->ci_intrdepth == -1); 681 682 /* 683 * If the msgbuf is not in segment 0, allocate KVA for it and access 684 * it via mapped pages. [This prevents unneeded BAT switches.] 685 */ 686 sz = round_page(MSGBUFSIZE); 687 v = (void *) msgbuf_paddr; 688 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 689 minaddr = 0; 690 if (uvm_map(kernel_map, &minaddr, sz, 691 NULL, UVM_UNKNOWN_OFFSET, 0, 692 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 693 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 694 panic("startup: cannot allocate VM for msgbuf"); 695 v = (void *)minaddr; 696 for (i = 0; i < sz; i += PAGE_SIZE) { 697 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 698 VM_PROT_READ|VM_PROT_WRITE); 699 } 700 pmap_update(pmap_kernel()); 701 } 702 initmsgbuf(v, sz); 703 704 printf("%s%s", copyright, version); 705 if (model != NULL) 706 printf("Model: %s\n", model); 707 cpu_identify(NULL, 0); 708 709 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 710 printf("total memory = %s\n", pbuf); 711 712 /* 713 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 714 * the bufpages are allocated in case they overlap since it's not 715 * fatal if we can't allocate these. 716 */ 717 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 718 int error; 719 minaddr = 0xDEAC0000; 720 error = uvm_map(kernel_map, &minaddr, 0x30000, 721 NULL, UVM_UNKNOWN_OFFSET, 0, 722 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 723 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 724 if (error != 0 || minaddr != 0xDEAC0000) 725 printf("oea_startup: failed to allocate DEAD " 726 "ZONE: error=%d\n", error); 727 } 728 729 minaddr = 0; 730 /* 731 * Allocate a submap for exec arguments. This map effectively 732 * limits the number of processes exec'ing at any time. These 733 * submaps will be allocated after the dead zone. 734 */ 735 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 736 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 737 738 /* 739 * Allocate a submap for physio 740 */ 741 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 742 VM_PHYS_SIZE, 0, false, NULL); 743 744 #ifndef PMAP_MAP_POOLPAGE 745 /* 746 * No need to allocate an mbuf cluster submap. Mbuf clusters 747 * are allocated via the pool allocator, and we use direct-mapped 748 * pool pages. 749 */ 750 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 751 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 752 #endif 753 754 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 755 printf("avail memory = %s\n", pbuf); 756 } 757 758 /* 759 * Crash dump handling. 760 */ 761 762 void 763 oea_dumpsys(void) 764 { 765 printf("dumpsys: TBD\n"); 766 } 767 768 /* 769 * Convert kernel VA to physical address 770 */ 771 paddr_t 772 kvtop(void *addr) 773 { 774 vaddr_t va; 775 paddr_t pa; 776 uintptr_t off; 777 extern char end[]; 778 779 if (addr < (void *)end) 780 return (paddr_t)addr; 781 782 va = trunc_page((vaddr_t)addr); 783 off = (uintptr_t)addr - va; 784 785 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 786 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 787 return (paddr_t)addr; 788 } 789 790 return(pa + off); 791 } 792 793 /* 794 * Allocate vm space and mapin the I/O address 795 */ 796 void * 797 mapiodev(paddr_t pa, psize_t len) 798 { 799 paddr_t faddr; 800 vaddr_t taddr, va; 801 int off; 802 803 faddr = trunc_page(pa); 804 off = pa - faddr; 805 len = round_page(off + len); 806 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 807 808 if (va == 0) 809 return NULL; 810 811 for (; len > 0; len -= PAGE_SIZE) { 812 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 813 faddr += PAGE_SIZE; 814 taddr += PAGE_SIZE; 815 } 816 pmap_update(pmap_kernel()); 817 return (void *)(va + off); 818 } 819 820 void 821 unmapiodev(vaddr_t va, vsize_t len) 822 { 823 paddr_t faddr; 824 825 if (! va) 826 return; 827 828 faddr = trunc_page(va); 829 len = round_page(va - faddr + len); 830 831 pmap_kremove(faddr, len); 832 pmap_update(pmap_kernel()); 833 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 834 } 835 836 void 837 trap0(void *lr) 838 { 839 panic("call to null-ptr from %p", lr); 840 } 841
Indexes created Wed Oct 01 15:09:59 GMT 2025