oea_machdep.c revision 1.40
1 /* $NetBSD: oea_machdep.c,v 1.40 2008/02/05 22:31:49 garbled Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.40 2008/02/05 22:31:49 garbled Exp $"); 37 38 #include "opt_compat_netbsd.h" 39 #include "opt_ddb.h" 40 #include "opt_kgdb.h" 41 #include "opt_ipkdb.h" 42 #include "opt_multiprocessor.h" 43 #include "opt_altivec.h" 44 45 #include <sys/param.h> 46 #include <sys/buf.h> 47 #include <sys/exec.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/mount.h> 51 #include <sys/msgbuf.h> 52 #include <sys/proc.h> 53 #include <sys/reboot.h> 54 #include <sys/syscallargs.h> 55 #include <sys/syslog.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/user.h> 59 #include <sys/boot_flag.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/netisr.h> 64 65 #ifdef DDB 66 #include <machine/db_machdep.h> 67 #include <ddb/db_extern.h> 68 #endif 69 70 #ifdef KGDB 71 #include <sys/kgdb.h> 72 #endif 73 74 #ifdef IPKDB 75 #include <ipkdb/ipkdb.h> 76 #endif 77 78 #include <powerpc/oea/bat.h> 79 #include <powerpc/oea/sr_601.h> 80 #include <powerpc/trap.h> 81 #include <powerpc/stdarg.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/pte.h> 84 #include <powerpc/altivec.h> 85 #include <machine/powerpc.h> 86 87 char machine[] = MACHINE; /* from <machine/param.h> */ 88 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 89 90 struct vm_map *exec_map = NULL; 91 struct vm_map *mb_map = NULL; 92 struct vm_map *phys_map = NULL; 93 94 /* 95 * Global variables used here and there 96 */ 97 extern struct user *proc0paddr; 98 99 static void trap0(void *); 100 101 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 102 struct bat battable[512]; 103 104 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 105 paddr_t msgbuf_paddr; 106 107 void 108 oea_init(void (*handler)(void)) 109 { 110 extern int trapcode[], trapsize[]; 111 extern int sctrap[], scsize[]; 112 extern int alitrap[], alisize[]; 113 extern int dsitrap[], dsisize[]; 114 #ifdef PPC_OEA601 115 extern int trapstart[], trapend[]; 116 extern int dsi601trap[], dsi601size[]; 117 #endif 118 extern int decrint[], decrsize[]; 119 extern int tlbimiss[], tlbimsize[]; 120 extern int tlbdlmiss[], tlbdlmsize[]; 121 extern int tlbdsmiss[], tlbdsmsize[]; 122 #if defined(DDB) || defined(KGDB) 123 extern int ddblow[], ddbsize[]; 124 #endif 125 #ifdef IPKDB 126 extern int ipkdblow[], ipkdbsize[]; 127 #endif 128 #ifdef ALTIVEC 129 register_t msr; 130 #endif 131 uintptr_t exc; 132 #if defined(ALTIVEC) || defined(PPC_OEA) 133 register_t scratch; 134 #endif 135 unsigned int cpuvers; 136 size_t size; 137 struct cpu_info * const ci = &cpu_info[0]; 138 139 mtspr(SPR_SPRG0, ci); 140 cpuvers = mfpvr() >> 16; 141 142 /* 143 * Initialize proc0 and current pcb and pmap pointers. 144 */ 145 KASSERT(ci != NULL); 146 KASSERT(curcpu() == ci); 147 lwp0.l_cpu = ci; 148 lwp0.l_addr = proc0paddr; 149 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 150 KASSERT(lwp0.l_cpu != NULL); 151 152 curpcb = &proc0paddr->u_pcb; 153 memset(curpcb, 0, sizeof(*curpcb)); 154 #ifdef ALTIVEC 155 /* 156 * Initialize the vectors with NaNs 157 */ 158 for (scratch = 0; scratch < 32; scratch++) { 159 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 160 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 161 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 162 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 163 } 164 curpcb->pcb_vr.vscr = 0; 165 curpcb->pcb_vr.vrsave = 0; 166 #endif 167 curpm = curpcb->pcb_pm = pmap_kernel(); 168 169 /* 170 * Cause a PGM trap if we branch to 0. 171 * 172 * XXX GCC4.1 complains about memset on address zero, so 173 * don't use the builtin. 174 */ 175 #undef memset 176 memset(0, 0, 0x100); 177 178 /* 179 * Set up trap vectors. Don't assume vectors are on 0x100. 180 */ 181 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 182 switch (exc) { 183 default: 184 size = (size_t)trapsize; 185 memcpy((void *)exc, trapcode, size); 186 break; 187 #if 0 188 case EXC_EXI: 189 /* 190 * This one is (potentially) installed during autoconf 191 */ 192 break; 193 #endif 194 case EXC_SC: 195 size = (size_t)scsize; 196 memcpy((void *)EXC_SC, sctrap, size); 197 break; 198 case EXC_ALI: 199 size = (size_t)alisize; 200 memcpy((void *)EXC_ALI, alitrap, size); 201 break; 202 case EXC_DSI: 203 #ifdef PPC_OEA601 204 if (cpuvers == MPC601) { 205 size = (size_t)dsi601size; 206 memcpy((void *)EXC_DSI, dsi601trap, size); 207 } else { 208 size = (size_t)dsisize; 209 memcpy((void *)EXC_DSI, dsitrap, size); 210 } 211 #else 212 size = (size_t)dsisize; 213 memcpy((void *)EXC_DSI, dsitrap, size); 214 #endif /* PPC_OEA601 */ 215 break; 216 case EXC_DECR: 217 size = (size_t)decrsize; 218 memcpy((void *)EXC_DECR, decrint, size); 219 break; 220 case EXC_IMISS: 221 size = (size_t)tlbimsize; 222 memcpy((void *)EXC_IMISS, tlbimiss, size); 223 break; 224 case EXC_DLMISS: 225 size = (size_t)tlbdlmsize; 226 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 227 break; 228 case EXC_DSMISS: 229 size = (size_t)tlbdsmsize; 230 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 231 break; 232 case EXC_PERF: 233 size = (size_t)trapsize; 234 memcpy((void *)EXC_PERF, trapcode, size); 235 memcpy((void *)EXC_VEC, trapcode, size); 236 break; 237 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 238 case EXC_RUNMODETRC: 239 if (cpuvers != MPC601) { 240 size = (size_t)trapsize; 241 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 242 break; 243 } 244 /* FALLTHROUGH */ 245 case EXC_PGM: 246 case EXC_TRC: 247 case EXC_BPT: 248 #if defined(DDB) || defined(KGDB) 249 size = (size_t)ddbsize; 250 memcpy((void *)exc, ddblow, size); 251 #if defined(IPKDB) 252 #error "cannot enable IPKDB with DDB or KGDB" 253 #endif 254 #else 255 size = (size_t)ipkdbsize; 256 memcpy((void *)exc, ipkdblow, size); 257 #endif 258 break; 259 #endif /* DDB || IPKDB || KGDB */ 260 } 261 #if 0 262 exc += roundup(size, 32); 263 #endif 264 } 265 266 /* 267 * Install a branch absolute to trap0 to force a panic. 268 */ 269 *(uint32_t *) 0 = 0x7c6802a6; 270 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 271 272 /* 273 * Get the cache sizes because install_extint calls __syncicache. 274 */ 275 cpu_probe_cache(); 276 277 #define MxSPR_MASK 0x7c1fffff 278 #define MFSPR_MQ 0x7c0002a6 279 #define MTSPR_MQ 0x7c0003a6 280 #define MTSPR_IBAT0L 0x7c1183a6 281 #define MTSPR_IBAT1L 0x7c1383a6 282 #define NOP 0x60000000 283 #define B 0x48000000 284 #define TLBSYNC 0x7c00046c 285 #define SYNC 0x7c0004ac 286 287 #ifdef ALTIVEC 288 #define MFSPR_VRSAVE 0x7c0042a6 289 #define MTSPR_VRSAVE 0x7c0043a6 290 291 /* 292 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 293 * not on a AltiVec capable processor. 294 */ 295 __asm volatile ( 296 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 297 "mfmsr %1; mtmsr %0; isync" 298 : "=r"(msr), "=r"(scratch) 299 : "J"(PSL_VEC)); 300 301 /* 302 * If we aren't on an AltiVec capable processor, we need to zap any of 303 * the sequences we save/restore the VRSAVE SPR into NOPs. 304 */ 305 if (scratch & PSL_VEC) { 306 cpu_altivec = 1; 307 } else { 308 int *ip = trapstart; 309 310 for (; ip < trapend; ip++) { 311 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 312 ip[0] = NOP; /* mfspr */ 313 ip[1] = NOP; /* stw */ 314 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 315 ip[-1] = NOP; /* lwz */ 316 ip[0] = NOP; /* mtspr */ 317 } 318 } 319 } 320 #endif 321 322 #ifdef PPC_OEA601 323 /* 324 * If we aren't on a MPC601 processor, we need to zap any of the 325 * sequences we save/restore the MQ SPR into NOPs, and skip over the 326 * sequences where we zap/restore BAT registers on kernel exit/entry. 327 */ 328 if (cpuvers != MPC601) { 329 int *ip = trapstart; 330 331 for (; ip < trapend; ip++) { 332 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 333 ip[0] = NOP; /* mfspr */ 334 ip[1] = NOP; /* stw */ 335 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 336 ip[-1] = NOP; /* lwz */ 337 ip[0] = NOP; /* mtspr */ 338 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 339 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 340 ip[-1] = B | 0x14; /* li */ 341 else 342 ip[-4] = B | 0x24; /* lis */ 343 } 344 } 345 } 346 347 /* 348 * Sync the changed instructions. 349 */ 350 __syncicache((void *) trapstart, 351 (uintptr_t) trapend - (uintptr_t) trapstart); 352 353 /* 354 * If we are on a MPC601 processor, we need to zap any tlbsync 355 * instructions into sync. This differs from the above in 356 * examing all kernel text, as opposed to just the exception handling. 357 * We sync the icache on every instruction found since there are 358 * only very few of them. 359 */ 360 if (cpuvers == MPC601) { 361 extern int kernel_text[], etext[]; 362 int *ip; 363 364 for (ip = kernel_text; ip < etext; ip++) 365 if (*ip == TLBSYNC) { 366 *ip = SYNC; 367 __syncicache(ip, sizeof(*ip)); 368 } 369 } 370 #endif /* PPC_OEA601 */ 371 372 /* 373 * Configure a PSL user mask matching this processor. 374 */ 375 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 376 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 377 #ifdef PPC_OEA601 378 if (cpuvers == MPC601) { 379 cpu_psluserset &= PSL_601_MASK; 380 cpu_pslusermod &= PSL_601_MASK; 381 } 382 #endif 383 #ifdef ALTIVEC 384 if (cpu_altivec) 385 cpu_pslusermod |= PSL_VEC; 386 #endif 387 388 /* 389 * external interrupt handler install 390 */ 391 if (handler) 392 oea_install_extint(handler); 393 394 __syncicache(0, EXC_LAST + 0x100); 395 396 /* 397 * Now enable translation (and machine checks/recoverable interrupts). 398 */ 399 #ifdef PPC_OEA 400 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 401 : "=r"(scratch) 402 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 403 #endif 404 405 KASSERT(curcpu() == ci); 406 } 407 408 #ifdef PPC_OEA601 409 void 410 mpc601_ioseg_add(paddr_t pa, register_t len) 411 { 412 const u_int i = pa >> ADDR_SR_SHFT; 413 414 if (len != BAT_BL_256M) 415 panic("mpc601_ioseg_add: len != 256M"); 416 417 /* 418 * Translate into an I/O segment, load it, and stash away for use 419 * in pmap_bootstrap(). 420 */ 421 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 422 __asm volatile ("mtsrin %0,%1" 423 :: "r"(iosrtable[i]), 424 "r"(pa)); 425 } 426 #endif /* PPC_OEA601 */ 427 428 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 429 void 430 oea_iobat_add(paddr_t pa, register_t len) 431 { 432 static int n = 1; 433 const u_int i = pa >> 28; 434 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 435 battable[i].batu = BATU(pa, len, BAT_Vs); 436 437 /* 438 * Let's start loading the BAT registers. 439 */ 440 switch (n) { 441 case 1: 442 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 443 :: "r"(battable[i].batl), 444 "r"(battable[i].batu)); 445 n = 2; 446 break; 447 case 2: 448 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 449 :: "r"(battable[i].batl), 450 "r"(battable[i].batu)); 451 n = 3; 452 break; 453 case 3: 454 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 455 :: "r"(battable[i].batl), 456 "r"(battable[i].batu)); 457 n = 4; 458 break; 459 default: 460 break; 461 } 462 } 463 464 void 465 oea_iobat_remove(paddr_t pa) 466 { 467 register_t batu; 468 int i, n; 469 470 n = pa >> ADDR_SR_SHFT; 471 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 472 !BAT_VALID_P(battable[n].batu, PSL_PR)) 473 return; 474 battable[n].batl = 0; 475 battable[n].batu = 0; 476 #define BAT_RESET(n) \ 477 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 478 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 479 480 for (i=1 ; i<4 ; i++) { 481 switch (i) { 482 case 1: 483 BATU_GET(1, batu); 484 if (BAT_VA_MATCH_P(batu, pa) && 485 BAT_VALID_P(batu, PSL_PR)) 486 BAT_RESET(1); 487 break; 488 case 2: 489 BATU_GET(2, batu); 490 if (BAT_VA_MATCH_P(batu, pa) && 491 BAT_VALID_P(batu, PSL_PR)) 492 BAT_RESET(2); 493 break; 494 case 3: 495 BATU_GET(3, batu); 496 if (BAT_VA_MATCH_P(batu, pa) && 497 BAT_VALID_P(batu, PSL_PR)) 498 BAT_RESET(3); 499 break; 500 default: 501 break; 502 } 503 } 504 } 505 506 void 507 oea_batinit(paddr_t pa, ...) 508 { 509 struct mem_region *allmem, *availmem, *mp; 510 unsigned int cpuvers; 511 register_t msr = mfmsr(); 512 va_list ap; 513 514 cpuvers = mfpvr() >> 16; 515 516 /* 517 * Initialize BAT registers to unmapped to not generate 518 * overlapping mappings below. 519 * 520 * The 601's implementation differs in the Valid bit being situated 521 * in the lower BAT register, and in being a unified BAT only whose 522 * four entries are accessed through the IBAT[0-3] SPRs. 523 * 524 * Also, while the 601 does distinguish between supervisor/user 525 * protection keys, it does _not_ distinguish between validity in 526 * supervisor/user mode. 527 */ 528 if ((msr & (PSL_IR|PSL_DR)) == 0) { 529 #ifdef PPC_OEA601 530 if (cpuvers == MPC601) { 531 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 532 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 533 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 534 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 535 } else 536 #endif /* PPC_OEA601 */ 537 { 538 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 539 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 540 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 541 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 542 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 543 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 544 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 545 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 546 } 547 } 548 549 /* 550 * Set up BAT to map physical memory 551 */ 552 #ifdef PPC_OEA601 553 if (cpuvers == MPC601) { 554 int i; 555 556 /* 557 * Set up battable to map the lowest 256 MB area. 558 * Map the lowest 32 MB area via BAT[0-3]; 559 * BAT[01] are fixed, BAT[23] are floating. 560 */ 561 for (i = 0; i < 32; i++) { 562 battable[i].batl = BATL601(i << 23, 563 BAT601_BSM_8M, BAT601_V); 564 battable[i].batu = BATU601(i << 23, 565 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 566 } 567 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 568 :: "r"(battable[0x00000000 >> 23].batl), 569 "r"(battable[0x00000000 >> 23].batu)); 570 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 571 :: "r"(battable[0x00800000 >> 23].batl), 572 "r"(battable[0x00800000 >> 23].batu)); 573 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 574 :: "r"(battable[0x01000000 >> 23].batl), 575 "r"(battable[0x01000000 >> 23].batu)); 576 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 577 :: "r"(battable[0x01800000 >> 23].batl), 578 "r"(battable[0x01800000 >> 23].batu)); 579 } else 580 #endif /* PPC_OEA601 */ 581 { 582 /* 583 * Set up BAT0 to only map the lowest 256 MB area 584 */ 585 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 586 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 587 588 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 589 "mtdbatl 0,%0; mtdbatu 0,%1;" 590 :: "r"(battable[0].batl), "r"(battable[0].batu)); 591 } 592 593 /* 594 * Now setup other fixed bat registers 595 * 596 * Note that we still run in real mode, and the BAT 597 * registers were cleared above. 598 */ 599 600 va_start(ap, pa); 601 602 /* 603 * Add any I/O BATs specificed; 604 * use I/O segments on the BAT-starved 601. 605 */ 606 #ifdef PPC_OEA601 607 if (cpuvers == MPC601) { 608 while (pa != 0) { 609 register_t len = va_arg(ap, register_t); 610 mpc601_ioseg_add(pa, len); 611 pa = va_arg(ap, paddr_t); 612 } 613 } else 614 #endif 615 { 616 while (pa != 0) { 617 register_t len = va_arg(ap, register_t); 618 oea_iobat_add(pa, len); 619 pa = va_arg(ap, paddr_t); 620 } 621 } 622 623 va_end(ap); 624 625 /* 626 * Set up battable to map all RAM regions. 627 * This is here because mem_regions() call needs bat0 set up. 628 */ 629 mem_regions(&allmem, &availmem); 630 #ifdef PPC_OEA601 631 if (cpuvers == MPC601) { 632 for (mp = allmem; mp->size; mp++) { 633 paddr_t paddr = mp->start & 0xff800000; 634 paddr_t end = mp->start + mp->size; 635 636 do { 637 u_int ix = paddr >> 23; 638 639 battable[ix].batl = 640 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 641 battable[ix].batu = 642 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 643 paddr += (1 << 23); 644 } while (paddr < end); 645 } 646 } else 647 #endif 648 { 649 for (mp = allmem; mp->size; mp++) { 650 paddr_t paddr = mp->start & 0xf0000000; 651 paddr_t end = mp->start + mp->size; 652 653 do { 654 u_int ix = paddr >> 28; 655 656 battable[ix].batl = 657 BATL(paddr, BAT_M, BAT_PP_RW); 658 battable[ix].batu = 659 BATU(paddr, BAT_BL_256M, BAT_Vs); 660 paddr += SEGMENT_LENGTH; 661 } while (paddr < end); 662 } 663 } 664 } 665 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 666 667 void 668 oea_install_extint(void (*handler)(void)) 669 { 670 extern int extint[], extsize[]; 671 extern int extint_call[]; 672 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 673 int omsr, msr; 674 675 #ifdef DIAGNOSTIC 676 if (offset > 0x1ffffff) 677 panic("install_extint: %p too far away (%#lx)", handler, 678 (unsigned long) offset); 679 #endif 680 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 681 : "=r" (omsr), "=r" (msr) 682 : "K" ((u_short)~PSL_EE)); 683 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 684 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 685 __syncicache((void *)extint_call, sizeof extint_call[0]); 686 __syncicache((void *)EXC_EXI, (int)extsize); 687 __asm volatile ("mtmsr %0" :: "r"(omsr)); 688 } 689 690 /* 691 * Machine dependent startup code. 692 */ 693 void 694 oea_startup(const char *model) 695 { 696 uintptr_t sz; 697 void *v; 698 vaddr_t minaddr, maxaddr; 699 char pbuf[9]; 700 u_int i; 701 702 KASSERT(curcpu() != NULL); 703 KASSERT(lwp0.l_cpu != NULL); 704 KASSERT(curcpu()->ci_intstk != 0); 705 KASSERT(curcpu()->ci_intrdepth == -1); 706 707 /* 708 * If the msgbuf is not in segment 0, allocate KVA for it and access 709 * it via mapped pages. [This prevents unneeded BAT switches.] 710 */ 711 sz = round_page(MSGBUFSIZE); 712 v = (void *) msgbuf_paddr; 713 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 714 minaddr = 0; 715 if (uvm_map(kernel_map, &minaddr, sz, 716 NULL, UVM_UNKNOWN_OFFSET, 0, 717 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 718 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 719 panic("startup: cannot allocate VM for msgbuf"); 720 v = (void *)minaddr; 721 for (i = 0; i < sz; i += PAGE_SIZE) { 722 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 723 VM_PROT_READ|VM_PROT_WRITE); 724 } 725 pmap_update(pmap_kernel()); 726 } 727 initmsgbuf(v, sz); 728 729 printf("%s%s", copyright, version); 730 if (model != NULL) 731 printf("Model: %s\n", model); 732 cpu_identify(NULL, 0); 733 734 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 735 printf("total memory = %s\n", pbuf); 736 737 /* 738 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 739 * the bufpages are allocated in case they overlap since it's not 740 * fatal if we can't allocate these. 741 */ 742 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 743 int error; 744 minaddr = 0xDEAC0000; 745 error = uvm_map(kernel_map, &minaddr, 0x30000, 746 NULL, UVM_UNKNOWN_OFFSET, 0, 747 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 748 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 749 if (error != 0 || minaddr != 0xDEAC0000) 750 printf("oea_startup: failed to allocate DEAD " 751 "ZONE: error=%d\n", error); 752 } 753 754 minaddr = 0; 755 /* 756 * Allocate a submap for exec arguments. This map effectively 757 * limits the number of processes exec'ing at any time. These 758 * submaps will be allocated after the dead zone. 759 */ 760 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 761 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 762 763 /* 764 * Allocate a submap for physio 765 */ 766 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 767 VM_PHYS_SIZE, 0, false, NULL); 768 769 #ifndef PMAP_MAP_POOLPAGE 770 /* 771 * No need to allocate an mbuf cluster submap. Mbuf clusters 772 * are allocated via the pool allocator, and we use direct-mapped 773 * pool pages. 774 */ 775 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 776 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 777 #endif 778 779 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 780 printf("avail memory = %s\n", pbuf); 781 } 782 783 /* 784 * Crash dump handling. 785 */ 786 787 void 788 oea_dumpsys(void) 789 { 790 printf("dumpsys: TBD\n"); 791 } 792 793 /* 794 * Convert kernel VA to physical address 795 */ 796 paddr_t 797 kvtop(void *addr) 798 { 799 vaddr_t va; 800 paddr_t pa; 801 uintptr_t off; 802 extern char end[]; 803 804 if (addr < (void *)end) 805 return (paddr_t)addr; 806 807 va = trunc_page((vaddr_t)addr); 808 off = (uintptr_t)addr - va; 809 810 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 811 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 812 return (paddr_t)addr; 813 } 814 815 return(pa + off); 816 } 817 818 /* 819 * Allocate vm space and mapin the I/O address 820 */ 821 void * 822 mapiodev(paddr_t pa, psize_t len) 823 { 824 paddr_t faddr; 825 vaddr_t taddr, va; 826 int off; 827 828 faddr = trunc_page(pa); 829 off = pa - faddr; 830 len = round_page(off + len); 831 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 832 833 if (va == 0) 834 return NULL; 835 836 for (; len > 0; len -= PAGE_SIZE) { 837 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 838 faddr += PAGE_SIZE; 839 taddr += PAGE_SIZE; 840 } 841 pmap_update(pmap_kernel()); 842 return (void *)(va + off); 843 } 844 845 void 846 unmapiodev(vaddr_t va, vsize_t len) 847 { 848 paddr_t faddr; 849 850 if (! va) 851 return; 852 853 faddr = trunc_page(va); 854 len = round_page(va - faddr + len); 855 856 pmap_kremove(faddr, len); 857 pmap_update(pmap_kernel()); 858 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 859 } 860 861 void 862 trap0(void *lr) 863 { 864 panic("call to null-ptr from %p", lr); 865 } 866
Indexes created Tue Sep 30 20:09:53 GMT 2025