oea_machdep.c revision 1.41
1 /* $NetBSD: oea_machdep.c,v 1.41 2008/02/06 03:15:06 garbled Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.41 2008/02/06 03:15:06 garbled Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/exec.h> 49 #include <sys/malloc.h> 50 #include <sys/mbuf.h> 51 #include <sys/mount.h> 52 #include <sys/msgbuf.h> 53 #include <sys/proc.h> 54 #include <sys/reboot.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/trap.h> 82 #include <powerpc/stdarg.h> 83 #include <powerpc/spr.h> 84 #include <powerpc/pte.h> 85 #include <powerpc/altivec.h> 86 #include <machine/powerpc.h> 87 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 91 struct vm_map *exec_map = NULL; 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 static void trap0(void *); 101 102 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 103 struct bat battable[512]; 104 105 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 106 paddr_t msgbuf_paddr; 107 108 void 109 oea_init(void (*handler)(void)) 110 { 111 extern int trapcode[], trapsize[]; 112 extern int sctrap[], scsize[]; 113 extern int alitrap[], alisize[]; 114 extern int dsitrap[], dsisize[]; 115 extern int trapstart[], trapend[]; 116 #ifdef PPC_OEA601 117 extern int dsi601trap[], dsi601size[]; 118 #endif 119 extern int decrint[], decrsize[]; 120 extern int tlbimiss[], tlbimsize[]; 121 extern int tlbdlmiss[], tlbdlmsize[]; 122 extern int tlbdsmiss[], tlbdsmsize[]; 123 #if defined(DDB) || defined(KGDB) 124 extern int ddblow[], ddbsize[]; 125 #endif 126 #ifdef IPKDB 127 extern int ipkdblow[], ipkdbsize[]; 128 #endif 129 #ifdef ALTIVEC 130 register_t msr; 131 #endif 132 uintptr_t exc; 133 #if defined(ALTIVEC) || defined(PPC_OEA) 134 register_t scratch; 135 #endif 136 unsigned int cpuvers; 137 size_t size; 138 struct cpu_info * const ci = &cpu_info[0]; 139 140 mtspr(SPR_SPRG0, ci); 141 cpuvers = mfpvr() >> 16; 142 143 /* 144 * Initialize proc0 and current pcb and pmap pointers. 145 */ 146 KASSERT(ci != NULL); 147 KASSERT(curcpu() == ci); 148 lwp0.l_cpu = ci; 149 lwp0.l_addr = proc0paddr; 150 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 151 KASSERT(lwp0.l_cpu != NULL); 152 153 curpcb = &proc0paddr->u_pcb; 154 memset(curpcb, 0, sizeof(*curpcb)); 155 #ifdef ALTIVEC 156 /* 157 * Initialize the vectors with NaNs 158 */ 159 for (scratch = 0; scratch < 32; scratch++) { 160 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 161 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 162 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 163 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 164 } 165 curpcb->pcb_vr.vscr = 0; 166 curpcb->pcb_vr.vrsave = 0; 167 #endif 168 curpm = curpcb->pcb_pm = pmap_kernel(); 169 170 /* 171 * Cause a PGM trap if we branch to 0. 172 * 173 * XXX GCC4.1 complains about memset on address zero, so 174 * don't use the builtin. 175 */ 176 #undef memset 177 memset(0, 0, 0x100); 178 179 /* 180 * Set up trap vectors. Don't assume vectors are on 0x100. 181 */ 182 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 183 switch (exc) { 184 default: 185 size = (size_t)trapsize; 186 memcpy((void *)exc, trapcode, size); 187 break; 188 #if 0 189 case EXC_EXI: 190 /* 191 * This one is (potentially) installed during autoconf 192 */ 193 break; 194 #endif 195 case EXC_SC: 196 size = (size_t)scsize; 197 memcpy((void *)EXC_SC, sctrap, size); 198 break; 199 case EXC_ALI: 200 size = (size_t)alisize; 201 memcpy((void *)EXC_ALI, alitrap, size); 202 break; 203 case EXC_DSI: 204 #ifdef PPC_OEA601 205 if (cpuvers == MPC601) { 206 size = (size_t)dsi601size; 207 memcpy((void *)EXC_DSI, dsi601trap, size); 208 } else { 209 size = (size_t)dsisize; 210 memcpy((void *)EXC_DSI, dsitrap, size); 211 } 212 #else 213 size = (size_t)dsisize; 214 memcpy((void *)EXC_DSI, dsitrap, size); 215 #endif /* PPC_OEA601 */ 216 break; 217 case EXC_DECR: 218 size = (size_t)decrsize; 219 memcpy((void *)EXC_DECR, decrint, size); 220 break; 221 case EXC_IMISS: 222 size = (size_t)tlbimsize; 223 memcpy((void *)EXC_IMISS, tlbimiss, size); 224 break; 225 case EXC_DLMISS: 226 size = (size_t)tlbdlmsize; 227 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 228 break; 229 case EXC_DSMISS: 230 size = (size_t)tlbdsmsize; 231 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 232 break; 233 case EXC_PERF: 234 size = (size_t)trapsize; 235 memcpy((void *)EXC_PERF, trapcode, size); 236 memcpy((void *)EXC_VEC, trapcode, size); 237 break; 238 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 239 case EXC_RUNMODETRC: 240 if (cpuvers != MPC601) { 241 size = (size_t)trapsize; 242 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 243 break; 244 } 245 /* FALLTHROUGH */ 246 case EXC_PGM: 247 case EXC_TRC: 248 case EXC_BPT: 249 #if defined(DDB) || defined(KGDB) 250 size = (size_t)ddbsize; 251 memcpy((void *)exc, ddblow, size); 252 #if defined(IPKDB) 253 #error "cannot enable IPKDB with DDB or KGDB" 254 #endif 255 #else 256 size = (size_t)ipkdbsize; 257 memcpy((void *)exc, ipkdblow, size); 258 #endif 259 break; 260 #endif /* DDB || IPKDB || KGDB */ 261 } 262 #if 0 263 exc += roundup(size, 32); 264 #endif 265 } 266 267 /* 268 * Install a branch absolute to trap0 to force a panic. 269 */ 270 *(uint32_t *) 0 = 0x7c6802a6; 271 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 272 273 /* 274 * Get the cache sizes because install_extint calls __syncicache. 275 */ 276 cpu_probe_cache(); 277 278 #define MxSPR_MASK 0x7c1fffff 279 #define MFSPR_MQ 0x7c0002a6 280 #define MTSPR_MQ 0x7c0003a6 281 #define MTSPR_IBAT0L 0x7c1183a6 282 #define MTSPR_IBAT1L 0x7c1383a6 283 #define NOP 0x60000000 284 #define B 0x48000000 285 #define TLBSYNC 0x7c00046c 286 #define SYNC 0x7c0004ac 287 288 #ifdef ALTIVEC 289 #define MFSPR_VRSAVE 0x7c0042a6 290 #define MTSPR_VRSAVE 0x7c0043a6 291 292 /* 293 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 294 * not on a AltiVec capable processor. 295 */ 296 __asm volatile ( 297 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 298 "mfmsr %1; mtmsr %0; isync" 299 : "=r"(msr), "=r"(scratch) 300 : "J"(PSL_VEC)); 301 302 /* 303 * If we aren't on an AltiVec capable processor, we need to zap any of 304 * the sequences we save/restore the VRSAVE SPR into NOPs. 305 */ 306 if (scratch & PSL_VEC) { 307 cpu_altivec = 1; 308 } else { 309 int *ip = trapstart; 310 311 for (; ip < trapend; ip++) { 312 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 313 ip[0] = NOP; /* mfspr */ 314 ip[1] = NOP; /* stw */ 315 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 316 ip[-1] = NOP; /* lwz */ 317 ip[0] = NOP; /* mtspr */ 318 } 319 } 320 } 321 #endif 322 323 /* XXX It would seem like this code could be elided ifndef 601, but 324 * doing so breaks my power3 machine. 325 */ 326 /* 327 * If we aren't on a MPC601 processor, we need to zap any of the 328 * sequences we save/restore the MQ SPR into NOPs, and skip over the 329 * sequences where we zap/restore BAT registers on kernel exit/entry. 330 */ 331 if (cpuvers != MPC601) { 332 int *ip = trapstart; 333 334 for (; ip < trapend; ip++) { 335 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 336 ip[0] = NOP; /* mfspr */ 337 ip[1] = NOP; /* stw */ 338 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 339 ip[-1] = NOP; /* lwz */ 340 ip[0] = NOP; /* mtspr */ 341 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 342 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 343 ip[-1] = B | 0x14; /* li */ 344 else 345 ip[-4] = B | 0x24; /* lis */ 346 } 347 } 348 } 349 350 /* 351 * Sync the changed instructions. 352 */ 353 __syncicache((void *) trapstart, 354 (uintptr_t) trapend - (uintptr_t) trapstart); 355 #ifdef PPC_OEA601 356 357 /* 358 * If we are on a MPC601 processor, we need to zap any tlbsync 359 * instructions into sync. This differs from the above in 360 * examing all kernel text, as opposed to just the exception handling. 361 * We sync the icache on every instruction found since there are 362 * only very few of them. 363 */ 364 if (cpuvers == MPC601) { 365 extern int kernel_text[], etext[]; 366 int *ip; 367 368 for (ip = kernel_text; ip < etext; ip++) 369 if (*ip == TLBSYNC) { 370 *ip = SYNC; 371 __syncicache(ip, sizeof(*ip)); 372 } 373 } 374 #endif /* PPC_OEA601 */ 375 376 /* 377 * Configure a PSL user mask matching this processor. 378 */ 379 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 380 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 381 #ifdef PPC_OEA601 382 if (cpuvers == MPC601) { 383 cpu_psluserset &= PSL_601_MASK; 384 cpu_pslusermod &= PSL_601_MASK; 385 } 386 #endif 387 #ifdef ALTIVEC 388 if (cpu_altivec) 389 cpu_pslusermod |= PSL_VEC; 390 #endif 391 392 /* 393 * external interrupt handler install 394 */ 395 if (handler) 396 oea_install_extint(handler); 397 398 __syncicache(0, EXC_LAST + 0x100); 399 400 /* 401 * Now enable translation (and machine checks/recoverable interrupts). 402 */ 403 #ifdef PPC_OEA 404 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 405 : "=r"(scratch) 406 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 407 #endif 408 409 KASSERT(curcpu() == ci); 410 } 411 412 #ifdef PPC_OEA601 413 void 414 mpc601_ioseg_add(paddr_t pa, register_t len) 415 { 416 const u_int i = pa >> ADDR_SR_SHFT; 417 418 if (len != BAT_BL_256M) 419 panic("mpc601_ioseg_add: len != 256M"); 420 421 /* 422 * Translate into an I/O segment, load it, and stash away for use 423 * in pmap_bootstrap(). 424 */ 425 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 426 __asm volatile ("mtsrin %0,%1" 427 :: "r"(iosrtable[i]), 428 "r"(pa)); 429 } 430 #endif /* PPC_OEA601 */ 431 432 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 433 void 434 oea_iobat_add(paddr_t pa, register_t len) 435 { 436 static int n = 1; 437 const u_int i = pa >> 28; 438 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 439 battable[i].batu = BATU(pa, len, BAT_Vs); 440 441 /* 442 * Let's start loading the BAT registers. 443 */ 444 switch (n) { 445 case 1: 446 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 447 :: "r"(battable[i].batl), 448 "r"(battable[i].batu)); 449 n = 2; 450 break; 451 case 2: 452 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 453 :: "r"(battable[i].batl), 454 "r"(battable[i].batu)); 455 n = 3; 456 break; 457 case 3: 458 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 459 :: "r"(battable[i].batl), 460 "r"(battable[i].batu)); 461 n = 4; 462 break; 463 default: 464 break; 465 } 466 } 467 468 void 469 oea_iobat_remove(paddr_t pa) 470 { 471 register_t batu; 472 int i, n; 473 474 n = pa >> ADDR_SR_SHFT; 475 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 476 !BAT_VALID_P(battable[n].batu, PSL_PR)) 477 return; 478 battable[n].batl = 0; 479 battable[n].batu = 0; 480 #define BAT_RESET(n) \ 481 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 482 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 483 484 for (i=1 ; i<4 ; i++) { 485 switch (i) { 486 case 1: 487 BATU_GET(1, batu); 488 if (BAT_VA_MATCH_P(batu, pa) && 489 BAT_VALID_P(batu, PSL_PR)) 490 BAT_RESET(1); 491 break; 492 case 2: 493 BATU_GET(2, batu); 494 if (BAT_VA_MATCH_P(batu, pa) && 495 BAT_VALID_P(batu, PSL_PR)) 496 BAT_RESET(2); 497 break; 498 case 3: 499 BATU_GET(3, batu); 500 if (BAT_VA_MATCH_P(batu, pa) && 501 BAT_VALID_P(batu, PSL_PR)) 502 BAT_RESET(3); 503 break; 504 default: 505 break; 506 } 507 } 508 } 509 510 void 511 oea_batinit(paddr_t pa, ...) 512 { 513 struct mem_region *allmem, *availmem, *mp; 514 unsigned int cpuvers; 515 register_t msr = mfmsr(); 516 va_list ap; 517 518 cpuvers = mfpvr() >> 16; 519 520 /* 521 * Initialize BAT registers to unmapped to not generate 522 * overlapping mappings below. 523 * 524 * The 601's implementation differs in the Valid bit being situated 525 * in the lower BAT register, and in being a unified BAT only whose 526 * four entries are accessed through the IBAT[0-3] SPRs. 527 * 528 * Also, while the 601 does distinguish between supervisor/user 529 * protection keys, it does _not_ distinguish between validity in 530 * supervisor/user mode. 531 */ 532 if ((msr & (PSL_IR|PSL_DR)) == 0) { 533 #ifdef PPC_OEA601 534 if (cpuvers == MPC601) { 535 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 536 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 537 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 538 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 539 } else 540 #endif /* PPC_OEA601 */ 541 { 542 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 543 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 544 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 545 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 546 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 547 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 548 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 549 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 550 } 551 } 552 553 /* 554 * Set up BAT to map physical memory 555 */ 556 #ifdef PPC_OEA601 557 if (cpuvers == MPC601) { 558 int i; 559 560 /* 561 * Set up battable to map the lowest 256 MB area. 562 * Map the lowest 32 MB area via BAT[0-3]; 563 * BAT[01] are fixed, BAT[23] are floating. 564 */ 565 for (i = 0; i < 32; i++) { 566 battable[i].batl = BATL601(i << 23, 567 BAT601_BSM_8M, BAT601_V); 568 battable[i].batu = BATU601(i << 23, 569 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 570 } 571 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 572 :: "r"(battable[0x00000000 >> 23].batl), 573 "r"(battable[0x00000000 >> 23].batu)); 574 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 575 :: "r"(battable[0x00800000 >> 23].batl), 576 "r"(battable[0x00800000 >> 23].batu)); 577 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 578 :: "r"(battable[0x01000000 >> 23].batl), 579 "r"(battable[0x01000000 >> 23].batu)); 580 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 581 :: "r"(battable[0x01800000 >> 23].batl), 582 "r"(battable[0x01800000 >> 23].batu)); 583 } else 584 #endif /* PPC_OEA601 */ 585 { 586 /* 587 * Set up BAT0 to only map the lowest 256 MB area 588 */ 589 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 590 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 591 592 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 593 "mtdbatl 0,%0; mtdbatu 0,%1;" 594 :: "r"(battable[0].batl), "r"(battable[0].batu)); 595 } 596 597 /* 598 * Now setup other fixed bat registers 599 * 600 * Note that we still run in real mode, and the BAT 601 * registers were cleared above. 602 */ 603 604 va_start(ap, pa); 605 606 /* 607 * Add any I/O BATs specificed; 608 * use I/O segments on the BAT-starved 601. 609 */ 610 #ifdef PPC_OEA601 611 if (cpuvers == MPC601) { 612 while (pa != 0) { 613 register_t len = va_arg(ap, register_t); 614 mpc601_ioseg_add(pa, len); 615 pa = va_arg(ap, paddr_t); 616 } 617 } else 618 #endif 619 { 620 while (pa != 0) { 621 register_t len = va_arg(ap, register_t); 622 oea_iobat_add(pa, len); 623 pa = va_arg(ap, paddr_t); 624 } 625 } 626 627 va_end(ap); 628 629 /* 630 * Set up battable to map all RAM regions. 631 * This is here because mem_regions() call needs bat0 set up. 632 */ 633 mem_regions(&allmem, &availmem); 634 #ifdef PPC_OEA601 635 if (cpuvers == MPC601) { 636 for (mp = allmem; mp->size; mp++) { 637 paddr_t paddr = mp->start & 0xff800000; 638 paddr_t end = mp->start + mp->size; 639 640 do { 641 u_int ix = paddr >> 23; 642 643 battable[ix].batl = 644 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 645 battable[ix].batu = 646 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 647 paddr += (1 << 23); 648 } while (paddr < end); 649 } 650 } else 651 #endif 652 { 653 for (mp = allmem; mp->size; mp++) { 654 paddr_t paddr = mp->start & 0xf0000000; 655 paddr_t end = mp->start + mp->size; 656 657 do { 658 u_int ix = paddr >> 28; 659 660 battable[ix].batl = 661 BATL(paddr, BAT_M, BAT_PP_RW); 662 battable[ix].batu = 663 BATU(paddr, BAT_BL_256M, BAT_Vs); 664 paddr += SEGMENT_LENGTH; 665 } while (paddr < end); 666 } 667 } 668 } 669 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 670 671 void 672 oea_install_extint(void (*handler)(void)) 673 { 674 extern int extint[], extsize[]; 675 extern int extint_call[]; 676 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 677 int omsr, msr; 678 679 #ifdef DIAGNOSTIC 680 if (offset > 0x1ffffff) 681 panic("install_extint: %p too far away (%#lx)", handler, 682 (unsigned long) offset); 683 #endif 684 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 685 : "=r" (omsr), "=r" (msr) 686 : "K" ((u_short)~PSL_EE)); 687 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 688 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 689 __syncicache((void *)extint_call, sizeof extint_call[0]); 690 __syncicache((void *)EXC_EXI, (int)extsize); 691 __asm volatile ("mtmsr %0" :: "r"(omsr)); 692 } 693 694 /* 695 * Machine dependent startup code. 696 */ 697 void 698 oea_startup(const char *model) 699 { 700 uintptr_t sz; 701 void *v; 702 vaddr_t minaddr, maxaddr; 703 char pbuf[9]; 704 u_int i; 705 706 KASSERT(curcpu() != NULL); 707 KASSERT(lwp0.l_cpu != NULL); 708 KASSERT(curcpu()->ci_intstk != 0); 709 KASSERT(curcpu()->ci_intrdepth == -1); 710 711 /* 712 * If the msgbuf is not in segment 0, allocate KVA for it and access 713 * it via mapped pages. [This prevents unneeded BAT switches.] 714 */ 715 sz = round_page(MSGBUFSIZE); 716 v = (void *) msgbuf_paddr; 717 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 718 minaddr = 0; 719 if (uvm_map(kernel_map, &minaddr, sz, 720 NULL, UVM_UNKNOWN_OFFSET, 0, 721 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 722 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 723 panic("startup: cannot allocate VM for msgbuf"); 724 v = (void *)minaddr; 725 for (i = 0; i < sz; i += PAGE_SIZE) { 726 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 727 VM_PROT_READ|VM_PROT_WRITE); 728 } 729 pmap_update(pmap_kernel()); 730 } 731 initmsgbuf(v, sz); 732 733 printf("%s%s", copyright, version); 734 if (model != NULL) 735 printf("Model: %s\n", model); 736 cpu_identify(NULL, 0); 737 738 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 739 printf("total memory = %s\n", pbuf); 740 741 /* 742 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 743 * the bufpages are allocated in case they overlap since it's not 744 * fatal if we can't allocate these. 745 */ 746 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 747 int error; 748 minaddr = 0xDEAC0000; 749 error = uvm_map(kernel_map, &minaddr, 0x30000, 750 NULL, UVM_UNKNOWN_OFFSET, 0, 751 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 752 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 753 if (error != 0 || minaddr != 0xDEAC0000) 754 printf("oea_startup: failed to allocate DEAD " 755 "ZONE: error=%d\n", error); 756 } 757 758 minaddr = 0; 759 /* 760 * Allocate a submap for exec arguments. This map effectively 761 * limits the number of processes exec'ing at any time. These 762 * submaps will be allocated after the dead zone. 763 */ 764 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 765 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 766 767 /* 768 * Allocate a submap for physio 769 */ 770 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 771 VM_PHYS_SIZE, 0, false, NULL); 772 773 #ifndef PMAP_MAP_POOLPAGE 774 /* 775 * No need to allocate an mbuf cluster submap. Mbuf clusters 776 * are allocated via the pool allocator, and we use direct-mapped 777 * pool pages. 778 */ 779 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 780 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 781 #endif 782 783 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 784 printf("avail memory = %s\n", pbuf); 785 } 786 787 /* 788 * Crash dump handling. 789 */ 790 791 void 792 oea_dumpsys(void) 793 { 794 printf("dumpsys: TBD\n"); 795 } 796 797 /* 798 * Convert kernel VA to physical address 799 */ 800 paddr_t 801 kvtop(void *addr) 802 { 803 vaddr_t va; 804 paddr_t pa; 805 uintptr_t off; 806 extern char end[]; 807 808 if (addr < (void *)end) 809 return (paddr_t)addr; 810 811 va = trunc_page((vaddr_t)addr); 812 off = (uintptr_t)addr - va; 813 814 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 815 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 816 return (paddr_t)addr; 817 } 818 819 return(pa + off); 820 } 821 822 /* 823 * Allocate vm space and mapin the I/O address 824 */ 825 void * 826 mapiodev(paddr_t pa, psize_t len) 827 { 828 paddr_t faddr; 829 vaddr_t taddr, va; 830 int off; 831 832 faddr = trunc_page(pa); 833 off = pa - faddr; 834 len = round_page(off + len); 835 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 836 837 if (va == 0) 838 return NULL; 839 840 for (; len > 0; len -= PAGE_SIZE) { 841 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 842 faddr += PAGE_SIZE; 843 taddr += PAGE_SIZE; 844 } 845 pmap_update(pmap_kernel()); 846 return (void *)(va + off); 847 } 848 849 void 850 unmapiodev(vaddr_t va, vsize_t len) 851 { 852 paddr_t faddr; 853 854 if (! va) 855 return; 856 857 faddr = trunc_page(va); 858 len = round_page(va - faddr + len); 859 860 pmap_kremove(faddr, len); 861 pmap_update(pmap_kernel()); 862 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 863 } 864 865 void 866 trap0(void *lr) 867 { 868 panic("call to null-ptr from %p", lr); 869 } 870
Indexes created Tue Sep 30 20:09:53 GMT 2025