oea_machdep.c revision 1.42
1 /* $NetBSD: oea_machdep.c,v 1.42 2008/02/07 01:17:51 matt Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.42 2008/02/07 01:17:51 matt Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/exec.h> 49 #include <sys/malloc.h> 50 #include <sys/mbuf.h> 51 #include <sys/mount.h> 52 #include <sys/msgbuf.h> 53 #include <sys/proc.h> 54 #include <sys/reboot.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/trap.h> 82 #include <powerpc/stdarg.h> 83 #include <powerpc/spr.h> 84 #include <powerpc/pte.h> 85 #include <powerpc/altivec.h> 86 #include <machine/powerpc.h> 87 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 91 struct vm_map *exec_map = NULL; 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 static void trap0(void *); 101 102 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 103 struct bat battable[512]; 104 105 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 106 paddr_t msgbuf_paddr; 107 108 void 109 oea_init(void (*handler)(void)) 110 { 111 extern int trapcode[], trapsize[]; 112 extern int sctrap[], scsize[]; 113 extern int alitrap[], alisize[]; 114 extern int dsitrap[], dsisize[]; 115 extern int trapstart[], trapend[]; 116 #ifdef PPC_OEA601 117 extern int dsi601trap[], dsi601size[]; 118 #endif 119 extern int decrint[], decrsize[]; 120 extern int tlbimiss[], tlbimsize[]; 121 extern int tlbdlmiss[], tlbdlmsize[]; 122 extern int tlbdsmiss[], tlbdsmsize[]; 123 #if defined(DDB) || defined(KGDB) 124 extern int ddblow[], ddbsize[]; 125 #endif 126 #ifdef IPKDB 127 extern int ipkdblow[], ipkdbsize[]; 128 #endif 129 #ifdef ALTIVEC 130 register_t msr; 131 #endif 132 uintptr_t exc; 133 #if defined(ALTIVEC) || defined(PPC_OEA) 134 register_t scratch; 135 #endif 136 unsigned int cpuvers; 137 size_t size; 138 struct cpu_info * const ci = &cpu_info[0]; 139 140 mtspr(SPR_SPRG0, ci); 141 cpuvers = mfpvr() >> 16; 142 143 /* 144 * Initialize proc0 and current pcb and pmap pointers. 145 */ 146 KASSERT(ci != NULL); 147 KASSERT(curcpu() == ci); 148 lwp0.l_cpu = ci; 149 lwp0.l_addr = proc0paddr; 150 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 151 KASSERT(lwp0.l_cpu != NULL); 152 153 curpcb = &proc0paddr->u_pcb; 154 memset(curpcb, 0, sizeof(*curpcb)); 155 #ifdef ALTIVEC 156 /* 157 * Initialize the vectors with NaNs 158 */ 159 for (scratch = 0; scratch < 32; scratch++) { 160 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 161 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 162 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 163 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 164 } 165 curpcb->pcb_vr.vscr = 0; 166 curpcb->pcb_vr.vrsave = 0; 167 #endif 168 curpm = curpcb->pcb_pm = pmap_kernel(); 169 170 /* 171 * Cause a PGM trap if we branch to 0. 172 * 173 * XXX GCC4.1 complains about memset on address zero, so 174 * don't use the builtin. 175 */ 176 #undef memset 177 memset(0, 0, 0x100); 178 179 /* 180 * Set up trap vectors. Don't assume vectors are on 0x100. 181 */ 182 for (exc = 0x0; exc <= EXC_LAST; exc += 0x100) { 183 switch (exc) { 184 default: 185 size = (size_t)trapsize; 186 memcpy((void *)exc, trapcode, size); 187 break; 188 #if 0 189 case EXC_EXI: 190 /* 191 * This one is (potentially) installed during autoconf 192 */ 193 break; 194 #endif 195 case EXC_SC: 196 size = (size_t)scsize; 197 memcpy((void *)EXC_SC, sctrap, size); 198 break; 199 case EXC_ALI: 200 size = (size_t)alisize; 201 memcpy((void *)EXC_ALI, alitrap, size); 202 break; 203 case EXC_DSI: 204 #ifdef PPC_OEA601 205 if (cpuvers == MPC601) { 206 size = (size_t)dsi601size; 207 memcpy((void *)EXC_DSI, dsi601trap, size); 208 break; 209 } 210 #endif /* PPC_OEA601 */ 211 size = (size_t)dsisize; 212 memcpy((void *)EXC_DSI, dsitrap, size); 213 break; 214 case EXC_DECR: 215 size = (size_t)decrsize; 216 memcpy((void *)EXC_DECR, decrint, size); 217 break; 218 case EXC_IMISS: 219 size = (size_t)tlbimsize; 220 memcpy((void *)EXC_IMISS, tlbimiss, size); 221 break; 222 case EXC_DLMISS: 223 size = (size_t)tlbdlmsize; 224 memcpy((void *)EXC_DLMISS, tlbdlmiss, size); 225 break; 226 case EXC_DSMISS: 227 size = (size_t)tlbdsmsize; 228 memcpy((void *)EXC_DSMISS, tlbdsmiss, size); 229 break; 230 case EXC_PERF: 231 size = (size_t)trapsize; 232 memcpy((void *)EXC_PERF, trapcode, size); 233 memcpy((void *)EXC_VEC, trapcode, size); 234 break; 235 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 236 case EXC_RUNMODETRC: 237 #ifdef PPC_OEA601 238 if (cpuvers != MPC601) { 239 #endif 240 size = (size_t)trapsize; 241 memcpy((void *)EXC_RUNMODETRC, trapcode, size); 242 break; 243 #ifdef PPC_OEA601 244 } 245 /* FALLTHROUGH */ 246 #endif 247 case EXC_PGM: 248 case EXC_TRC: 249 case EXC_BPT: 250 #if defined(DDB) || defined(KGDB) 251 size = (size_t)ddbsize; 252 memcpy((void *)exc, ddblow, size); 253 #if defined(IPKDB) 254 #error "cannot enable IPKDB with DDB or KGDB" 255 #endif 256 #else 257 size = (size_t)ipkdbsize; 258 memcpy((void *)exc, ipkdblow, size); 259 #endif 260 break; 261 #endif /* DDB || IPKDB || KGDB */ 262 } 263 #if 0 264 exc += roundup(size, 32); 265 #endif 266 } 267 268 /* 269 * Install a branch absolute to trap0 to force a panic. 270 */ 271 *(uint32_t *) 0 = 0x7c6802a6; 272 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 273 274 /* 275 * Get the cache sizes because install_extint calls __syncicache. 276 */ 277 cpu_probe_cache(); 278 279 #define MxSPR_MASK 0x7c1fffff 280 #define MFSPR_MQ 0x7c0002a6 281 #define MTSPR_MQ 0x7c0003a6 282 #define MTSPR_IBAT0L 0x7c1183a6 283 #define MTSPR_IBAT1L 0x7c1383a6 284 #define NOP 0x60000000 285 #define B 0x48000000 286 #define TLBSYNC 0x7c00046c 287 #define SYNC 0x7c0004ac 288 289 #ifdef ALTIVEC 290 #define MFSPR_VRSAVE 0x7c0042a6 291 #define MTSPR_VRSAVE 0x7c0043a6 292 293 /* 294 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 295 * not on a AltiVec capable processor. 296 */ 297 __asm volatile ( 298 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 299 "mfmsr %1; mtmsr %0; isync" 300 : "=r"(msr), "=r"(scratch) 301 : "J"(PSL_VEC)); 302 303 /* 304 * If we aren't on an AltiVec capable processor, we need to zap any of 305 * the sequences we save/restore the VRSAVE SPR into NOPs. 306 */ 307 if (scratch & PSL_VEC) { 308 cpu_altivec = 1; 309 } else { 310 int *ip = trapstart; 311 312 for (; ip < trapend; ip++) { 313 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 314 ip[0] = NOP; /* mfspr */ 315 ip[1] = NOP; /* stw */ 316 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 317 ip[-1] = NOP; /* lwz */ 318 ip[0] = NOP; /* mtspr */ 319 } 320 } 321 } 322 #endif 323 324 /* XXX It would seem like this code could be elided ifndef 601, but 325 * doing so breaks my power3 machine. 326 */ 327 /* 328 * If we aren't on a MPC601 processor, we need to zap any of the 329 * sequences we save/restore the MQ SPR into NOPs, and skip over the 330 * sequences where we zap/restore BAT registers on kernel exit/entry. 331 */ 332 if (cpuvers != MPC601) { 333 int *ip = trapstart; 334 335 for (; ip < trapend; ip++) { 336 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 337 ip[0] = NOP; /* mfspr */ 338 ip[1] = NOP; /* stw */ 339 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 340 ip[-1] = NOP; /* lwz */ 341 ip[0] = NOP; /* mtspr */ 342 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 343 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 344 ip[-1] = B | 0x14; /* li */ 345 else 346 ip[-4] = B | 0x24; /* lis */ 347 } 348 } 349 } 350 351 /* 352 * Sync the changed instructions. 353 */ 354 __syncicache((void *) trapstart, 355 (uintptr_t) trapend - (uintptr_t) trapstart); 356 #ifdef PPC_OEA601 357 358 /* 359 * If we are on a MPC601 processor, we need to zap any tlbsync 360 * instructions into sync. This differs from the above in 361 * examing all kernel text, as opposed to just the exception handling. 362 * We sync the icache on every instruction found since there are 363 * only very few of them. 364 */ 365 if (cpuvers == MPC601) { 366 extern int kernel_text[], etext[]; 367 int *ip; 368 369 for (ip = kernel_text; ip < etext; ip++) 370 if (*ip == TLBSYNC) { 371 *ip = SYNC; 372 __syncicache(ip, sizeof(*ip)); 373 } 374 } 375 #endif /* PPC_OEA601 */ 376 377 /* 378 * Configure a PSL user mask matching this processor. 379 */ 380 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 381 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 382 #ifdef PPC_OEA601 383 if (cpuvers == MPC601) { 384 cpu_psluserset &= PSL_601_MASK; 385 cpu_pslusermod &= PSL_601_MASK; 386 } 387 #endif 388 #ifdef ALTIVEC 389 if (cpu_altivec) 390 cpu_pslusermod |= PSL_VEC; 391 #endif 392 393 /* 394 * external interrupt handler install 395 */ 396 if (handler) 397 oea_install_extint(handler); 398 399 __syncicache(0, EXC_LAST + 0x100); 400 401 /* 402 * Now enable translation (and machine checks/recoverable interrupts). 403 */ 404 #ifdef PPC_OEA 405 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 406 : "=r"(scratch) 407 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 408 #endif 409 410 KASSERT(curcpu() == ci); 411 } 412 413 #ifdef PPC_OEA601 414 void 415 mpc601_ioseg_add(paddr_t pa, register_t len) 416 { 417 const u_int i = pa >> ADDR_SR_SHFT; 418 419 if (len != BAT_BL_256M) 420 panic("mpc601_ioseg_add: len != 256M"); 421 422 /* 423 * Translate into an I/O segment, load it, and stash away for use 424 * in pmap_bootstrap(). 425 */ 426 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 427 __asm volatile ("mtsrin %0,%1" 428 :: "r"(iosrtable[i]), 429 "r"(pa)); 430 } 431 #endif /* PPC_OEA601 */ 432 433 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 434 void 435 oea_iobat_add(paddr_t pa, register_t len) 436 { 437 static int n = 1; 438 const u_int i = pa >> 28; 439 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 440 battable[i].batu = BATU(pa, len, BAT_Vs); 441 442 /* 443 * Let's start loading the BAT registers. 444 */ 445 switch (n) { 446 case 1: 447 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 448 :: "r"(battable[i].batl), 449 "r"(battable[i].batu)); 450 n = 2; 451 break; 452 case 2: 453 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 454 :: "r"(battable[i].batl), 455 "r"(battable[i].batu)); 456 n = 3; 457 break; 458 case 3: 459 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 460 :: "r"(battable[i].batl), 461 "r"(battable[i].batu)); 462 n = 4; 463 break; 464 default: 465 break; 466 } 467 } 468 469 void 470 oea_iobat_remove(paddr_t pa) 471 { 472 register_t batu; 473 int i, n; 474 475 n = pa >> ADDR_SR_SHFT; 476 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 477 !BAT_VALID_P(battable[n].batu, PSL_PR)) 478 return; 479 battable[n].batl = 0; 480 battable[n].batu = 0; 481 #define BAT_RESET(n) \ 482 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 483 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 484 485 for (i=1 ; i<4 ; i++) { 486 switch (i) { 487 case 1: 488 BATU_GET(1, batu); 489 if (BAT_VA_MATCH_P(batu, pa) && 490 BAT_VALID_P(batu, PSL_PR)) 491 BAT_RESET(1); 492 break; 493 case 2: 494 BATU_GET(2, batu); 495 if (BAT_VA_MATCH_P(batu, pa) && 496 BAT_VALID_P(batu, PSL_PR)) 497 BAT_RESET(2); 498 break; 499 case 3: 500 BATU_GET(3, batu); 501 if (BAT_VA_MATCH_P(batu, pa) && 502 BAT_VALID_P(batu, PSL_PR)) 503 BAT_RESET(3); 504 break; 505 default: 506 break; 507 } 508 } 509 } 510 511 void 512 oea_batinit(paddr_t pa, ...) 513 { 514 struct mem_region *allmem, *availmem, *mp; 515 unsigned int cpuvers; 516 register_t msr = mfmsr(); 517 va_list ap; 518 519 cpuvers = mfpvr() >> 16; 520 521 /* 522 * Initialize BAT registers to unmapped to not generate 523 * overlapping mappings below. 524 * 525 * The 601's implementation differs in the Valid bit being situated 526 * in the lower BAT register, and in being a unified BAT only whose 527 * four entries are accessed through the IBAT[0-3] SPRs. 528 * 529 * Also, while the 601 does distinguish between supervisor/user 530 * protection keys, it does _not_ distinguish between validity in 531 * supervisor/user mode. 532 */ 533 if ((msr & (PSL_IR|PSL_DR)) == 0) { 534 #ifdef PPC_OEA601 535 if (cpuvers == MPC601) { 536 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 537 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 538 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 539 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 540 } else 541 #endif /* PPC_OEA601 */ 542 { 543 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 544 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 545 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 546 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 547 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 548 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 549 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 550 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 551 } 552 } 553 554 /* 555 * Set up BAT to map physical memory 556 */ 557 #ifdef PPC_OEA601 558 if (cpuvers == MPC601) { 559 int i; 560 561 /* 562 * Set up battable to map the lowest 256 MB area. 563 * Map the lowest 32 MB area via BAT[0-3]; 564 * BAT[01] are fixed, BAT[23] are floating. 565 */ 566 for (i = 0; i < 32; i++) { 567 battable[i].batl = BATL601(i << 23, 568 BAT601_BSM_8M, BAT601_V); 569 battable[i].batu = BATU601(i << 23, 570 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 571 } 572 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 573 :: "r"(battable[0x00000000 >> 23].batl), 574 "r"(battable[0x00000000 >> 23].batu)); 575 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 576 :: "r"(battable[0x00800000 >> 23].batl), 577 "r"(battable[0x00800000 >> 23].batu)); 578 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 579 :: "r"(battable[0x01000000 >> 23].batl), 580 "r"(battable[0x01000000 >> 23].batu)); 581 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 582 :: "r"(battable[0x01800000 >> 23].batl), 583 "r"(battable[0x01800000 >> 23].batu)); 584 } else 585 #endif /* PPC_OEA601 */ 586 { 587 /* 588 * Set up BAT0 to only map the lowest 256 MB area 589 */ 590 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 591 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 592 593 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 594 "mtdbatl 0,%0; mtdbatu 0,%1;" 595 :: "r"(battable[0].batl), "r"(battable[0].batu)); 596 } 597 598 /* 599 * Now setup other fixed bat registers 600 * 601 * Note that we still run in real mode, and the BAT 602 * registers were cleared above. 603 */ 604 605 va_start(ap, pa); 606 607 /* 608 * Add any I/O BATs specificed; 609 * use I/O segments on the BAT-starved 601. 610 */ 611 #ifdef PPC_OEA601 612 if (cpuvers == MPC601) { 613 while (pa != 0) { 614 register_t len = va_arg(ap, register_t); 615 mpc601_ioseg_add(pa, len); 616 pa = va_arg(ap, paddr_t); 617 } 618 } else 619 #endif 620 { 621 while (pa != 0) { 622 register_t len = va_arg(ap, register_t); 623 oea_iobat_add(pa, len); 624 pa = va_arg(ap, paddr_t); 625 } 626 } 627 628 va_end(ap); 629 630 /* 631 * Set up battable to map all RAM regions. 632 * This is here because mem_regions() call needs bat0 set up. 633 */ 634 mem_regions(&allmem, &availmem); 635 #ifdef PPC_OEA601 636 if (cpuvers == MPC601) { 637 for (mp = allmem; mp->size; mp++) { 638 paddr_t paddr = mp->start & 0xff800000; 639 paddr_t end = mp->start + mp->size; 640 641 do { 642 u_int ix = paddr >> 23; 643 644 battable[ix].batl = 645 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 646 battable[ix].batu = 647 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 648 paddr += (1 << 23); 649 } while (paddr < end); 650 } 651 } else 652 #endif 653 { 654 for (mp = allmem; mp->size; mp++) { 655 paddr_t paddr = mp->start & 0xf0000000; 656 paddr_t end = mp->start + mp->size; 657 658 do { 659 u_int ix = paddr >> 28; 660 661 battable[ix].batl = 662 BATL(paddr, BAT_M, BAT_PP_RW); 663 battable[ix].batu = 664 BATU(paddr, BAT_BL_256M, BAT_Vs); 665 paddr += SEGMENT_LENGTH; 666 } while (paddr < end); 667 } 668 } 669 } 670 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 671 672 void 673 oea_install_extint(void (*handler)(void)) 674 { 675 extern int extint[], extsize[]; 676 extern int extint_call[]; 677 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 678 int omsr, msr; 679 680 #ifdef DIAGNOSTIC 681 if (offset > 0x1ffffff) 682 panic("install_extint: %p too far away (%#lx)", handler, 683 (unsigned long) offset); 684 #endif 685 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 686 : "=r" (omsr), "=r" (msr) 687 : "K" ((u_short)~PSL_EE)); 688 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 689 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 690 __syncicache((void *)extint_call, sizeof extint_call[0]); 691 __syncicache((void *)EXC_EXI, (int)extsize); 692 __asm volatile ("mtmsr %0" :: "r"(omsr)); 693 } 694 695 /* 696 * Machine dependent startup code. 697 */ 698 void 699 oea_startup(const char *model) 700 { 701 uintptr_t sz; 702 void *v; 703 vaddr_t minaddr, maxaddr; 704 char pbuf[9]; 705 u_int i; 706 707 KASSERT(curcpu() != NULL); 708 KASSERT(lwp0.l_cpu != NULL); 709 KASSERT(curcpu()->ci_intstk != 0); 710 KASSERT(curcpu()->ci_intrdepth == -1); 711 712 /* 713 * If the msgbuf is not in segment 0, allocate KVA for it and access 714 * it via mapped pages. [This prevents unneeded BAT switches.] 715 */ 716 sz = round_page(MSGBUFSIZE); 717 v = (void *) msgbuf_paddr; 718 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 719 minaddr = 0; 720 if (uvm_map(kernel_map, &minaddr, sz, 721 NULL, UVM_UNKNOWN_OFFSET, 0, 722 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 723 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 724 panic("startup: cannot allocate VM for msgbuf"); 725 v = (void *)minaddr; 726 for (i = 0; i < sz; i += PAGE_SIZE) { 727 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 728 VM_PROT_READ|VM_PROT_WRITE); 729 } 730 pmap_update(pmap_kernel()); 731 } 732 initmsgbuf(v, sz); 733 734 printf("%s%s", copyright, version); 735 if (model != NULL) 736 printf("Model: %s\n", model); 737 cpu_identify(NULL, 0); 738 739 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 740 printf("total memory = %s\n", pbuf); 741 742 /* 743 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 744 * the bufpages are allocated in case they overlap since it's not 745 * fatal if we can't allocate these. 746 */ 747 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 748 int error; 749 minaddr = 0xDEAC0000; 750 error = uvm_map(kernel_map, &minaddr, 0x30000, 751 NULL, UVM_UNKNOWN_OFFSET, 0, 752 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 753 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 754 if (error != 0 || minaddr != 0xDEAC0000) 755 printf("oea_startup: failed to allocate DEAD " 756 "ZONE: error=%d\n", error); 757 } 758 759 minaddr = 0; 760 /* 761 * Allocate a submap for exec arguments. This map effectively 762 * limits the number of processes exec'ing at any time. These 763 * submaps will be allocated after the dead zone. 764 */ 765 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 766 16*NCARGS, VM_MAP_PAGEABLE, false, NULL); 767 768 /* 769 * Allocate a submap for physio 770 */ 771 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 772 VM_PHYS_SIZE, 0, false, NULL); 773 774 #ifndef PMAP_MAP_POOLPAGE 775 /* 776 * No need to allocate an mbuf cluster submap. Mbuf clusters 777 * are allocated via the pool allocator, and we use direct-mapped 778 * pool pages. 779 */ 780 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 781 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 782 #endif 783 784 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 785 printf("avail memory = %s\n", pbuf); 786 } 787 788 /* 789 * Crash dump handling. 790 */ 791 792 void 793 oea_dumpsys(void) 794 { 795 printf("dumpsys: TBD\n"); 796 } 797 798 /* 799 * Convert kernel VA to physical address 800 */ 801 paddr_t 802 kvtop(void *addr) 803 { 804 vaddr_t va; 805 paddr_t pa; 806 uintptr_t off; 807 extern char end[]; 808 809 if (addr < (void *)end) 810 return (paddr_t)addr; 811 812 va = trunc_page((vaddr_t)addr); 813 off = (uintptr_t)addr - va; 814 815 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 816 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 817 return (paddr_t)addr; 818 } 819 820 return(pa + off); 821 } 822 823 /* 824 * Allocate vm space and mapin the I/O address 825 */ 826 void * 827 mapiodev(paddr_t pa, psize_t len) 828 { 829 paddr_t faddr; 830 vaddr_t taddr, va; 831 int off; 832 833 faddr = trunc_page(pa); 834 off = pa - faddr; 835 len = round_page(off + len); 836 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 837 838 if (va == 0) 839 return NULL; 840 841 for (; len > 0; len -= PAGE_SIZE) { 842 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 843 faddr += PAGE_SIZE; 844 taddr += PAGE_SIZE; 845 } 846 pmap_update(pmap_kernel()); 847 return (void *)(va + off); 848 } 849 850 void 851 unmapiodev(vaddr_t va, vsize_t len) 852 { 853 paddr_t faddr; 854 855 if (! va) 856 return; 857 858 faddr = trunc_page(va); 859 len = round_page(va - faddr + len); 860 861 pmap_kremove(faddr, len); 862 pmap_update(pmap_kernel()); 863 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 864 } 865 866 void 867 trap0(void *lr) 868 { 869 panic("call to null-ptr from %p", lr); 870 } 871
Indexes created Wed Oct 01 07:09:59 GMT 2025