oea_machdep.c revision 1.46
1 /* $NetBSD: oea_machdep.c,v 1.46 2008/07/02 17:28:56 ad Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.46 2008/07/02 17:28:56 ad Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/exec.h> 49 #include <sys/malloc.h> 50 #include <sys/mbuf.h> 51 #include <sys/mount.h> 52 #include <sys/msgbuf.h> 53 #include <sys/proc.h> 54 #include <sys/reboot.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/oea/cpufeat.h> 82 #include <powerpc/trap.h> 83 #include <powerpc/stdarg.h> 84 #include <powerpc/spr.h> 85 #include <powerpc/pte.h> 86 #include <powerpc/altivec.h> 87 #include <machine/powerpc.h> 88 89 char machine[] = MACHINE; /* from <machine/param.h> */ 90 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 91 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 static void trap0(void *); 101 102 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 103 struct bat battable[512]; 104 105 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 106 paddr_t msgbuf_paddr; 107 108 void 109 oea_init(void (*handler)(void)) 110 { 111 extern int trapcode[], trapsize[]; 112 extern int sctrap[], scsize[]; 113 extern int alitrap[], alisize[]; 114 extern int dsitrap[], dsisize[]; 115 extern int trapstart[], trapend[]; 116 #ifdef PPC_OEA601 117 extern int dsi601trap[], dsi601size[]; 118 #endif 119 extern int decrint[], decrsize[]; 120 extern int tlbimiss[], tlbimsize[]; 121 extern int tlbdlmiss[], tlbdlmsize[]; 122 extern int tlbdsmiss[], tlbdsmsize[]; 123 #if defined(DDB) || defined(KGDB) 124 extern int ddblow[], ddbsize[]; 125 #endif 126 #ifdef IPKDB 127 extern int ipkdblow[], ipkdbsize[]; 128 #endif 129 #ifdef ALTIVEC 130 register_t msr; 131 #endif 132 uintptr_t exc, exc_base; 133 #if defined(ALTIVEC) || defined(PPC_OEA) 134 register_t scratch; 135 #endif 136 unsigned int cpuvers; 137 size_t size; 138 struct cpu_info * const ci = &cpu_info[0]; 139 140 #ifdef PPC_HIGH_VEC 141 exc_base = EXC_HIGHVEC; 142 #else 143 exc_base = 0; 144 #endif 145 mtspr(SPR_SPRG0, ci); 146 cpuvers = mfpvr() >> 16; 147 148 /* 149 * Initialize proc0 and current pcb and pmap pointers. 150 */ 151 KASSERT(ci != NULL); 152 KASSERT(curcpu() == ci); 153 lwp0.l_cpu = ci; 154 lwp0.l_addr = proc0paddr; 155 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 156 KASSERT(lwp0.l_cpu != NULL); 157 158 curpcb = &proc0paddr->u_pcb; 159 memset(curpcb, 0, sizeof(*curpcb)); 160 #ifdef ALTIVEC 161 /* 162 * Initialize the vectors with NaNs 163 */ 164 for (scratch = 0; scratch < 32; scratch++) { 165 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 166 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 167 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 168 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 169 } 170 curpcb->pcb_vr.vscr = 0; 171 curpcb->pcb_vr.vrsave = 0; 172 #endif 173 curpm = curpcb->pcb_pm = pmap_kernel(); 174 175 /* 176 * Cause a PGM trap if we branch to 0. 177 * 178 * XXX GCC4.1 complains about memset on address zero, so 179 * don't use the builtin. 180 */ 181 #undef memset 182 memset(0, 0, 0x100); 183 184 /* 185 * Set up trap vectors. Don't assume vectors are on 0x100. 186 */ 187 for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) { 188 switch (exc - exc_base) { 189 default: 190 size = (size_t)trapsize; 191 memcpy((void *)exc, trapcode, size); 192 break; 193 #if 0 194 case EXC_EXI: 195 /* 196 * This one is (potentially) installed during autoconf 197 */ 198 break; 199 #endif 200 case EXC_SC: 201 size = (size_t)scsize; 202 memcpy((void *)exc, sctrap, size); 203 break; 204 case EXC_ALI: 205 size = (size_t)alisize; 206 memcpy((void *)exc, alitrap, size); 207 break; 208 case EXC_DSI: 209 #ifdef PPC_OEA601 210 if (cpuvers == MPC601) { 211 size = (size_t)dsi601size; 212 memcpy((void *)exc, dsi601trap, size); 213 break; 214 } else 215 #endif /* PPC_OEA601 */ 216 if (oeacpufeat & OEACPU_NOBAT) { 217 size = (size_t)alisize; 218 memcpy((void *)exc, alitrap, size); 219 } else { 220 size = (size_t)dsisize; 221 memcpy((void *)exc, dsitrap, size); 222 } 223 break; 224 case EXC_DECR: 225 size = (size_t)decrsize; 226 memcpy((void *)exc, decrint, size); 227 break; 228 case EXC_IMISS: 229 size = (size_t)tlbimsize; 230 memcpy((void *)exc, tlbimiss, size); 231 break; 232 case EXC_DLMISS: 233 size = (size_t)tlbdlmsize; 234 memcpy((void *)exc, tlbdlmiss, size); 235 break; 236 case EXC_DSMISS: 237 size = (size_t)tlbdsmsize; 238 memcpy((void *)exc, tlbdsmiss, size); 239 break; 240 case EXC_PERF: 241 size = (size_t)trapsize; 242 memcpy((void *)exc, trapcode, size); 243 memcpy((void *)(exc_base + EXC_VEC), trapcode, size); 244 break; 245 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 246 case EXC_RUNMODETRC: 247 #ifdef PPC_OEA601 248 if (cpuvers != MPC601) { 249 #endif 250 size = (size_t)trapsize; 251 memcpy((void *)exc, trapcode, size); 252 break; 253 #ifdef PPC_OEA601 254 } 255 /* FALLTHROUGH */ 256 #endif 257 case EXC_PGM: 258 case EXC_TRC: 259 case EXC_BPT: 260 #if defined(DDB) || defined(KGDB) 261 size = (size_t)ddbsize; 262 memcpy((void *)exc, ddblow, size); 263 #if defined(IPKDB) 264 #error "cannot enable IPKDB with DDB or KGDB" 265 #endif 266 #else 267 size = (size_t)ipkdbsize; 268 memcpy((void *)exc, ipkdblow, size); 269 #endif 270 break; 271 #endif /* DDB || IPKDB || KGDB */ 272 } 273 #if 0 274 exc += roundup(size, 32); 275 #endif 276 } 277 278 /* 279 * Install a branch absolute to trap0 to force a panic. 280 */ 281 if ((uintptr_t)trap0 < 0x2000000) { 282 *(uint32_t *) 0 = 0x7c6802a6; 283 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 284 } 285 286 /* 287 * Get the cache sizes because install_extint calls __syncicache. 288 */ 289 cpu_probe_cache(); 290 291 #define MxSPR_MASK 0x7c1fffff 292 #define MFSPR_MQ 0x7c0002a6 293 #define MTSPR_MQ 0x7c0003a6 294 #define MTSPR_IBAT0L 0x7c1183a6 295 #define MTSPR_IBAT1L 0x7c1383a6 296 #define NOP 0x60000000 297 #define B 0x48000000 298 #define TLBSYNC 0x7c00046c 299 #define SYNC 0x7c0004ac 300 301 #ifdef ALTIVEC 302 #define MFSPR_VRSAVE 0x7c0042a6 303 #define MTSPR_VRSAVE 0x7c0043a6 304 305 /* 306 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 307 * not on a AltiVec capable processor. 308 */ 309 __asm volatile ( 310 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 311 "mfmsr %1; mtmsr %0; isync" 312 : "=r"(msr), "=r"(scratch) 313 : "J"(PSL_VEC)); 314 315 /* 316 * If we aren't on an AltiVec capable processor, we need to zap any of 317 * the sequences we save/restore the VRSAVE SPR into NOPs. 318 */ 319 if (scratch & PSL_VEC) { 320 cpu_altivec = 1; 321 } else { 322 int *ip = trapstart; 323 324 for (; ip < trapend; ip++) { 325 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 326 ip[0] = NOP; /* mfspr */ 327 ip[1] = NOP; /* stw */ 328 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 329 ip[-1] = NOP; /* lwz */ 330 ip[0] = NOP; /* mtspr */ 331 } 332 } 333 } 334 #endif 335 336 /* XXX It would seem like this code could be elided ifndef 601, but 337 * doing so breaks my power3 machine. 338 */ 339 /* 340 * If we aren't on a MPC601 processor, we need to zap any of the 341 * sequences we save/restore the MQ SPR into NOPs, and skip over the 342 * sequences where we zap/restore BAT registers on kernel exit/entry. 343 */ 344 if (cpuvers != MPC601) { 345 int *ip = trapstart; 346 347 for (; ip < trapend; ip++) { 348 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 349 ip[0] = NOP; /* mfspr */ 350 ip[1] = NOP; /* stw */ 351 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 352 ip[-1] = NOP; /* lwz */ 353 ip[0] = NOP; /* mtspr */ 354 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 355 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 356 ip[-1] = B | 0x14; /* li */ 357 else 358 ip[-4] = B | 0x24; /* lis */ 359 } 360 } 361 } 362 363 /* 364 * Sync the changed instructions. 365 */ 366 __syncicache((void *) trapstart, 367 (uintptr_t) trapend - (uintptr_t) trapstart); 368 #ifdef PPC_OEA601 369 370 /* 371 * If we are on a MPC601 processor, we need to zap any tlbsync 372 * instructions into sync. This differs from the above in 373 * examing all kernel text, as opposed to just the exception handling. 374 * We sync the icache on every instruction found since there are 375 * only very few of them. 376 */ 377 if (cpuvers == MPC601) { 378 extern int kernel_text[], etext[]; 379 int *ip; 380 381 for (ip = kernel_text; ip < etext; ip++) 382 if (*ip == TLBSYNC) { 383 *ip = SYNC; 384 __syncicache(ip, sizeof(*ip)); 385 } 386 } 387 #endif /* PPC_OEA601 */ 388 389 /* 390 * Configure a PSL user mask matching this processor. 391 */ 392 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 393 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 394 #ifdef PPC_OEA601 395 if (cpuvers == MPC601) { 396 cpu_psluserset &= PSL_601_MASK; 397 cpu_pslusermod &= PSL_601_MASK; 398 } 399 #endif 400 #ifdef ALTIVEC 401 if (cpu_altivec) 402 cpu_pslusermod |= PSL_VEC; 403 #endif 404 #ifdef PPC_HIGH_VEC 405 cpu_psluserset |= PSL_IP; /* XXX ok? */ 406 #endif 407 408 /* 409 * external interrupt handler install 410 */ 411 if (handler) 412 oea_install_extint(handler); 413 414 __syncicache((void *)exc_base, EXC_LAST + 0x100); 415 416 /* 417 * Now enable translation (and machine checks/recoverable interrupts). 418 */ 419 #ifdef PPC_OEA 420 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 421 : "=r"(scratch) 422 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 423 #endif 424 425 KASSERT(curcpu() == ci); 426 } 427 428 #ifdef PPC_OEA601 429 void 430 mpc601_ioseg_add(paddr_t pa, register_t len) 431 { 432 const u_int i = pa >> ADDR_SR_SHFT; 433 434 if (len != BAT_BL_256M) 435 panic("mpc601_ioseg_add: len != 256M"); 436 437 /* 438 * Translate into an I/O segment, load it, and stash away for use 439 * in pmap_bootstrap(). 440 */ 441 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 442 __asm volatile ("mtsrin %0,%1" 443 :: "r"(iosrtable[i]), 444 "r"(pa)); 445 } 446 #endif /* PPC_OEA601 */ 447 448 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 449 void 450 oea_iobat_add(paddr_t pa, register_t len) 451 { 452 static int n = 1; 453 const u_int i = pa >> 28; 454 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 455 battable[i].batu = BATU(pa, len, BAT_Vs); 456 457 /* 458 * Let's start loading the BAT registers. 459 */ 460 switch (n) { 461 case 1: 462 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 463 :: "r"(battable[i].batl), 464 "r"(battable[i].batu)); 465 n = 2; 466 break; 467 case 2: 468 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 469 :: "r"(battable[i].batl), 470 "r"(battable[i].batu)); 471 n = 3; 472 break; 473 case 3: 474 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 475 :: "r"(battable[i].batl), 476 "r"(battable[i].batu)); 477 n = 4; 478 break; 479 default: 480 break; 481 } 482 } 483 484 void 485 oea_iobat_remove(paddr_t pa) 486 { 487 register_t batu; 488 int i, n; 489 490 n = pa >> ADDR_SR_SHFT; 491 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 492 !BAT_VALID_P(battable[n].batu, PSL_PR)) 493 return; 494 battable[n].batl = 0; 495 battable[n].batu = 0; 496 #define BAT_RESET(n) \ 497 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 498 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 499 500 for (i=1 ; i<4 ; i++) { 501 switch (i) { 502 case 1: 503 BATU_GET(1, batu); 504 if (BAT_VA_MATCH_P(batu, pa) && 505 BAT_VALID_P(batu, PSL_PR)) 506 BAT_RESET(1); 507 break; 508 case 2: 509 BATU_GET(2, batu); 510 if (BAT_VA_MATCH_P(batu, pa) && 511 BAT_VALID_P(batu, PSL_PR)) 512 BAT_RESET(2); 513 break; 514 case 3: 515 BATU_GET(3, batu); 516 if (BAT_VA_MATCH_P(batu, pa) && 517 BAT_VALID_P(batu, PSL_PR)) 518 BAT_RESET(3); 519 break; 520 default: 521 break; 522 } 523 } 524 } 525 526 void 527 oea_batinit(paddr_t pa, ...) 528 { 529 struct mem_region *allmem, *availmem, *mp; 530 unsigned int cpuvers; 531 register_t msr = mfmsr(); 532 va_list ap; 533 534 cpuvers = mfpvr() >> 16; 535 536 /* 537 * Initialize BAT registers to unmapped to not generate 538 * overlapping mappings below. 539 * 540 * The 601's implementation differs in the Valid bit being situated 541 * in the lower BAT register, and in being a unified BAT only whose 542 * four entries are accessed through the IBAT[0-3] SPRs. 543 * 544 * Also, while the 601 does distinguish between supervisor/user 545 * protection keys, it does _not_ distinguish between validity in 546 * supervisor/user mode. 547 */ 548 if ((msr & (PSL_IR|PSL_DR)) == 0) { 549 #ifdef PPC_OEA601 550 if (cpuvers == MPC601) { 551 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 552 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 553 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 554 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 555 } else 556 #endif /* PPC_OEA601 */ 557 { 558 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 559 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 560 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 561 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 562 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 563 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 564 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 565 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 566 } 567 } 568 569 /* 570 * Set up BAT to map physical memory 571 */ 572 #ifdef PPC_OEA601 573 if (cpuvers == MPC601) { 574 int i; 575 576 /* 577 * Set up battable to map the lowest 256 MB area. 578 * Map the lowest 32 MB area via BAT[0-3]; 579 * BAT[01] are fixed, BAT[23] are floating. 580 */ 581 for (i = 0; i < 32; i++) { 582 battable[i].batl = BATL601(i << 23, 583 BAT601_BSM_8M, BAT601_V); 584 battable[i].batu = BATU601(i << 23, 585 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 586 } 587 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 588 :: "r"(battable[0x00000000 >> 23].batl), 589 "r"(battable[0x00000000 >> 23].batu)); 590 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 591 :: "r"(battable[0x00800000 >> 23].batl), 592 "r"(battable[0x00800000 >> 23].batu)); 593 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 594 :: "r"(battable[0x01000000 >> 23].batl), 595 "r"(battable[0x01000000 >> 23].batu)); 596 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 597 :: "r"(battable[0x01800000 >> 23].batl), 598 "r"(battable[0x01800000 >> 23].batu)); 599 } else 600 #endif /* PPC_OEA601 */ 601 { 602 /* 603 * Set up BAT0 to only map the lowest 256 MB area 604 */ 605 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 606 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 607 608 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 609 "mtdbatl 0,%0; mtdbatu 0,%1;" 610 :: "r"(battable[0].batl), "r"(battable[0].batu)); 611 } 612 613 /* 614 * Now setup other fixed bat registers 615 * 616 * Note that we still run in real mode, and the BAT 617 * registers were cleared above. 618 */ 619 620 va_start(ap, pa); 621 622 /* 623 * Add any I/O BATs specificed; 624 * use I/O segments on the BAT-starved 601. 625 */ 626 #ifdef PPC_OEA601 627 if (cpuvers == MPC601) { 628 while (pa != 0) { 629 register_t len = va_arg(ap, register_t); 630 mpc601_ioseg_add(pa, len); 631 pa = va_arg(ap, paddr_t); 632 } 633 } else 634 #endif 635 { 636 while (pa != 0) { 637 register_t len = va_arg(ap, register_t); 638 oea_iobat_add(pa, len); 639 pa = va_arg(ap, paddr_t); 640 } 641 } 642 643 va_end(ap); 644 645 /* 646 * Set up battable to map all RAM regions. 647 * This is here because mem_regions() call needs bat0 set up. 648 */ 649 mem_regions(&allmem, &availmem); 650 #ifdef PPC_OEA601 651 if (cpuvers == MPC601) { 652 for (mp = allmem; mp->size; mp++) { 653 paddr_t paddr = mp->start & 0xff800000; 654 paddr_t end = mp->start + mp->size; 655 656 do { 657 u_int ix = paddr >> 23; 658 659 battable[ix].batl = 660 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 661 battable[ix].batu = 662 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 663 paddr += (1 << 23); 664 } while (paddr < end); 665 } 666 } else 667 #endif 668 { 669 for (mp = allmem; mp->size; mp++) { 670 paddr_t paddr = mp->start & 0xf0000000; 671 paddr_t end = mp->start + mp->size; 672 673 do { 674 u_int ix = paddr >> 28; 675 676 battable[ix].batl = 677 BATL(paddr, BAT_M, BAT_PP_RW); 678 battable[ix].batu = 679 BATU(paddr, BAT_BL_256M, BAT_Vs); 680 paddr += SEGMENT_LENGTH; 681 } while (paddr < end); 682 } 683 } 684 } 685 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 686 687 void 688 oea_install_extint(void (*handler)(void)) 689 { 690 extern int extint[], extsize[]; 691 extern int extint_call[]; 692 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 693 int omsr, msr; 694 695 #ifdef DIAGNOSTIC 696 if (offset > 0x1ffffff) 697 panic("install_extint: %p too far away (%#lx)", handler, 698 (unsigned long) offset); 699 #endif 700 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 701 : "=r" (omsr), "=r" (msr) 702 : "K" ((u_short)~PSL_EE)); 703 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 704 __syncicache((void *)extint_call, sizeof extint_call[0]); 705 #ifdef PPC_HIGH_VEC 706 memcpy((void *)(EXC_HIGHVEC + EXC_EXI), extint, (size_t)extsize); 707 __syncicache((void *)(EXC_HIGHVEC + EXC_EXI), (int)extsize); 708 #else 709 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 710 __syncicache((void *)EXC_EXI, (int)extsize); 711 #endif 712 __asm volatile ("mtmsr %0" :: "r"(omsr)); 713 } 714 715 /* 716 * Machine dependent startup code. 717 */ 718 void 719 oea_startup(const char *model) 720 { 721 uintptr_t sz; 722 void *v; 723 vaddr_t minaddr, maxaddr; 724 char pbuf[9]; 725 u_int i; 726 727 KASSERT(curcpu() != NULL); 728 KASSERT(lwp0.l_cpu != NULL); 729 KASSERT(curcpu()->ci_intstk != 0); 730 KASSERT(curcpu()->ci_intrdepth == -1); 731 732 /* 733 * If the msgbuf is not in segment 0, allocate KVA for it and access 734 * it via mapped pages. [This prevents unneeded BAT switches.] 735 */ 736 sz = round_page(MSGBUFSIZE); 737 v = (void *) msgbuf_paddr; 738 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 739 minaddr = 0; 740 if (uvm_map(kernel_map, &minaddr, sz, 741 NULL, UVM_UNKNOWN_OFFSET, 0, 742 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 743 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 744 panic("startup: cannot allocate VM for msgbuf"); 745 v = (void *)minaddr; 746 for (i = 0; i < sz; i += PAGE_SIZE) { 747 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 748 VM_PROT_READ|VM_PROT_WRITE); 749 } 750 pmap_update(pmap_kernel()); 751 } 752 initmsgbuf(v, sz); 753 754 printf("%s%s", copyright, version); 755 if (model != NULL) 756 printf("Model: %s\n", model); 757 cpu_identify(NULL, 0); 758 759 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 760 printf("total memory = %s\n", pbuf); 761 762 /* 763 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 764 * the bufpages are allocated in case they overlap since it's not 765 * fatal if we can't allocate these. 766 */ 767 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 768 int error; 769 minaddr = 0xDEAC0000; 770 error = uvm_map(kernel_map, &minaddr, 0x30000, 771 NULL, UVM_UNKNOWN_OFFSET, 0, 772 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 773 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 774 if (error != 0 || minaddr != 0xDEAC0000) 775 printf("oea_startup: failed to allocate DEAD " 776 "ZONE: error=%d\n", error); 777 } 778 779 minaddr = 0; 780 781 /* 782 * Allocate a submap for physio 783 */ 784 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 785 VM_PHYS_SIZE, 0, false, NULL); 786 787 #ifndef PMAP_MAP_POOLPAGE 788 /* 789 * No need to allocate an mbuf cluster submap. Mbuf clusters 790 * are allocated via the pool allocator, and we use direct-mapped 791 * pool pages. 792 */ 793 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 794 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 795 #endif 796 797 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 798 printf("avail memory = %s\n", pbuf); 799 } 800 801 /* 802 * Crash dump handling. 803 */ 804 805 void 806 oea_dumpsys(void) 807 { 808 printf("dumpsys: TBD\n"); 809 } 810 811 /* 812 * Convert kernel VA to physical address 813 */ 814 paddr_t 815 kvtop(void *addr) 816 { 817 vaddr_t va; 818 paddr_t pa; 819 uintptr_t off; 820 extern char end[]; 821 822 if (addr < (void *)end) 823 return (paddr_t)addr; 824 825 va = trunc_page((vaddr_t)addr); 826 off = (uintptr_t)addr - va; 827 828 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 829 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 830 return (paddr_t)addr; 831 } 832 833 return(pa + off); 834 } 835 836 /* 837 * Allocate vm space and mapin the I/O address 838 */ 839 void * 840 mapiodev(paddr_t pa, psize_t len) 841 { 842 paddr_t faddr; 843 vaddr_t taddr, va; 844 int off; 845 846 faddr = trunc_page(pa); 847 off = pa - faddr; 848 len = round_page(off + len); 849 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 850 851 if (va == 0) 852 return NULL; 853 854 for (; len > 0; len -= PAGE_SIZE) { 855 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 856 faddr += PAGE_SIZE; 857 taddr += PAGE_SIZE; 858 } 859 pmap_update(pmap_kernel()); 860 return (void *)(va + off); 861 } 862 863 void 864 unmapiodev(vaddr_t va, vsize_t len) 865 { 866 paddr_t faddr; 867 868 if (! va) 869 return; 870 871 faddr = trunc_page(va); 872 len = round_page(va - faddr + len); 873 874 pmap_kremove(faddr, len); 875 pmap_update(pmap_kernel()); 876 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 877 } 878 879 void 880 trap0(void *lr) 881 { 882 panic("call to null-ptr from %p", lr); 883 } 884
Indexes created Mon Oct 20 16:09:52 GMT 2025