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oea_machdep.c revision 1.46.18.2
      1 /*	$NetBSD: oea_machdep.c,v 1.46.18.2 2011/01/17 07:45:59 matt Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 2002 Matt Thomas
      5  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
      6  * Copyright (C) 1995, 1996 TooLs GmbH.
      7  * All rights reserved.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed by TooLs GmbH.
     20  * 4. The name of TooLs GmbH may not be used to endorse or promote products
     21  *    derived from this software without specific prior written permission.
     22  *
     23  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
     24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     26  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     28  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     29  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     30  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     31  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     32  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33  */
     34 
     35 #include <sys/cdefs.h>
     36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.46.18.2 2011/01/17 07:45:59 matt Exp $");
     37 
     38 #include "opt_ppcarch.h"
     39 #include "opt_compat_netbsd.h"
     40 #include "opt_ddb.h"
     41 #include "opt_kgdb.h"
     42 #include "opt_ipkdb.h"
     43 #include "opt_multiprocessor.h"
     44 #include "opt_altivec.h"
     45 
     46 #include <sys/param.h>
     47 #include <sys/buf.h>
     48 #include <sys/exec.h>
     49 #include <sys/malloc.h>
     50 #include <sys/mbuf.h>
     51 #include <sys/mount.h>
     52 #include <sys/msgbuf.h>
     53 #include <sys/proc.h>
     54 #include <sys/reboot.h>
     55 #include <sys/syscallargs.h>
     56 #include <sys/syslog.h>
     57 #include <sys/systm.h>
     58 #include <sys/kernel.h>
     59 #include <sys/user.h>
     60 #include <sys/boot_flag.h>
     61 
     62 #include <uvm/uvm_extern.h>
     63 
     64 #include <net/netisr.h>
     65 
     66 #ifdef DDB
     67 #include <machine/db_machdep.h>
     68 #include <ddb/db_extern.h>
     69 #endif
     70 
     71 #ifdef KGDB
     72 #include <sys/kgdb.h>
     73 #endif
     74 
     75 #ifdef IPKDB
     76 #include <ipkdb/ipkdb.h>
     77 #endif
     78 
     79 #include <powerpc/oea/bat.h>
     80 #include <powerpc/oea/sr_601.h>
     81 #include <powerpc/oea/cpufeat.h>
     82 #include <powerpc/trap.h>
     83 #include <powerpc/stdarg.h>
     84 #include <powerpc/spr.h>
     85 #include <powerpc/pte.h>
     86 #include <powerpc/altivec.h>
     87 #include <machine/powerpc.h>
     88 #include <powerpc/oea/spr.h>
     89 
     90 char machine[] = MACHINE;		/* from <machine/param.h> */
     91 char machine_arch[] = MACHINE_ARCH;	/* from <machine/param.h> */
     92 
     93 struct vm_map *mb_map = NULL;
     94 struct vm_map *phys_map = NULL;
     95 
     96 /*
     97  * Global variables used here and there
     98  */
     99 extern struct user *proc0paddr;
    100 
    101 static void trap0(void *);
    102 
    103 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */
    104 struct bat battable[512];
    105 
    106 register_t iosrtable[16];	/* I/O segments, for kernel_pmap setup */
    107 paddr_t msgbuf_paddr;
    108 
    109 void
    110 oea_init(void (*handler)(void))
    111 {
    112 	extern int trapcode[], trapsize[];
    113 	extern int sctrap[], scsize[];
    114 	extern int alitrap[], alisize[];
    115 	extern int dsitrap[], dsisize[];
    116 	extern int trapstart[], trapend[];
    117 #ifdef PPC_OEA601
    118 	extern int dsi601trap[], dsi601size[];
    119 #endif
    120 	extern int decrint[], decrsize[];
    121 	extern int tlbimiss[], tlbimsize[];
    122 	extern int tlbdlmiss[], tlbdlmsize[];
    123 	extern int tlbdsmiss[], tlbdsmsize[];
    124 #if defined(DDB) || defined(KGDB)
    125 	extern int ddblow[], ddbsize[];
    126 #endif
    127 #ifdef IPKDB
    128 	extern int ipkdblow[], ipkdbsize[];
    129 #endif
    130 #ifdef ALTIVEC
    131 	register_t msr;
    132 #endif
    133 	uintptr_t exc, exc_base;
    134 #if defined(ALTIVEC) || defined(PPC_OEA)
    135 	register_t scratch;
    136 #endif
    137 	unsigned int cpuvers;
    138 	size_t size;
    139 	struct cpu_info * const ci = &cpu_info[0];
    140 
    141 #ifdef PPC_HIGH_VEC
    142 	exc_base = EXC_HIGHVEC;
    143 #else
    144 	exc_base = 0;
    145 #endif
    146 	mtspr(SPR_SPRG0, ci);
    147 	cpuvers = mfpvr() >> 16;
    148 
    149 	/*
    150 	 * Initialize proc0 and current pcb and pmap pointers.
    151 	 */
    152 	KASSERT(ci != NULL);
    153 	KASSERT(curcpu() == ci);
    154 	lwp0.l_cpu = ci;
    155 	lwp0.l_addr = proc0paddr;
    156 	lwp0.l_md.md_fpucpu = ci;
    157 	lwp0.l_md.md_utf = trapframe(&lwp0);
    158 	memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr);
    159 	KASSERT(lwp0.l_cpu != NULL);
    160 
    161 	curpcb = &proc0paddr->u_pcb;
    162 	memset(curpcb, 0, sizeof(*curpcb));
    163 #ifdef ALTIVEC
    164 	/*
    165 	 * Initialize the vectors with NaNs
    166 	 */
    167 	for (scratch = 0; scratch < 32; scratch++) {
    168 		curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD;
    169 		curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD;
    170 		curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD;
    171 		curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD;
    172 	}
    173 	lwp0.l_md.md_veccpu = ci;
    174 	ci->ci_veclwp = &lwp0;
    175 #endif
    176 #ifdef PPC_HAVE_FPU
    177 	lwp0.l_md.md_fpucpu = ci;
    178 	ci->ci_fpulwp = &lwp0;
    179 #endif
    180 	curpm = curpcb->pcb_pm = pmap_kernel();
    181 
    182 	/*
    183 	 * Cause a PGM trap if we branch to 0.
    184 	 *
    185 	 * XXX GCC4.1 complains about memset on address zero, so
    186 	 * don't use the builtin.
    187 	 */
    188 #undef memset
    189 	memset(0, 0, 0x100);
    190 
    191 	/*
    192 	 * Set up trap vectors.  Don't assume vectors are on 0x100.
    193 	 */
    194 	for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) {
    195 		switch (exc - exc_base) {
    196 		default:
    197 			size = (size_t)trapsize;
    198 			memcpy((void *)exc, trapcode, size);
    199 			break;
    200 #if 0
    201 		case EXC_EXI:
    202 			/*
    203 			 * This one is (potentially) installed during autoconf
    204 			 */
    205 			break;
    206 #endif
    207 		case EXC_SC:
    208 			size = (size_t)scsize;
    209 			memcpy((void *)exc, sctrap, size);
    210 			break;
    211 		case EXC_ALI:
    212 			size = (size_t)alisize;
    213 			memcpy((void *)exc, alitrap, size);
    214 			break;
    215 		case EXC_DSI:
    216 #ifdef PPC_OEA601
    217 			if (cpuvers == MPC601) {
    218 				size = (size_t)dsi601size;
    219 				memcpy((void *)exc, dsi601trap, size);
    220 				break;
    221 			} else
    222 #endif /* PPC_OEA601 */
    223 			if (oeacpufeat & OEACPU_NOBAT) {
    224 				size = (size_t)alisize;
    225 				memcpy((void *)exc, alitrap, size);
    226 			} else {
    227 				size = (size_t)dsisize;
    228 				memcpy((void *)exc, dsitrap, size);
    229 			}
    230 			break;
    231 		case EXC_DECR:
    232 			size = (size_t)decrsize;
    233 			memcpy((void *)exc, decrint, size);
    234 			break;
    235 		case EXC_IMISS:
    236 			size = (size_t)tlbimsize;
    237 			memcpy((void *)exc, tlbimiss, size);
    238 			break;
    239 		case EXC_DLMISS:
    240 			size = (size_t)tlbdlmsize;
    241 			memcpy((void *)exc, tlbdlmiss, size);
    242 			break;
    243 		case EXC_DSMISS:
    244 			size = (size_t)tlbdsmsize;
    245 			memcpy((void *)exc, tlbdsmiss, size);
    246 			break;
    247 		case EXC_PERF:
    248 			size = (size_t)trapsize;
    249 			memcpy((void *)exc, trapcode, size);
    250 			memcpy((void *)(exc_base + EXC_VEC),  trapcode, size);
    251 			break;
    252 #if defined(DDB) || defined(IPKDB) || defined(KGDB)
    253 		case EXC_RUNMODETRC:
    254 #ifdef PPC_OEA601
    255 			if (cpuvers != MPC601) {
    256 #endif
    257 				size = (size_t)trapsize;
    258 				memcpy((void *)exc, trapcode, size);
    259 				break;
    260 #ifdef PPC_OEA601
    261 			}
    262 			/* FALLTHROUGH */
    263 #endif
    264 		case EXC_PGM:
    265 		case EXC_TRC:
    266 		case EXC_BPT:
    267 #if defined(DDB) || defined(KGDB)
    268 			size = (size_t)ddbsize;
    269 			memcpy((void *)exc, ddblow, size);
    270 #if defined(IPKDB)
    271 #error "cannot enable IPKDB with DDB or KGDB"
    272 #endif
    273 #else
    274 			size = (size_t)ipkdbsize;
    275 			memcpy((void *)exc, ipkdblow, size);
    276 #endif
    277 			break;
    278 #endif /* DDB || IPKDB || KGDB */
    279 		}
    280 #if 0
    281 		exc += roundup(size, 32);
    282 #endif
    283 	}
    284 
    285 	/*
    286 	 * Install a branch absolute to trap0 to force a panic.
    287 	 */
    288 	if ((uintptr_t)trap0 < 0x2000000) {
    289 		*(uint32_t *) 0 = 0x7c6802a6;
    290 		*(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0;
    291 	}
    292 
    293 	/*
    294 	 * Get the cache sizes because install_extint calls __syncicache.
    295 	 */
    296 	cpu_probe_cache();
    297 
    298 #define	MxSPR_MASK	0x7c1fffff
    299 #define	MFSPR_MQ	0x7c0002a6
    300 #define	MTSPR_MQ	0x7c0003a6
    301 #define	MTSPR_IBAT0L	0x7c1183a6
    302 #define	MTSPR_IBAT1L	0x7c1383a6
    303 #define	NOP		0x60000000
    304 #define	B		0x48000000
    305 #define	TLBSYNC		0x7c00046c
    306 #define	SYNC		0x7c0004ac
    307 
    308 #ifdef ALTIVEC
    309 #define	MFSPR_VRSAVE	0x7c0042a6
    310 #define	MTSPR_VRSAVE	0x7c0043a6
    311 
    312 	/*
    313 	 * Try to set the VEC bit in the MSR.  If it doesn't get set, we are
    314 	 * not on a AltiVec capable processor.
    315 	 */
    316 	__asm volatile (
    317 	    "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; "
    318 		"mfmsr %1; mtmsr %0; isync"
    319 	    :	"=r"(msr), "=r"(scratch)
    320 	    :	"J"(PSL_VEC));
    321 
    322 	/*
    323 	 * If we aren't on an AltiVec capable processor, we need to zap any of
    324 	 * the sequences we save/restore the VRSAVE SPR into NOPs.
    325 	 */
    326 	if (scratch & PSL_VEC) {
    327 		cpu_altivec = 1;
    328 	} else {
    329 		int *ip = trapstart;
    330 
    331 		for (; ip < trapend; ip++) {
    332 			if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) {
    333 				ip[0] = NOP;	/* mfspr */
    334 				ip[1] = NOP;	/* stw */
    335 			} else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) {
    336 				ip[-1] = NOP;	/* lwz */
    337 				ip[0] = NOP;	/* mtspr */
    338 			}
    339 		}
    340 	}
    341 #endif
    342 
    343 	/* XXX It would seem like this code could be elided ifndef 601, but
    344 	 * doing so breaks my power3 machine.
    345 	 */
    346 	/*
    347 	 * If we aren't on a MPC601 processor, we need to zap any of the
    348 	 * sequences we save/restore the MQ SPR into NOPs, and skip over the
    349 	 * sequences where we zap/restore BAT registers on kernel exit/entry.
    350 	 */
    351 	if (cpuvers != MPC601) {
    352 		int *ip = trapstart;
    353 
    354 		for (; ip < trapend; ip++) {
    355 			if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) {
    356 				ip[0] = NOP;	/* mfspr */
    357 				ip[1] = NOP;	/* stw */
    358 			} else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) {
    359 				ip[-1] = NOP;	/* lwz */
    360 				ip[0] = NOP;	/* mtspr */
    361 			} else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) {
    362 				if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L)
    363 					ip[-1] = B | 0x14;	/* li */
    364 				else
    365 					ip[-4] = B | 0x24;	/* lis */
    366 			}
    367 		}
    368 	}
    369 
    370 	/*
    371 	 * Sync the changed instructions.
    372 	 */
    373 	__syncicache((void *) trapstart,
    374 	    (uintptr_t) trapend - (uintptr_t) trapstart);
    375 #ifdef PPC_OEA601
    376 
    377 	/*
    378 	 * If we are on a MPC601 processor, we need to zap any tlbsync
    379 	 * instructions into sync.  This differs from the above in
    380 	 * examing all kernel text, as opposed to just the exception handling.
    381 	 * We sync the icache on every instruction found since there are
    382 	 * only very few of them.
    383 	 */
    384 	if (cpuvers == MPC601) {
    385 		extern int kernel_text[], etext[];
    386 		int *ip;
    387 
    388 		for (ip = kernel_text; ip < etext; ip++)
    389 			if (*ip == TLBSYNC) {
    390 				*ip = SYNC;
    391 				__syncicache(ip, sizeof(*ip));
    392 		}
    393 	}
    394 #endif /* PPC_OEA601 */
    395 
    396         /*
    397 	 * Configure a PSL user mask matching this processor.
    398  	 */
    399 	cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
    400 	cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE;
    401 #ifdef PPC_OEA601
    402 	if (cpuvers == MPC601) {
    403 		cpu_psluserset &= PSL_601_MASK;
    404 		cpu_pslusermod &= PSL_601_MASK;
    405 	}
    406 #endif
    407 #ifdef ALTIVEC
    408 	if (cpu_altivec)
    409 		cpu_pslusermod |= PSL_VEC;
    410 #endif
    411 #ifdef PPC_HIGH_VEC
    412 	cpu_psluserset |= PSL_IP;	/* XXX ok? */
    413 #endif
    414 
    415 	/*
    416 	 * external interrupt handler install
    417 	 */
    418 	if (handler)
    419 		oea_install_extint(handler);
    420 
    421 	__syncicache((void *)exc_base, EXC_LAST + 0x100);
    422 
    423 	/*
    424 	 * Now enable translation (and machine checks/recoverable interrupts).
    425 	 */
    426 #ifdef PPC_OEA
    427 	__asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync"
    428 	    : "=r"(scratch)
    429 	    : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
    430 #endif
    431 
    432 	KASSERT(curcpu() == ci);
    433 }
    434 
    435 #ifdef PPC_OEA601
    436 void
    437 mpc601_ioseg_add(paddr_t pa, register_t len)
    438 {
    439 	const u_int i = pa >> ADDR_SR_SHFT;
    440 
    441 	if (len != BAT_BL_256M)
    442 		panic("mpc601_ioseg_add: len != 256M");
    443 
    444 	/*
    445 	 * Translate into an I/O segment, load it, and stash away for use
    446 	 * in pmap_bootstrap().
    447 	 */
    448 	iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i);
    449 	__asm volatile ("mtsrin %0,%1"
    450 	    ::	"r"(iosrtable[i]),
    451 		"r"(pa));
    452 }
    453 #endif /* PPC_OEA601 */
    454 
    455 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE)
    456 void
    457 oea_iobat_add(paddr_t pa, register_t len)
    458 {
    459 	static int n = 1;
    460 	const u_int i = pa >> 28;
    461 	battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW);
    462 	battable[i].batu = BATU(pa, len, BAT_Vs);
    463 
    464 	/*
    465 	 * Let's start loading the BAT registers.
    466 	 */
    467 	switch (n) {
    468 	case 1:
    469 		__asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;"
    470 		    ::	"r"(battable[i].batl),
    471 			"r"(battable[i].batu));
    472 		n = 2;
    473 		break;
    474 	case 2:
    475 		__asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;"
    476 		    ::	"r"(battable[i].batl),
    477 			"r"(battable[i].batu));
    478 		n = 3;
    479 		break;
    480 	case 3:
    481 		__asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;"
    482 		    ::	"r"(battable[i].batl),
    483 			"r"(battable[i].batu));
    484 		n = 4;
    485 		break;
    486 	default:
    487 		break;
    488 	}
    489 }
    490 
    491 void
    492 oea_iobat_remove(paddr_t pa)
    493 {
    494 	register_t batu;
    495 	int i, n;
    496 
    497 	n = pa >> ADDR_SR_SHFT;
    498 	if (!BAT_VA_MATCH_P(battable[n].batu, pa) ||
    499 	    !BAT_VALID_P(battable[n].batu, PSL_PR))
    500 		return;
    501 	battable[n].batl = 0;
    502 	battable[n].batu = 0;
    503 #define	BAT_RESET(n) \
    504 	__asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0))
    505 #define	BATU_GET(n, r)	__asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n))
    506 
    507 	for (i=1 ; i<4 ; i++) {
    508 		switch (i) {
    509 		case 1:
    510 			BATU_GET(1, batu);
    511 			if (BAT_VA_MATCH_P(batu, pa) &&
    512 			    BAT_VALID_P(batu, PSL_PR))
    513 				BAT_RESET(1);
    514 			break;
    515 		case 2:
    516 			BATU_GET(2, batu);
    517 			if (BAT_VA_MATCH_P(batu, pa) &&
    518 			    BAT_VALID_P(batu, PSL_PR))
    519 				BAT_RESET(2);
    520 			break;
    521 		case 3:
    522 			BATU_GET(3, batu);
    523 			if (BAT_VA_MATCH_P(batu, pa) &&
    524 			    BAT_VALID_P(batu, PSL_PR))
    525 				BAT_RESET(3);
    526 			break;
    527 		default:
    528 			break;
    529 		}
    530 	}
    531 }
    532 
    533 void
    534 oea_batinit(paddr_t pa, ...)
    535 {
    536 	struct mem_region *allmem, *availmem, *mp;
    537 	unsigned int cpuvers;
    538 	register_t msr = mfmsr();
    539 	va_list ap;
    540 
    541 	cpuvers = mfpvr() >> 16;
    542 
    543 	/*
    544 	 * Initialize BAT registers to unmapped to not generate
    545 	 * overlapping mappings below.
    546 	 *
    547 	 * The 601's implementation differs in the Valid bit being situated
    548 	 * in the lower BAT register, and in being a unified BAT only whose
    549 	 * four entries are accessed through the IBAT[0-3] SPRs.
    550 	 *
    551 	 * Also, while the 601 does distinguish between supervisor/user
    552 	 * protection keys, it does _not_ distinguish between validity in
    553 	 * supervisor/user mode.
    554 	 */
    555 	if ((msr & (PSL_IR|PSL_DR)) == 0) {
    556 #ifdef PPC_OEA601
    557 		if (cpuvers == MPC601) {
    558 			__asm volatile ("mtibatl 0,%0" :: "r"(0));
    559 			__asm volatile ("mtibatl 1,%0" :: "r"(0));
    560 			__asm volatile ("mtibatl 2,%0" :: "r"(0));
    561 			__asm volatile ("mtibatl 3,%0" :: "r"(0));
    562 		} else
    563 #endif /* PPC_OEA601 */
    564 		{
    565 			__asm volatile ("mtibatu 0,%0" :: "r"(0));
    566 			__asm volatile ("mtibatu 1,%0" :: "r"(0));
    567 			__asm volatile ("mtibatu 2,%0" :: "r"(0));
    568 			__asm volatile ("mtibatu 3,%0" :: "r"(0));
    569 			__asm volatile ("mtdbatu 0,%0" :: "r"(0));
    570 			__asm volatile ("mtdbatu 1,%0" :: "r"(0));
    571 			__asm volatile ("mtdbatu 2,%0" :: "r"(0));
    572 			__asm volatile ("mtdbatu 3,%0" :: "r"(0));
    573 		}
    574 	}
    575 
    576 	/*
    577 	 * Set up BAT to map physical memory
    578 	 */
    579 #ifdef PPC_OEA601
    580 	if (cpuvers == MPC601) {
    581 		int i;
    582 
    583 		/*
    584 		 * Set up battable to map the lowest 256 MB area.
    585 		 * Map the lowest 32 MB area via BAT[0-3];
    586 		 * BAT[01] are fixed, BAT[23] are floating.
    587 		 */
    588 		for (i = 0; i < 32; i++) {
    589 			battable[i].batl = BATL601(i << 23,
    590 			   BAT601_BSM_8M, BAT601_V);
    591 			battable[i].batu = BATU601(i << 23,
    592 			    BAT601_M, BAT601_Ku, BAT601_PP_NONE);
    593 		}
    594 		__asm volatile ("mtibatu 0,%1; mtibatl 0,%0"
    595 		    :: "r"(battable[0x00000000 >> 23].batl),
    596 		       "r"(battable[0x00000000 >> 23].batu));
    597 		__asm volatile ("mtibatu 1,%1; mtibatl 1,%0"
    598 		    :: "r"(battable[0x00800000 >> 23].batl),
    599 		       "r"(battable[0x00800000 >> 23].batu));
    600 		__asm volatile ("mtibatu 2,%1; mtibatl 2,%0"
    601 		    :: "r"(battable[0x01000000 >> 23].batl),
    602 		       "r"(battable[0x01000000 >> 23].batu));
    603 		__asm volatile ("mtibatu 3,%1; mtibatl 3,%0"
    604 		    :: "r"(battable[0x01800000 >> 23].batl),
    605 		       "r"(battable[0x01800000 >> 23].batu));
    606 	} else
    607 #endif /* PPC_OEA601 */
    608 	{
    609 		/*
    610 		 * Set up BAT0 to only map the lowest 256 MB area
    611 		 */
    612 		battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
    613 		battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
    614 
    615 		__asm volatile ("mtibatl 0,%0; mtibatu 0,%1;"
    616 				  "mtdbatl 0,%0; mtdbatu 0,%1;"
    617 		    ::	"r"(battable[0].batl), "r"(battable[0].batu));
    618 	}
    619 
    620 	/*
    621 	 * Now setup other fixed bat registers
    622 	 *
    623 	 * Note that we still run in real mode, and the BAT
    624 	 * registers were cleared above.
    625 	 */
    626 
    627 	va_start(ap, pa);
    628 
    629 	/*
    630 	 * Add any I/O BATs specificed;
    631 	 * use I/O segments on the BAT-starved 601.
    632 	 */
    633 #ifdef PPC_OEA601
    634 	if (cpuvers == MPC601) {
    635 		while (pa != 0) {
    636 			register_t len = va_arg(ap, register_t);
    637 			mpc601_ioseg_add(pa, len);
    638 			pa = va_arg(ap, paddr_t);
    639 		}
    640 	} else
    641 #endif
    642 	{
    643 		while (pa != 0) {
    644 			register_t len = va_arg(ap, register_t);
    645 			oea_iobat_add(pa, len);
    646 			pa = va_arg(ap, paddr_t);
    647 		}
    648 	}
    649 
    650 	va_end(ap);
    651 
    652 	/*
    653 	 * Set up battable to map all RAM regions.
    654 	 * This is here because mem_regions() call needs bat0 set up.
    655 	 */
    656 	mem_regions(&allmem, &availmem);
    657 #ifdef PPC_OEA601
    658 	if (cpuvers == MPC601) {
    659 		for (mp = allmem; mp->size; mp++) {
    660 			paddr_t paddr = mp->start & 0xff800000;
    661 			paddr_t end = mp->start + mp->size;
    662 
    663 			do {
    664 				u_int ix = paddr >> 23;
    665 
    666 				battable[ix].batl =
    667 				    BATL601(paddr, BAT601_BSM_8M, BAT601_V);
    668 				battable[ix].batu =
    669 				    BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE);
    670 				paddr += (1 << 23);
    671 			} while (paddr < end);
    672 		}
    673 	} else
    674 #endif
    675 	{
    676 		for (mp = allmem; mp->size; mp++) {
    677 			paddr_t paddr = mp->start & 0xf0000000;
    678 			paddr_t end = mp->start + mp->size;
    679 
    680 			do {
    681 				u_int ix = paddr >> 28;
    682 
    683 				battable[ix].batl =
    684 				    BATL(paddr, BAT_M, BAT_PP_RW);
    685 				battable[ix].batu =
    686 				    BATU(paddr, BAT_BL_256M, BAT_Vs);
    687 				paddr += SEGMENT_LENGTH;
    688 			} while (paddr < end);
    689 		}
    690 	}
    691 }
    692 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */
    693 
    694 void
    695 oea_install_extint(void (*handler)(void))
    696 {
    697 	extern int extint[], extsize[];
    698 	extern int extint_call[];
    699 	uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call;
    700 	int omsr, msr;
    701 
    702 #ifdef	DIAGNOSTIC
    703 	if (offset > 0x1ffffff)
    704 		panic("install_extint: %p too far away (%#lx)", handler,
    705 		    (unsigned long) offset);
    706 #endif
    707 	__asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1"
    708 	    :	"=r" (omsr), "=r" (msr)
    709 	    :	"K" ((u_short)~PSL_EE));
    710 	extint_call[0] = (extint_call[0] & 0xfc000003) | offset;
    711 	__syncicache((void *)extint_call, sizeof extint_call[0]);
    712 #ifdef PPC_HIGH_VEC
    713 	memcpy((void *)(EXC_HIGHVEC + EXC_EXI), extint, (size_t)extsize);
    714 	__syncicache((void *)(EXC_HIGHVEC + EXC_EXI), (int)extsize);
    715 #else
    716 	memcpy((void *)EXC_EXI, extint, (size_t)extsize);
    717 	__syncicache((void *)EXC_EXI, (int)extsize);
    718 #endif
    719 	__asm volatile ("mtmsr %0" :: "r"(omsr));
    720 }
    721 
    722 /*
    723  * Machine dependent startup code.
    724  */
    725 void
    726 oea_startup(const char *model)
    727 {
    728 	uintptr_t sz;
    729 	void *v;
    730 	vaddr_t minaddr, maxaddr;
    731 	char pbuf[9];
    732 	u_int i;
    733 
    734 	KASSERT(curcpu() != NULL);
    735 	KASSERT(lwp0.l_cpu != NULL);
    736 	KASSERT(curcpu()->ci_idepth == -1);
    737 
    738 	/*
    739 	 * If the msgbuf is not in segment 0, allocate KVA for it and access
    740 	 * it via mapped pages.  [This prevents unneeded BAT switches.]
    741 	 */
    742         sz = round_page(MSGBUFSIZE);
    743 	v = (void *) msgbuf_paddr;
    744 	if (msgbuf_paddr + sz > SEGMENT_LENGTH) {
    745 		minaddr = 0;
    746 		if (uvm_map(kernel_map, &minaddr, sz,
    747 				NULL, UVM_UNKNOWN_OFFSET, 0,
    748 				UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE,
    749 				    UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0)
    750 			panic("startup: cannot allocate VM for msgbuf");
    751 		v = (void *)minaddr;
    752 		for (i = 0; i < sz; i += PAGE_SIZE) {
    753 			pmap_kenter_pa(minaddr + i, msgbuf_paddr + i,
    754 			    VM_PROT_READ|VM_PROT_WRITE);
    755 		}
    756 		pmap_update(pmap_kernel());
    757 	}
    758 	initmsgbuf(v, sz);
    759 
    760 	printf("%s%s", copyright, version);
    761 	if (model != NULL)
    762 		printf("Model: %s\n", model);
    763 	cpu_identify(NULL, 0);
    764 
    765 	format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem));
    766 	printf("total memory = %s\n", pbuf);
    767 
    768 	/*
    769 	 * Allocate away the pages that map to 0xDEA[CDE]xxxx.  Do this after
    770 	 * the bufpages are allocated in case they overlap since it's not
    771 	 * fatal if we can't allocate these.
    772 	 */
    773 	if (KERNEL_SR == 13 || KERNEL2_SR == 14) {
    774 		int error;
    775 		minaddr = 0xDEAC0000;
    776 		error = uvm_map(kernel_map, &minaddr, 0x30000,
    777 		    NULL, UVM_UNKNOWN_OFFSET, 0,
    778 		    UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE,
    779 				UVM_ADV_NORMAL, UVM_FLAG_FIXED));
    780 		if (error != 0 || minaddr != 0xDEAC0000)
    781 			printf("oea_startup: failed to allocate DEAD "
    782 			    "ZONE: error=%d\n", error);
    783 	}
    784 
    785 	minaddr = 0;
    786 
    787 	/*
    788 	 * Allocate a submap for physio
    789 	 */
    790 	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
    791 				 VM_PHYS_SIZE, 0, false, NULL);
    792 
    793 #ifndef PMAP_MAP_POOLPAGE
    794 	/*
    795 	 * No need to allocate an mbuf cluster submap.  Mbuf clusters
    796 	 * are allocated via the pool allocator, and we use direct-mapped
    797 	 * pool pages.
    798 	 */
    799 	mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
    800 	    mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL);
    801 #endif
    802 
    803 	format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
    804 	printf("avail memory = %s\n", pbuf);
    805 }
    806 
    807 /*
    808  * Crash dump handling.
    809  */
    810 
    811 void
    812 oea_dumpsys(void)
    813 {
    814 	printf("dumpsys: TBD\n");
    815 }
    816 
    817 /*
    818  * Convert kernel VA to physical address
    819  */
    820 paddr_t
    821 kvtop(void *addr)
    822 {
    823 	vaddr_t va;
    824 	paddr_t pa;
    825 	uintptr_t off;
    826 	extern char end[];
    827 
    828 	if (addr < (void *)end)
    829 		return (paddr_t)addr;
    830 
    831 	va = trunc_page((vaddr_t)addr);
    832 	off = (uintptr_t)addr - va;
    833 
    834 	if (pmap_extract(pmap_kernel(), va, &pa) == false) {
    835 		/*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/
    836 		return (paddr_t)addr;
    837 	}
    838 
    839 	return(pa + off);
    840 }
    841 
    842 /*
    843  * Allocate vm space and mapin the I/O address
    844  */
    845 void *
    846 mapiodev(paddr_t pa, psize_t len)
    847 {
    848 	paddr_t faddr;
    849 	vaddr_t taddr, va;
    850 	int off;
    851 
    852 	faddr = trunc_page(pa);
    853 	off = pa - faddr;
    854 	len = round_page(off + len);
    855 	va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY);
    856 
    857 	if (va == 0)
    858 		return NULL;
    859 
    860 	for (; len > 0; len -= PAGE_SIZE) {
    861 		pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE);
    862 		faddr += PAGE_SIZE;
    863 		taddr += PAGE_SIZE;
    864 	}
    865 	pmap_update(pmap_kernel());
    866 	return (void *)(va + off);
    867 }
    868 
    869 void
    870 unmapiodev(vaddr_t va, vsize_t len)
    871 {
    872 	paddr_t faddr;
    873 
    874 	if (! va)
    875 		return;
    876 
    877 	faddr = trunc_page(va);
    878 	len = round_page(va - faddr + len);
    879 
    880 	pmap_kremove(faddr, len);
    881 	pmap_update(pmap_kernel());
    882 	uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY);
    883 }
    884 
    885 void
    886 trap0(void *lr)
    887 {
    888 	panic("call to null-ptr from %p", lr);
    889 }
    890