oea_machdep.c revision 1.46.18.4
1 /* $NetBSD: oea_machdep.c,v 1.46.18.4 2011/01/28 04:37:25 matt Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.46.18.4 2011/01/28 04:37:25 matt Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/exec.h> 49 #include <sys/malloc.h> 50 #include <sys/mbuf.h> 51 #include <sys/mount.h> 52 #include <sys/msgbuf.h> 53 #include <sys/proc.h> 54 #include <sys/reboot.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/oea/cpufeat.h> 82 #include <powerpc/trap.h> 83 #include <powerpc/stdarg.h> 84 #include <powerpc/spr.h> 85 #include <powerpc/pte.h> 86 #include <powerpc/altivec.h> 87 #include <machine/powerpc.h> 88 #include <powerpc/oea/spr.h> 89 90 char machine[] = MACHINE; /* from <machine/param.h> */ 91 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 92 93 struct vm_map *mb_map = NULL; 94 struct vm_map *phys_map = NULL; 95 96 /* 97 * Global variables used here and there 98 */ 99 extern struct user *proc0paddr; 100 101 static void trap0(void *); 102 103 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 104 struct bat battable[BAT_VA2IDX(0xffffffff)+1]; 105 106 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 107 paddr_t msgbuf_paddr; 108 109 extern int dsitrap_fix_dbat4[]; 110 extern int dsitrap_fix_dbat5[]; 111 extern int dsitrap_fix_dbat6[]; 112 extern int dsitrap_fix_dbat7[]; 113 114 void 115 oea_init(void (*handler)(void)) 116 { 117 extern int trapcode[], trapsize[]; 118 extern int sctrap[], scsize[]; 119 extern int alitrap[], alisize[]; 120 extern int dsitrap[], dsisize[]; 121 extern int trapstart[], trapend[]; 122 #ifdef PPC_OEA601 123 extern int dsi601trap[], dsi601size[]; 124 #endif 125 extern int decrint[], decrsize[]; 126 extern int tlbimiss[], tlbimsize[]; 127 extern int tlbdlmiss[], tlbdlmsize[]; 128 extern int tlbdsmiss[], tlbdsmsize[]; 129 #if defined(DDB) || defined(KGDB) 130 extern int ddblow[], ddbsize[]; 131 #endif 132 #ifdef IPKDB 133 extern int ipkdblow[], ipkdbsize[]; 134 #endif 135 #ifdef ALTIVEC 136 register_t msr; 137 #endif 138 uintptr_t exc, exc_base; 139 #if defined(ALTIVEC) || defined(PPC_OEA) 140 register_t scratch; 141 #endif 142 unsigned int cpuvers; 143 size_t size; 144 struct cpu_info * const ci = &cpu_info[0]; 145 146 #ifdef PPC_HIGH_VEC 147 exc_base = EXC_HIGHVEC; 148 #else 149 exc_base = 0; 150 #endif 151 mtspr(SPR_SPRG0, ci); 152 cpuvers = mfpvr() >> 16; 153 154 /* 155 * Initialize proc0 and current pcb and pmap pointers. 156 */ 157 KASSERT(ci != NULL); 158 KASSERT(curcpu() == ci); 159 lwp0.l_cpu = ci; 160 lwp0.l_addr = proc0paddr; 161 lwp0.l_md.md_fpucpu = ci; 162 lwp0.l_md.md_utf = trapframe(&lwp0); 163 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 164 KASSERT(lwp0.l_cpu != NULL); 165 166 curpcb = &proc0paddr->u_pcb; 167 memset(curpcb, 0, sizeof(*curpcb)); 168 #ifdef ALTIVEC 169 /* 170 * Initialize the vectors with NaNs 171 */ 172 for (scratch = 0; scratch < 32; scratch++) { 173 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 174 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 175 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 176 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 177 } 178 lwp0.l_md.md_veccpu = ci; 179 ci->ci_veclwp = &lwp0; 180 #endif 181 #ifdef PPC_HAVE_FPU 182 lwp0.l_md.md_fpucpu = ci; 183 ci->ci_fpulwp = &lwp0; 184 #endif 185 curpm = curpcb->pcb_pm = pmap_kernel(); 186 187 /* 188 * Cause a PGM trap if we branch to 0. 189 * 190 * XXX GCC4.1 complains about memset on address zero, so 191 * don't use the builtin. 192 */ 193 #undef memset 194 memset(0, 0, 0x100); 195 196 /* 197 * Set up trap vectors. Don't assume vectors are on 0x100. 198 */ 199 for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) { 200 switch (exc - exc_base) { 201 default: 202 size = (size_t)trapsize; 203 memcpy((void *)exc, trapcode, size); 204 break; 205 #if 0 206 case EXC_EXI: 207 /* 208 * This one is (potentially) installed during autoconf 209 */ 210 break; 211 #endif 212 case EXC_SC: 213 size = (size_t)scsize; 214 memcpy((void *)exc, sctrap, size); 215 break; 216 case EXC_ALI: 217 size = (size_t)alisize; 218 memcpy((void *)exc, alitrap, size); 219 break; 220 case EXC_DSI: 221 #ifdef PPC_OEA601 222 if (cpuvers == MPC601) { 223 size = (size_t)dsi601size; 224 memcpy((void *)exc, dsi601trap, size); 225 break; 226 } else 227 #endif /* PPC_OEA601 */ 228 if (oeacpufeat & OEACPU_NOBAT) { 229 size = (size_t)alisize; 230 memcpy((void *)exc, alitrap, size); 231 } else { 232 size = (size_t)dsisize; 233 memcpy((void *)exc, dsitrap, size); 234 } 235 break; 236 case EXC_DECR: 237 size = (size_t)decrsize; 238 memcpy((void *)exc, decrint, size); 239 break; 240 case EXC_IMISS: 241 size = (size_t)tlbimsize; 242 memcpy((void *)exc, tlbimiss, size); 243 break; 244 case EXC_DLMISS: 245 size = (size_t)tlbdlmsize; 246 memcpy((void *)exc, tlbdlmiss, size); 247 break; 248 case EXC_DSMISS: 249 size = (size_t)tlbdsmsize; 250 memcpy((void *)exc, tlbdsmiss, size); 251 break; 252 case EXC_PERF: 253 size = (size_t)trapsize; 254 memcpy((void *)exc, trapcode, size); 255 memcpy((void *)(exc_base + EXC_VEC), trapcode, size); 256 break; 257 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 258 case EXC_RUNMODETRC: 259 #ifdef PPC_OEA601 260 if (cpuvers != MPC601) { 261 #endif 262 size = (size_t)trapsize; 263 memcpy((void *)exc, trapcode, size); 264 break; 265 #ifdef PPC_OEA601 266 } 267 /* FALLTHROUGH */ 268 #endif 269 case EXC_PGM: 270 case EXC_TRC: 271 case EXC_BPT: 272 #if defined(DDB) || defined(KGDB) 273 size = (size_t)ddbsize; 274 memcpy((void *)exc, ddblow, size); 275 #if defined(IPKDB) 276 #error "cannot enable IPKDB with DDB or KGDB" 277 #endif 278 #else 279 size = (size_t)ipkdbsize; 280 memcpy((void *)exc, ipkdblow, size); 281 #endif 282 break; 283 #endif /* DDB || IPKDB || KGDB */ 284 } 285 #if 0 286 exc += roundup(size, 32); 287 #endif 288 } 289 290 /* 291 * Install a branch absolute to trap0 to force a panic. 292 */ 293 if ((uintptr_t)trap0 < 0x2000000) { 294 *(uint32_t *) 0 = 0x7c6802a6; 295 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 296 } 297 298 /* 299 * Get the cache sizes because install_extint calls __syncicache. 300 */ 301 cpu_probe_cache(); 302 303 #define MxSPR_MASK 0x7c1fffff 304 #define MFSPR_MQ 0x7c0002a6 305 #define MTSPR_MQ 0x7c0003a6 306 #define MTSPR_IBAT0L 0x7c1183a6 307 #define MTSPR_IBAT1L 0x7c1383a6 308 #define NOP 0x60000000 309 #define B 0x48000000 310 #define TLBSYNC 0x7c00046c 311 #define SYNC 0x7c0004ac 312 313 #ifdef ALTIVEC 314 #define MFSPR_VRSAVE 0x7c0042a6 315 #define MTSPR_VRSAVE 0x7c0043a6 316 317 /* 318 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 319 * not on a AltiVec capable processor. 320 */ 321 __asm volatile ( 322 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 323 "mfmsr %1; mtmsr %0; isync" 324 : "=r"(msr), "=r"(scratch) 325 : "J"(PSL_VEC)); 326 327 /* 328 * If we aren't on an AltiVec capable processor, we need to zap any of 329 * the sequences we save/restore the VRSAVE SPR into NOPs. 330 */ 331 if (scratch & PSL_VEC) { 332 cpu_altivec = 1; 333 } else { 334 int *ip = trapstart; 335 336 for (; ip < trapend; ip++) { 337 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 338 ip[0] = NOP; /* mfspr */ 339 ip[1] = NOP; /* stw */ 340 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 341 ip[-1] = NOP; /* lwz */ 342 ip[0] = NOP; /* mtspr */ 343 } 344 } 345 } 346 #endif 347 348 /* XXX It would seem like this code could be elided ifndef 601, but 349 * doing so breaks my power3 machine. 350 */ 351 /* 352 * If we aren't on a MPC601 processor, we need to zap any of the 353 * sequences we save/restore the MQ SPR into NOPs, and skip over the 354 * sequences where we zap/restore BAT registers on kernel exit/entry. 355 */ 356 if (cpuvers != MPC601) { 357 int *ip = trapstart; 358 359 for (; ip < trapend; ip++) { 360 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 361 ip[0] = NOP; /* mfspr */ 362 ip[1] = NOP; /* stw */ 363 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 364 ip[-1] = NOP; /* lwz */ 365 ip[0] = NOP; /* mtspr */ 366 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 367 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 368 ip[-1] = B | 0x14; /* li */ 369 else 370 ip[-4] = B | 0x24; /* lis */ 371 } 372 } 373 } 374 375 /* 376 * Sync the changed instructions. 377 */ 378 __syncicache((void *) trapstart, 379 (uintptr_t) trapend - (uintptr_t) trapstart); 380 __syncicache(dsitrap_fix_dbat4, 16); 381 __syncicache(dsitrap_fix_dbat7, 8); 382 #ifdef PPC_OEA601 383 384 /* 385 * If we are on a MPC601 processor, we need to zap any tlbsync 386 * instructions into sync. This differs from the above in 387 * examing all kernel text, as opposed to just the exception handling. 388 * We sync the icache on every instruction found since there are 389 * only very few of them. 390 */ 391 if (cpuvers == MPC601) { 392 extern int kernel_text[], etext[]; 393 int *ip; 394 395 for (ip = kernel_text; ip < etext; ip++) 396 if (*ip == TLBSYNC) { 397 *ip = SYNC; 398 __syncicache(ip, sizeof(*ip)); 399 } 400 } 401 #endif /* PPC_OEA601 */ 402 403 /* 404 * Configure a PSL user mask matching this processor. 405 */ 406 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 407 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 408 #ifdef PPC_OEA601 409 if (cpuvers == MPC601) { 410 cpu_psluserset &= PSL_601_MASK; 411 cpu_pslusermod &= PSL_601_MASK; 412 } 413 #endif 414 #ifdef ALTIVEC 415 if (cpu_altivec) 416 cpu_pslusermod |= PSL_VEC; 417 #endif 418 #ifdef PPC_HIGH_VEC 419 cpu_psluserset |= PSL_IP; /* XXX ok? */ 420 #endif 421 422 /* 423 * external interrupt handler install 424 */ 425 if (handler) 426 oea_install_extint(handler); 427 428 __syncicache((void *)exc_base, EXC_LAST + 0x100); 429 430 /* 431 * Now enable translation (and machine checks/recoverable interrupts). 432 */ 433 #ifdef PPC_OEA 434 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 435 : "=r"(scratch) 436 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 437 #endif 438 439 KASSERT(curcpu() == ci); 440 } 441 442 #ifdef PPC_OEA601 443 void 444 mpc601_ioseg_add(paddr_t pa, register_t len) 445 { 446 const u_int i = pa >> ADDR_SR_SHFT; 447 448 if (len != BAT_BL_256M) 449 panic("mpc601_ioseg_add: len != 256M"); 450 451 /* 452 * Translate into an I/O segment, load it, and stash away for use 453 * in pmap_bootstrap(). 454 */ 455 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 456 __asm volatile ("mtsrin %0,%1" 457 :: "r"(iosrtable[i]), 458 "r"(pa)); 459 } 460 #endif /* PPC_OEA601 */ 461 462 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 463 #define DBAT_SET(n, batl, batu) \ 464 do { \ 465 mtspr(SPR_DBAT##n##L, (batl)); \ 466 mtspr(SPR_DBAT##n##U, (batu)); \ 467 } while (/*CONSTCOND*/ 0) 468 #define DBAT_RESET(n) DBAT_SET(n, 0, 0) 469 #define DBATU_GET(n) mfspr(SPR_DBAT##n##U) 470 #define IBAT_SET(n, batl, batu) \ 471 do { \ 472 mtspr(SPR_IBAT##n##L, (batl)); \ 473 mtspr(SPR_IBAT##n##U, (batu)); \ 474 } while (/*CONSTCOND*/ 0) 475 #define IBAT_RESET(n) IBAT_SET(n, 0, 0) 476 477 void 478 oea_iobat_add(paddr_t pa, register_t len) 479 { 480 static int z = 1; 481 const u_int n = __SHIFTOUT(len, (BAT_XBL|BAT_BL) & ~BAT_BL_8M); 482 const u_int i = BAT_VA2IDX(pa) & -n; /* in case pa was in the middle */ 483 const int after_bat3 = (oeacpufeat & OEACPU_HIGHBAT) ? 4 : 8; 484 485 KASSERT(len >= BAT_BL_8M); 486 487 const register_t batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 488 const register_t batu = BATU(pa, len, BAT_Vs); 489 490 for (u_int j = 0; j < n; j++) { 491 battable[i + j].batl = batl; 492 battable[i + j].batu = batu; 493 } 494 495 /* 496 * Let's start loading the BAT registers. 497 */ 498 switch (z) { 499 case 1: 500 DBAT_SET(1, batl, batu); 501 z = 2; 502 break; 503 case 2: 504 DBAT_SET(2, batl, batu); 505 z = 3; 506 break; 507 case 3: 508 DBAT_SET(3, batl, batu); 509 z = after_bat3; /* no highbat, skip to end */ 510 break; 511 case 4: 512 DBAT_SET(4, batl, batu); 513 z = 5; 514 break; 515 case 5: 516 DBAT_SET(5, batl, batu); 517 z = 6; 518 break; 519 case 6: 520 DBAT_SET(6, batl, batu); 521 z = 7; 522 break; 523 case 7: 524 DBAT_SET(7, batl, batu); 525 z = 8; 526 break; 527 default: 528 break; 529 } 530 } 531 532 void 533 oea_iobat_remove(paddr_t pa) 534 { 535 const u_int i = BAT_VA2IDX(pa); 536 537 if (!BAT_VA_MATCH_P(battable[i].batu, pa) || 538 !BAT_VALID_P(battable[i].batu, PSL_PR)) 539 return; 540 const int n = 541 __SHIFTOUT(battable[i].batu, (BAT_XBL|BAT_BL) & ~BAT_BL_8M) + 1; 542 KASSERT((n & (n-1)) == 0); /* power of 2 */ 543 KASSERT((i & (n-1)) == 0); /* multiple of n */ 544 545 memset(&battable[i], 0, n*sizeof(battable[0])); 546 547 const int maxbat = oeacpufeat & OEACPU_HIGHBAT ? 8 : 4; 548 for (u_int k = 1 ; k < maxbat; k++) { 549 register_t batu; 550 switch (k) { 551 case 1: 552 batu = DBATU_GET(1); 553 if (BAT_VA_MATCH_P(batu, pa) && 554 BAT_VALID_P(batu, PSL_PR)) 555 DBAT_RESET(1); 556 break; 557 case 2: 558 batu = DBATU_GET(2); 559 if (BAT_VA_MATCH_P(batu, pa) && 560 BAT_VALID_P(batu, PSL_PR)) 561 DBAT_RESET(2); 562 break; 563 case 3: 564 batu = DBATU_GET(3); 565 if (BAT_VA_MATCH_P(batu, pa) && 566 BAT_VALID_P(batu, PSL_PR)) 567 DBAT_RESET(3); 568 break; 569 case 4: 570 batu = DBATU_GET(4); 571 if (BAT_VA_MATCH_P(batu, pa) && 572 BAT_VALID_P(batu, PSL_PR)) 573 DBAT_RESET(4); 574 break; 575 case 5: 576 batu = DBATU_GET(5); 577 if (BAT_VA_MATCH_P(batu, pa) && 578 BAT_VALID_P(batu, PSL_PR)) 579 DBAT_RESET(5); 580 break; 581 case 6: 582 batu = DBATU_GET(6); 583 if (BAT_VA_MATCH_P(batu, pa) && 584 BAT_VALID_P(batu, PSL_PR)) 585 DBAT_RESET(6); 586 break; 587 case 7: 588 batu = DBATU_GET(7); 589 if (BAT_VA_MATCH_P(batu, pa) && 590 BAT_VALID_P(batu, PSL_PR)) 591 DBAT_RESET(7); 592 break; 593 default: 594 break; 595 } 596 } 597 } 598 599 void 600 oea_batinit(paddr_t pa, ...) 601 { 602 struct mem_region *allmem, *availmem, *mp; 603 unsigned int cpuvers; 604 register_t msr = mfmsr(); 605 va_list ap; 606 607 cpuvers = mfpvr() >> 16; 608 609 /* 610 * Initialize BAT registers to unmapped to not generate 611 * overlapping mappings below. 612 * 613 * The 601's implementation differs in the Valid bit being situated 614 * in the lower BAT register, and in being a unified BAT only whose 615 * four entries are accessed through the IBAT[0-3] SPRs. 616 * 617 * Also, while the 601 does distinguish between supervisor/user 618 * protection keys, it does _not_ distinguish between validity in 619 * supervisor/user mode. 620 */ 621 if ((msr & (PSL_IR|PSL_DR)) == 0) { 622 #ifdef PPC_OEA601 623 if (cpuvers == MPC601) { 624 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 625 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 626 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 627 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 628 } else 629 #endif /* PPC_OEA601 */ 630 { 631 DBAT_RESET(0); IBAT_RESET(0); 632 DBAT_RESET(1); IBAT_RESET(1); 633 DBAT_RESET(2); IBAT_RESET(2); 634 DBAT_RESET(3); IBAT_RESET(3); 635 if (oeacpufeat & OEACPU_HIGHBAT) { 636 DBAT_RESET(4); IBAT_RESET(4); 637 DBAT_RESET(5); IBAT_RESET(5); 638 DBAT_RESET(6); IBAT_RESET(6); 639 DBAT_RESET(7); IBAT_RESET(7); 640 641 /* 642 * Change the first instruction to branch to 643 * dsitrap_fix_dbat6 644 */ 645 dsitrap_fix_dbat4[0] &= ~0xfffc; 646 dsitrap_fix_dbat4[0] 647 += (uintptr_t)dsitrap_fix_dbat6 648 - (uintptr_t)&dsitrap_fix_dbat4[0]; 649 650 /* 651 * Change the second instruction to branch to 652 * dsitrap_fix_dbat5 if bit 30 (aka bit 1) is 653 * true. 654 */ 655 dsitrap_fix_dbat4[1] = 0x419e0000 656 + (uintptr_t)dsitrap_fix_dbat5 657 - (uintptr_t)&dsitrap_fix_dbat4[1]; 658 659 /* 660 * Change it load dbat4 instead of dbat2 661 */ 662 dsitrap_fix_dbat4[2] = 0x7fd88ba6; 663 dsitrap_fix_dbat4[3] = 0x7ff98ba6; 664 665 /* 666 * Change it load dbat7 instead of dbat3 667 */ 668 dsitrap_fix_dbat7[0] = 0x7fde8ba6; 669 dsitrap_fix_dbat7[1] = 0x7fff8ba6; 670 } 671 } 672 } 673 674 /* 675 * Set up BAT to map physical memory 676 */ 677 #ifdef PPC_OEA601 678 if (cpuvers == MPC601) { 679 int i; 680 681 /* 682 * Set up battable to map the lowest 256 MB area. 683 * Map the lowest 32 MB area via BAT[0-3]; 684 * BAT[01] are fixed, BAT[23] are floating. 685 */ 686 for (i = 0; i < 32; i++) { 687 battable[i].batl = BATL601(i << 23, 688 BAT601_BSM_8M, BAT601_V); 689 battable[i].batu = BATU601(i << 23, 690 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 691 } 692 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 693 :: "r"(battable[0x00000000 >> 23].batl), 694 "r"(battable[0x00000000 >> 23].batu)); 695 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 696 :: "r"(battable[0x00800000 >> 23].batl), 697 "r"(battable[0x00800000 >> 23].batu)); 698 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 699 :: "r"(battable[0x01000000 >> 23].batl), 700 "r"(battable[0x01000000 >> 23].batu)); 701 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 702 :: "r"(battable[0x01800000 >> 23].batl), 703 "r"(battable[0x01800000 >> 23].batu)); 704 } else 705 #endif /* PPC_OEA601 */ 706 { 707 /* 708 * Set up BAT0 to only map the lowest 256 MB area 709 */ 710 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 711 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 712 713 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 714 "mtdbatl 0,%0; mtdbatu 0,%1;" 715 :: "r"(battable[0].batl), "r"(battable[0].batu)); 716 } 717 718 /* 719 * Now setup other fixed bat registers 720 * 721 * Note that we still run in real mode, and the BAT 722 * registers were cleared above. 723 */ 724 725 va_start(ap, pa); 726 727 /* 728 * Add any I/O BATs specificed; 729 * use I/O segments on the BAT-starved 601. 730 */ 731 #ifdef PPC_OEA601 732 if (cpuvers == MPC601) { 733 while (pa != 0) { 734 register_t len = va_arg(ap, register_t); 735 mpc601_ioseg_add(pa, len); 736 pa = va_arg(ap, paddr_t); 737 } 738 } else 739 #endif 740 { 741 while (pa != 0) { 742 register_t len = va_arg(ap, register_t); 743 oea_iobat_add(pa, len); 744 pa = va_arg(ap, paddr_t); 745 } 746 } 747 748 va_end(ap); 749 750 /* 751 * Set up battable to map all RAM regions. 752 * This is here because mem_regions() call needs bat0 set up. 753 */ 754 mem_regions(&allmem, &availmem); 755 #ifdef PPC_OEA601 756 if (cpuvers == MPC601) { 757 for (mp = allmem; mp->size; mp++) { 758 paddr_t paddr = mp->start & 0xff800000; 759 paddr_t end = mp->start + mp->size; 760 761 do { 762 u_int ix = paddr >> 23; 763 764 battable[ix].batl = 765 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 766 battable[ix].batu = 767 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 768 paddr += (1 << 23); 769 } while (paddr < end); 770 } 771 } else 772 #endif 773 { 774 for (mp = allmem; mp->size; mp++) { 775 paddr_t paddr = mp->start & -BAT_IDX2VA(1); 776 paddr_t end = 777 roundup2(mp->start + mp->size, BAT_IDX2VA(1)); 778 779 while (paddr < end) { 780 psize_t size = 256*1024*1024; 781 register_t bl = BAT_BL_256M; 782 u_int n = BAT_VA2IDX(size); 783 u_int i = BAT_VA2IDX(paddr); 784 785 while ((paddr & (size - 1)) 786 || paddr + size > end) { 787 size >>= 1; 788 bl = (bl >> 1) & BAT_BL; 789 n >>= 1; 790 } 791 KASSERT(size >= BAT_IDX2VA(1)); 792 KASSERT(n >= 1); 793 KASSERT(bl >= BAT_BL_8M); 794 795 for (; n-- > 0; i++) { 796 battable[i].batl = 797 BATL(paddr, BAT_M, BAT_PP_RW); 798 battable[i].batu = 799 BATU(paddr, bl, BAT_Vs); 800 } 801 paddr += size; 802 } 803 } 804 } 805 } 806 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 807 808 void 809 oea_install_extint(void (*handler)(void)) 810 { 811 extern int extint[], extsize[]; 812 extern int extint_call[]; 813 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 814 int omsr, msr; 815 816 #ifdef DIAGNOSTIC 817 if (offset > 0x1ffffff) 818 panic("install_extint: %p too far away (%#lx)", handler, 819 (unsigned long) offset); 820 #endif 821 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 822 : "=r" (omsr), "=r" (msr) 823 : "K" ((u_short)~PSL_EE)); 824 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 825 __syncicache((void *)extint_call, sizeof extint_call[0]); 826 #ifdef PPC_HIGH_VEC 827 memcpy((void *)(EXC_HIGHVEC + EXC_EXI), extint, (size_t)extsize); 828 __syncicache((void *)(EXC_HIGHVEC + EXC_EXI), (int)extsize); 829 #else 830 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 831 __syncicache((void *)EXC_EXI, (int)extsize); 832 #endif 833 __asm volatile ("mtmsr %0" :: "r"(omsr)); 834 } 835 836 /* 837 * Machine dependent startup code. 838 */ 839 void 840 oea_startup(const char *model) 841 { 842 uintptr_t sz; 843 void *v; 844 vaddr_t minaddr, maxaddr; 845 char pbuf[9]; 846 u_int i; 847 848 KASSERT(curcpu() != NULL); 849 KASSERT(lwp0.l_cpu != NULL); 850 KASSERT(curcpu()->ci_idepth == -1); 851 852 /* 853 * If the msgbuf is not in segment 0, allocate KVA for it and access 854 * it via mapped pages. [This prevents unneeded BAT switches.] 855 */ 856 sz = round_page(MSGBUFSIZE); 857 v = (void *) msgbuf_paddr; 858 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 859 minaddr = 0; 860 if (uvm_map(kernel_map, &minaddr, sz, 861 NULL, UVM_UNKNOWN_OFFSET, 0, 862 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 863 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 864 panic("startup: cannot allocate VM for msgbuf"); 865 v = (void *)minaddr; 866 for (i = 0; i < sz; i += PAGE_SIZE) { 867 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 868 VM_PROT_READ|VM_PROT_WRITE); 869 } 870 pmap_update(pmap_kernel()); 871 } 872 initmsgbuf(v, sz); 873 874 printf("%s%s", copyright, version); 875 if (model != NULL) 876 printf("Model: %s\n", model); 877 cpu_identify(NULL, 0); 878 879 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 880 printf("total memory = %s\n", pbuf); 881 882 /* 883 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 884 * the bufpages are allocated in case they overlap since it's not 885 * fatal if we can't allocate these. 886 */ 887 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 888 int error; 889 minaddr = 0xDEAC0000; 890 error = uvm_map(kernel_map, &minaddr, 0x30000, 891 NULL, UVM_UNKNOWN_OFFSET, 0, 892 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 893 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 894 if (error != 0 || minaddr != 0xDEAC0000) 895 printf("oea_startup: failed to allocate DEAD " 896 "ZONE: error=%d\n", error); 897 } 898 899 minaddr = 0; 900 901 /* 902 * Allocate a submap for physio 903 */ 904 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 905 VM_PHYS_SIZE, 0, false, NULL); 906 907 #ifndef PMAP_MAP_POOLPAGE 908 /* 909 * No need to allocate an mbuf cluster submap. Mbuf clusters 910 * are allocated via the pool allocator, and we use direct-mapped 911 * pool pages. 912 */ 913 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 914 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 915 #endif 916 917 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 918 printf("avail memory = %s\n", pbuf); 919 } 920 921 /* 922 * Crash dump handling. 923 */ 924 925 void 926 oea_dumpsys(void) 927 { 928 printf("dumpsys: TBD\n"); 929 } 930 931 /* 932 * Convert kernel VA to physical address 933 */ 934 paddr_t 935 kvtop(void *addr) 936 { 937 vaddr_t va; 938 paddr_t pa; 939 uintptr_t off; 940 extern char end[]; 941 942 if (addr < (void *)end) 943 return (paddr_t)addr; 944 945 va = trunc_page((vaddr_t)addr); 946 off = (uintptr_t)addr - va; 947 948 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 949 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 950 return (paddr_t)addr; 951 } 952 953 return(pa + off); 954 } 955 956 /* 957 * Allocate vm space and mapin the I/O address 958 */ 959 void * 960 mapiodev(paddr_t pa, psize_t len) 961 { 962 paddr_t faddr; 963 vaddr_t taddr, va; 964 int off; 965 966 faddr = trunc_page(pa); 967 off = pa - faddr; 968 len = round_page(off + len); 969 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 970 971 if (va == 0) 972 return NULL; 973 974 for (; len > 0; len -= PAGE_SIZE) { 975 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 976 faddr += PAGE_SIZE; 977 taddr += PAGE_SIZE; 978 } 979 pmap_update(pmap_kernel()); 980 return (void *)(va + off); 981 } 982 983 void 984 unmapiodev(vaddr_t va, vsize_t len) 985 { 986 paddr_t faddr; 987 988 if (! va) 989 return; 990 991 faddr = trunc_page(va); 992 len = round_page(va - faddr + len); 993 994 pmap_kremove(faddr, len); 995 pmap_update(pmap_kernel()); 996 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 997 } 998 999 void 1000 trap0(void *lr) 1001 { 1002 panic("call to null-ptr from %p", lr); 1003 } 1004
Indexes created Mon Oct 20 11:09:49 GMT 2025