oea_machdep.c revision 1.47
1 /* $NetBSD: oea_machdep.c,v 1.47 2009/06/07 13:37:29 phx Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.47 2009/06/07 13:37:29 phx Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/exec.h> 49 #include <sys/malloc.h> 50 #include <sys/mbuf.h> 51 #include <sys/mount.h> 52 #include <sys/msgbuf.h> 53 #include <sys/proc.h> 54 #include <sys/reboot.h> 55 #include <sys/syscallargs.h> 56 #include <sys/syslog.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/user.h> 60 #include <sys/boot_flag.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <net/netisr.h> 65 66 #ifdef DDB 67 #include <machine/db_machdep.h> 68 #include <ddb/db_extern.h> 69 #endif 70 71 #ifdef KGDB 72 #include <sys/kgdb.h> 73 #endif 74 75 #ifdef IPKDB 76 #include <ipkdb/ipkdb.h> 77 #endif 78 79 #include <powerpc/oea/bat.h> 80 #include <powerpc/oea/sr_601.h> 81 #include <powerpc/oea/cpufeat.h> 82 #include <powerpc/trap.h> 83 #include <powerpc/stdarg.h> 84 #include <powerpc/spr.h> 85 #include <powerpc/pte.h> 86 #include <powerpc/altivec.h> 87 #include <machine/powerpc.h> 88 89 char machine[] = MACHINE; /* from <machine/param.h> */ 90 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 91 92 struct vm_map *mb_map = NULL; 93 struct vm_map *phys_map = NULL; 94 95 /* 96 * Global variables used here and there 97 */ 98 extern struct user *proc0paddr; 99 100 static void trap0(void *); 101 102 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 103 struct bat battable[512]; 104 105 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 106 #ifndef MSGBUFADDR 107 paddr_t msgbuf_paddr; 108 #endif 109 110 void 111 oea_init(void (*handler)(void)) 112 { 113 extern int trapcode[], trapsize[]; 114 extern int sctrap[], scsize[]; 115 extern int alitrap[], alisize[]; 116 extern int dsitrap[], dsisize[]; 117 extern int trapstart[], trapend[]; 118 #ifdef PPC_OEA601 119 extern int dsi601trap[], dsi601size[]; 120 #endif 121 extern int decrint[], decrsize[]; 122 extern int tlbimiss[], tlbimsize[]; 123 extern int tlbdlmiss[], tlbdlmsize[]; 124 extern int tlbdsmiss[], tlbdsmsize[]; 125 #if defined(DDB) || defined(KGDB) 126 extern int ddblow[], ddbsize[]; 127 #endif 128 #ifdef IPKDB 129 extern int ipkdblow[], ipkdbsize[]; 130 #endif 131 #ifdef ALTIVEC 132 register_t msr; 133 #endif 134 uintptr_t exc, exc_base; 135 #if defined(ALTIVEC) || defined(PPC_OEA) 136 register_t scratch; 137 #endif 138 unsigned int cpuvers; 139 size_t size; 140 struct cpu_info * const ci = &cpu_info[0]; 141 142 #ifdef PPC_HIGH_VEC 143 exc_base = EXC_HIGHVEC; 144 #else 145 exc_base = 0; 146 #endif 147 mtspr(SPR_SPRG0, ci); 148 cpuvers = mfpvr() >> 16; 149 150 /* 151 * Initialize proc0 and current pcb and pmap pointers. 152 */ 153 KASSERT(ci != NULL); 154 KASSERT(curcpu() == ci); 155 lwp0.l_cpu = ci; 156 lwp0.l_addr = proc0paddr; 157 memset(lwp0.l_addr, 0, sizeof *lwp0.l_addr); 158 KASSERT(lwp0.l_cpu != NULL); 159 160 curpcb = &proc0paddr->u_pcb; 161 memset(curpcb, 0, sizeof(*curpcb)); 162 #ifdef ALTIVEC 163 /* 164 * Initialize the vectors with NaNs 165 */ 166 for (scratch = 0; scratch < 32; scratch++) { 167 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 168 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 169 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 170 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 171 } 172 curpcb->pcb_vr.vscr = 0; 173 curpcb->pcb_vr.vrsave = 0; 174 #endif 175 curpm = curpcb->pcb_pm = pmap_kernel(); 176 177 /* 178 * Cause a PGM trap if we branch to 0. 179 * 180 * XXX GCC4.1 complains about memset on address zero, so 181 * don't use the builtin. 182 */ 183 #undef memset 184 memset(0, 0, 0x100); 185 186 /* 187 * Set up trap vectors. Don't assume vectors are on 0x100. 188 */ 189 for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) { 190 switch (exc - exc_base) { 191 default: 192 size = (size_t)trapsize; 193 memcpy((void *)exc, trapcode, size); 194 break; 195 #if 0 196 case EXC_EXI: 197 /* 198 * This one is (potentially) installed during autoconf 199 */ 200 break; 201 #endif 202 case EXC_SC: 203 size = (size_t)scsize; 204 memcpy((void *)exc, sctrap, size); 205 break; 206 case EXC_ALI: 207 size = (size_t)alisize; 208 memcpy((void *)exc, alitrap, size); 209 break; 210 case EXC_DSI: 211 #ifdef PPC_OEA601 212 if (cpuvers == MPC601) { 213 size = (size_t)dsi601size; 214 memcpy((void *)exc, dsi601trap, size); 215 break; 216 } else 217 #endif /* PPC_OEA601 */ 218 if (oeacpufeat & OEACPU_NOBAT) { 219 size = (size_t)alisize; 220 memcpy((void *)exc, alitrap, size); 221 } else { 222 size = (size_t)dsisize; 223 memcpy((void *)exc, dsitrap, size); 224 } 225 break; 226 case EXC_DECR: 227 size = (size_t)decrsize; 228 memcpy((void *)exc, decrint, size); 229 break; 230 case EXC_IMISS: 231 size = (size_t)tlbimsize; 232 memcpy((void *)exc, tlbimiss, size); 233 break; 234 case EXC_DLMISS: 235 size = (size_t)tlbdlmsize; 236 memcpy((void *)exc, tlbdlmiss, size); 237 break; 238 case EXC_DSMISS: 239 size = (size_t)tlbdsmsize; 240 memcpy((void *)exc, tlbdsmiss, size); 241 break; 242 case EXC_PERF: 243 size = (size_t)trapsize; 244 memcpy((void *)exc, trapcode, size); 245 memcpy((void *)(exc_base + EXC_VEC), trapcode, size); 246 break; 247 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 248 case EXC_RUNMODETRC: 249 #ifdef PPC_OEA601 250 if (cpuvers != MPC601) { 251 #endif 252 size = (size_t)trapsize; 253 memcpy((void *)exc, trapcode, size); 254 break; 255 #ifdef PPC_OEA601 256 } 257 /* FALLTHROUGH */ 258 #endif 259 case EXC_PGM: 260 case EXC_TRC: 261 case EXC_BPT: 262 #if defined(DDB) || defined(KGDB) 263 size = (size_t)ddbsize; 264 memcpy((void *)exc, ddblow, size); 265 #if defined(IPKDB) 266 #error "cannot enable IPKDB with DDB or KGDB" 267 #endif 268 #else 269 size = (size_t)ipkdbsize; 270 memcpy((void *)exc, ipkdblow, size); 271 #endif 272 break; 273 #endif /* DDB || IPKDB || KGDB */ 274 } 275 #if 0 276 exc += roundup(size, 32); 277 #endif 278 } 279 280 /* 281 * Install a branch absolute to trap0 to force a panic. 282 */ 283 if ((uintptr_t)trap0 < 0x2000000) { 284 *(uint32_t *) 0 = 0x7c6802a6; 285 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 286 } 287 288 /* 289 * Get the cache sizes because install_extint calls __syncicache. 290 */ 291 cpu_probe_cache(); 292 293 #define MxSPR_MASK 0x7c1fffff 294 #define MFSPR_MQ 0x7c0002a6 295 #define MTSPR_MQ 0x7c0003a6 296 #define MTSPR_IBAT0L 0x7c1183a6 297 #define MTSPR_IBAT1L 0x7c1383a6 298 #define NOP 0x60000000 299 #define B 0x48000000 300 #define TLBSYNC 0x7c00046c 301 #define SYNC 0x7c0004ac 302 303 #ifdef ALTIVEC 304 #define MFSPR_VRSAVE 0x7c0042a6 305 #define MTSPR_VRSAVE 0x7c0043a6 306 307 /* 308 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 309 * not on a AltiVec capable processor. 310 */ 311 __asm volatile ( 312 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 313 "mfmsr %1; mtmsr %0; isync" 314 : "=r"(msr), "=r"(scratch) 315 : "J"(PSL_VEC)); 316 317 /* 318 * If we aren't on an AltiVec capable processor, we need to zap any of 319 * the sequences we save/restore the VRSAVE SPR into NOPs. 320 */ 321 if (scratch & PSL_VEC) { 322 cpu_altivec = 1; 323 } else { 324 int *ip = trapstart; 325 326 for (; ip < trapend; ip++) { 327 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 328 ip[0] = NOP; /* mfspr */ 329 ip[1] = NOP; /* stw */ 330 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 331 ip[-1] = NOP; /* lwz */ 332 ip[0] = NOP; /* mtspr */ 333 } 334 } 335 } 336 #endif 337 338 /* XXX It would seem like this code could be elided ifndef 601, but 339 * doing so breaks my power3 machine. 340 */ 341 /* 342 * If we aren't on a MPC601 processor, we need to zap any of the 343 * sequences we save/restore the MQ SPR into NOPs, and skip over the 344 * sequences where we zap/restore BAT registers on kernel exit/entry. 345 */ 346 if (cpuvers != MPC601) { 347 int *ip = trapstart; 348 349 for (; ip < trapend; ip++) { 350 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 351 ip[0] = NOP; /* mfspr */ 352 ip[1] = NOP; /* stw */ 353 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 354 ip[-1] = NOP; /* lwz */ 355 ip[0] = NOP; /* mtspr */ 356 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 357 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 358 ip[-1] = B | 0x14; /* li */ 359 else 360 ip[-4] = B | 0x24; /* lis */ 361 } 362 } 363 } 364 365 /* 366 * Sync the changed instructions. 367 */ 368 __syncicache((void *) trapstart, 369 (uintptr_t) trapend - (uintptr_t) trapstart); 370 #ifdef PPC_OEA601 371 372 /* 373 * If we are on a MPC601 processor, we need to zap any tlbsync 374 * instructions into sync. This differs from the above in 375 * examing all kernel text, as opposed to just the exception handling. 376 * We sync the icache on every instruction found since there are 377 * only very few of them. 378 */ 379 if (cpuvers == MPC601) { 380 extern int kernel_text[], etext[]; 381 int *ip; 382 383 for (ip = kernel_text; ip < etext; ip++) 384 if (*ip == TLBSYNC) { 385 *ip = SYNC; 386 __syncicache(ip, sizeof(*ip)); 387 } 388 } 389 #endif /* PPC_OEA601 */ 390 391 /* 392 * Configure a PSL user mask matching this processor. 393 */ 394 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 395 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 396 #ifdef PPC_OEA601 397 if (cpuvers == MPC601) { 398 cpu_psluserset &= PSL_601_MASK; 399 cpu_pslusermod &= PSL_601_MASK; 400 } 401 #endif 402 #ifdef ALTIVEC 403 if (cpu_altivec) 404 cpu_pslusermod |= PSL_VEC; 405 #endif 406 #ifdef PPC_HIGH_VEC 407 cpu_psluserset |= PSL_IP; /* XXX ok? */ 408 #endif 409 410 /* 411 * external interrupt handler install 412 */ 413 if (handler) 414 oea_install_extint(handler); 415 416 __syncicache((void *)exc_base, EXC_LAST + 0x100); 417 418 /* 419 * Now enable translation (and machine checks/recoverable interrupts). 420 */ 421 #ifdef PPC_OEA 422 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 423 : "=r"(scratch) 424 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 425 #endif 426 427 KASSERT(curcpu() == ci); 428 } 429 430 #ifdef PPC_OEA601 431 void 432 mpc601_ioseg_add(paddr_t pa, register_t len) 433 { 434 const u_int i = pa >> ADDR_SR_SHFT; 435 436 if (len != BAT_BL_256M) 437 panic("mpc601_ioseg_add: len != 256M"); 438 439 /* 440 * Translate into an I/O segment, load it, and stash away for use 441 * in pmap_bootstrap(). 442 */ 443 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 444 __asm volatile ("mtsrin %0,%1" 445 :: "r"(iosrtable[i]), 446 "r"(pa)); 447 } 448 #endif /* PPC_OEA601 */ 449 450 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 451 void 452 oea_iobat_add(paddr_t pa, register_t len) 453 { 454 static int n = 1; 455 const u_int i = pa >> 28; 456 battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 457 battable[i].batu = BATU(pa, len, BAT_Vs); 458 459 /* 460 * Let's start loading the BAT registers. 461 */ 462 switch (n) { 463 case 1: 464 __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;" 465 :: "r"(battable[i].batl), 466 "r"(battable[i].batu)); 467 n = 2; 468 break; 469 case 2: 470 __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;" 471 :: "r"(battable[i].batl), 472 "r"(battable[i].batu)); 473 n = 3; 474 break; 475 case 3: 476 __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;" 477 :: "r"(battable[i].batl), 478 "r"(battable[i].batu)); 479 n = 4; 480 break; 481 default: 482 break; 483 } 484 } 485 486 void 487 oea_iobat_remove(paddr_t pa) 488 { 489 register_t batu; 490 int i, n; 491 492 n = pa >> ADDR_SR_SHFT; 493 if (!BAT_VA_MATCH_P(battable[n].batu, pa) || 494 !BAT_VALID_P(battable[n].batu, PSL_PR)) 495 return; 496 battable[n].batl = 0; 497 battable[n].batu = 0; 498 #define BAT_RESET(n) \ 499 __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0)) 500 #define BATU_GET(n, r) __asm volatile("mfdbatu %0,%1" : "=r"(r) : "n"(n)) 501 502 for (i=1 ; i<4 ; i++) { 503 switch (i) { 504 case 1: 505 BATU_GET(1, batu); 506 if (BAT_VA_MATCH_P(batu, pa) && 507 BAT_VALID_P(batu, PSL_PR)) 508 BAT_RESET(1); 509 break; 510 case 2: 511 BATU_GET(2, batu); 512 if (BAT_VA_MATCH_P(batu, pa) && 513 BAT_VALID_P(batu, PSL_PR)) 514 BAT_RESET(2); 515 break; 516 case 3: 517 BATU_GET(3, batu); 518 if (BAT_VA_MATCH_P(batu, pa) && 519 BAT_VALID_P(batu, PSL_PR)) 520 BAT_RESET(3); 521 break; 522 default: 523 break; 524 } 525 } 526 } 527 528 void 529 oea_batinit(paddr_t pa, ...) 530 { 531 struct mem_region *allmem, *availmem, *mp; 532 unsigned int cpuvers; 533 register_t msr = mfmsr(); 534 va_list ap; 535 536 cpuvers = mfpvr() >> 16; 537 538 /* 539 * Initialize BAT registers to unmapped to not generate 540 * overlapping mappings below. 541 * 542 * The 601's implementation differs in the Valid bit being situated 543 * in the lower BAT register, and in being a unified BAT only whose 544 * four entries are accessed through the IBAT[0-3] SPRs. 545 * 546 * Also, while the 601 does distinguish between supervisor/user 547 * protection keys, it does _not_ distinguish between validity in 548 * supervisor/user mode. 549 */ 550 if ((msr & (PSL_IR|PSL_DR)) == 0) { 551 #ifdef PPC_OEA601 552 if (cpuvers == MPC601) { 553 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 554 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 555 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 556 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 557 } else 558 #endif /* PPC_OEA601 */ 559 { 560 __asm volatile ("mtibatu 0,%0" :: "r"(0)); 561 __asm volatile ("mtibatu 1,%0" :: "r"(0)); 562 __asm volatile ("mtibatu 2,%0" :: "r"(0)); 563 __asm volatile ("mtibatu 3,%0" :: "r"(0)); 564 __asm volatile ("mtdbatu 0,%0" :: "r"(0)); 565 __asm volatile ("mtdbatu 1,%0" :: "r"(0)); 566 __asm volatile ("mtdbatu 2,%0" :: "r"(0)); 567 __asm volatile ("mtdbatu 3,%0" :: "r"(0)); 568 } 569 } 570 571 /* 572 * Set up BAT to map physical memory 573 */ 574 #ifdef PPC_OEA601 575 if (cpuvers == MPC601) { 576 int i; 577 578 /* 579 * Set up battable to map the lowest 256 MB area. 580 * Map the lowest 32 MB area via BAT[0-3]; 581 * BAT[01] are fixed, BAT[23] are floating. 582 */ 583 for (i = 0; i < 32; i++) { 584 battable[i].batl = BATL601(i << 23, 585 BAT601_BSM_8M, BAT601_V); 586 battable[i].batu = BATU601(i << 23, 587 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 588 } 589 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 590 :: "r"(battable[0x00000000 >> 23].batl), 591 "r"(battable[0x00000000 >> 23].batu)); 592 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 593 :: "r"(battable[0x00800000 >> 23].batl), 594 "r"(battable[0x00800000 >> 23].batu)); 595 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 596 :: "r"(battable[0x01000000 >> 23].batl), 597 "r"(battable[0x01000000 >> 23].batu)); 598 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 599 :: "r"(battable[0x01800000 >> 23].batl), 600 "r"(battable[0x01800000 >> 23].batu)); 601 } else 602 #endif /* PPC_OEA601 */ 603 { 604 /* 605 * Set up BAT0 to only map the lowest 256 MB area 606 */ 607 battable[0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 608 battable[0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 609 610 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 611 "mtdbatl 0,%0; mtdbatu 0,%1;" 612 :: "r"(battable[0].batl), "r"(battable[0].batu)); 613 } 614 615 /* 616 * Now setup other fixed bat registers 617 * 618 * Note that we still run in real mode, and the BAT 619 * registers were cleared above. 620 */ 621 622 va_start(ap, pa); 623 624 /* 625 * Add any I/O BATs specificed; 626 * use I/O segments on the BAT-starved 601. 627 */ 628 #ifdef PPC_OEA601 629 if (cpuvers == MPC601) { 630 while (pa != 0) { 631 register_t len = va_arg(ap, register_t); 632 mpc601_ioseg_add(pa, len); 633 pa = va_arg(ap, paddr_t); 634 } 635 } else 636 #endif 637 { 638 while (pa != 0) { 639 register_t len = va_arg(ap, register_t); 640 oea_iobat_add(pa, len); 641 pa = va_arg(ap, paddr_t); 642 } 643 } 644 645 va_end(ap); 646 647 /* 648 * Set up battable to map all RAM regions. 649 * This is here because mem_regions() call needs bat0 set up. 650 */ 651 mem_regions(&allmem, &availmem); 652 #ifdef PPC_OEA601 653 if (cpuvers == MPC601) { 654 for (mp = allmem; mp->size; mp++) { 655 paddr_t paddr = mp->start & 0xff800000; 656 paddr_t end = mp->start + mp->size; 657 658 do { 659 u_int ix = paddr >> 23; 660 661 battable[ix].batl = 662 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 663 battable[ix].batu = 664 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 665 paddr += (1 << 23); 666 } while (paddr < end); 667 } 668 } else 669 #endif 670 { 671 for (mp = allmem; mp->size; mp++) { 672 paddr_t paddr = mp->start & 0xf0000000; 673 paddr_t end = mp->start + mp->size; 674 675 do { 676 u_int ix = paddr >> 28; 677 678 battable[ix].batl = 679 BATL(paddr, BAT_M, BAT_PP_RW); 680 battable[ix].batu = 681 BATU(paddr, BAT_BL_256M, BAT_Vs); 682 paddr += SEGMENT_LENGTH; 683 } while (paddr < end); 684 } 685 } 686 } 687 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 688 689 void 690 oea_install_extint(void (*handler)(void)) 691 { 692 extern int extint[], extsize[]; 693 extern int extint_call[]; 694 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 695 int omsr, msr; 696 697 #ifdef DIAGNOSTIC 698 if (offset > 0x1ffffff) 699 panic("install_extint: %p too far away (%#lx)", handler, 700 (unsigned long) offset); 701 #endif 702 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 703 : "=r" (omsr), "=r" (msr) 704 : "K" ((u_short)~PSL_EE)); 705 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 706 __syncicache((void *)extint_call, sizeof extint_call[0]); 707 #ifdef PPC_HIGH_VEC 708 memcpy((void *)(EXC_HIGHVEC + EXC_EXI), extint, (size_t)extsize); 709 __syncicache((void *)(EXC_HIGHVEC + EXC_EXI), (int)extsize); 710 #else 711 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 712 __syncicache((void *)EXC_EXI, (int)extsize); 713 #endif 714 __asm volatile ("mtmsr %0" :: "r"(omsr)); 715 } 716 717 /* 718 * Machine dependent startup code. 719 */ 720 void 721 oea_startup(const char *model) 722 { 723 uintptr_t sz; 724 void *v; 725 vaddr_t minaddr, maxaddr; 726 char pbuf[9]; 727 728 KASSERT(curcpu() != NULL); 729 KASSERT(lwp0.l_cpu != NULL); 730 KASSERT(curcpu()->ci_intstk != 0); 731 KASSERT(curcpu()->ci_intrdepth == -1); 732 733 sz = round_page(MSGBUFSIZE); 734 #ifdef MSGBUFADDR 735 v = (void *) MSGBUFADDR; 736 #else 737 /* 738 * If the msgbuf is not in segment 0, allocate KVA for it and access 739 * it via mapped pages. [This prevents unneeded BAT switches.] 740 */ 741 v = (void *) msgbuf_paddr; 742 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 743 u_int i; 744 745 minaddr = 0; 746 if (uvm_map(kernel_map, &minaddr, sz, 747 NULL, UVM_UNKNOWN_OFFSET, 0, 748 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 749 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 750 panic("startup: cannot allocate VM for msgbuf"); 751 v = (void *)minaddr; 752 for (i = 0; i < sz; i += PAGE_SIZE) { 753 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 754 VM_PROT_READ|VM_PROT_WRITE); 755 } 756 pmap_update(pmap_kernel()); 757 } 758 #endif 759 initmsgbuf(v, sz); 760 761 printf("%s%s", copyright, version); 762 if (model != NULL) 763 printf("Model: %s\n", model); 764 cpu_identify(NULL, 0); 765 766 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 767 printf("total memory = %s\n", pbuf); 768 769 /* 770 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 771 * the bufpages are allocated in case they overlap since it's not 772 * fatal if we can't allocate these. 773 */ 774 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 775 int error; 776 minaddr = 0xDEAC0000; 777 error = uvm_map(kernel_map, &minaddr, 0x30000, 778 NULL, UVM_UNKNOWN_OFFSET, 0, 779 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 780 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 781 if (error != 0 || minaddr != 0xDEAC0000) 782 printf("oea_startup: failed to allocate DEAD " 783 "ZONE: error=%d\n", error); 784 } 785 786 minaddr = 0; 787 788 /* 789 * Allocate a submap for physio 790 */ 791 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 792 VM_PHYS_SIZE, 0, false, NULL); 793 794 #ifndef PMAP_MAP_POOLPAGE 795 /* 796 * No need to allocate an mbuf cluster submap. Mbuf clusters 797 * are allocated via the pool allocator, and we use direct-mapped 798 * pool pages. 799 */ 800 mb_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 801 mclbytes*nmbclusters, VM_MAP_INTRSAFE, false, NULL); 802 #endif 803 804 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 805 printf("avail memory = %s\n", pbuf); 806 } 807 808 /* 809 * Crash dump handling. 810 */ 811 812 void 813 oea_dumpsys(void) 814 { 815 printf("dumpsys: TBD\n"); 816 } 817 818 /* 819 * Convert kernel VA to physical address 820 */ 821 paddr_t 822 kvtop(void *addr) 823 { 824 vaddr_t va; 825 paddr_t pa; 826 uintptr_t off; 827 extern char end[]; 828 829 if (addr < (void *)end) 830 return (paddr_t)addr; 831 832 va = trunc_page((vaddr_t)addr); 833 off = (uintptr_t)addr - va; 834 835 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 836 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 837 return (paddr_t)addr; 838 } 839 840 return(pa + off); 841 } 842 843 /* 844 * Allocate vm space and mapin the I/O address 845 */ 846 void * 847 mapiodev(paddr_t pa, psize_t len) 848 { 849 paddr_t faddr; 850 vaddr_t taddr, va; 851 int off; 852 853 faddr = trunc_page(pa); 854 off = pa - faddr; 855 len = round_page(off + len); 856 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 857 858 if (va == 0) 859 return NULL; 860 861 for (; len > 0; len -= PAGE_SIZE) { 862 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE); 863 faddr += PAGE_SIZE; 864 taddr += PAGE_SIZE; 865 } 866 pmap_update(pmap_kernel()); 867 return (void *)(va + off); 868 } 869 870 void 871 unmapiodev(vaddr_t va, vsize_t len) 872 { 873 paddr_t faddr; 874 875 if (! va) 876 return; 877 878 faddr = trunc_page(va); 879 len = round_page(va - faddr + len); 880 881 pmap_kremove(faddr, len); 882 pmap_update(pmap_kernel()); 883 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 884 } 885 886 void 887 trap0(void *lr) 888 { 889 panic("call to null-ptr from %p", lr); 890 } 891
Indexes created Thu Oct 02 01:09:59 GMT 2025