oea_machdep.c revision 1.63
1 /* $NetBSD: oea_machdep.c,v 1.63 2012/02/15 01:56:57 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 2002 Matt Thomas 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.63 2012/02/15 01:56:57 macallan Exp $"); 37 38 #include "opt_ppcarch.h" 39 #include "opt_compat_netbsd.h" 40 #include "opt_ddb.h" 41 #include "opt_kgdb.h" 42 #include "opt_ipkdb.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_altivec.h" 45 46 #include <sys/param.h> 47 #include <sys/buf.h> 48 #include <sys/boot_flag.h> 49 #include <sys/exec.h> 50 #include <sys/kernel.h> 51 #include <sys/mbuf.h> 52 #include <sys/mount.h> 53 #include <sys/msgbuf.h> 54 #include <sys/proc.h> 55 #include <sys/reboot.h> 56 #include <sys/syscallargs.h> 57 #include <sys/syslog.h> 58 #include <sys/systm.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #ifdef DDB 63 #include <powerpc/db_machdep.h> 64 #include <ddb/db_extern.h> 65 #endif 66 67 #ifdef KGDB 68 #include <sys/kgdb.h> 69 #endif 70 71 #ifdef IPKDB 72 #include <ipkdb/ipkdb.h> 73 #endif 74 75 #include <machine/powerpc.h> 76 77 #include <powerpc/trap.h> 78 #include <powerpc/spr.h> 79 #include <powerpc/pte.h> 80 #include <powerpc/altivec.h> 81 #include <powerpc/pcb.h> 82 83 #include <powerpc/oea/bat.h> 84 #include <powerpc/oea/cpufeat.h> 85 #include <powerpc/oea/spr.h> 86 #include <powerpc/oea/sr_601.h> 87 88 char machine[] = MACHINE; /* from <machine/param.h> */ 89 char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ 90 91 struct vm_map *phys_map = NULL; 92 93 /* 94 * Global variables used here and there 95 */ 96 static void trap0(void *); 97 98 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */ 99 struct bat battable[BAT_VA2IDX(0xffffffff)+1]; 100 101 register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */ 102 #ifndef MSGBUFADDR 103 paddr_t msgbuf_paddr; 104 #endif 105 106 extern int dsitrap_fix_dbat4[]; 107 extern int dsitrap_fix_dbat5[]; 108 extern int dsitrap_fix_dbat6[]; 109 extern int dsitrap_fix_dbat7[]; 110 111 void 112 oea_init(void (*handler)(void)) 113 { 114 extern int trapcode[], trapsize[]; 115 extern int sctrap[], scsize[]; 116 extern int alitrap[], alisize[]; 117 extern int dsitrap[], dsisize[]; 118 extern int trapstart[], trapend[]; 119 #ifdef PPC_OEA601 120 extern int dsi601trap[], dsi601size[]; 121 #endif 122 extern int decrint[], decrsize[]; 123 extern int tlbimiss[], tlbimsize[]; 124 extern int tlbdlmiss[], tlbdlmsize[]; 125 extern int tlbdsmiss[], tlbdsmsize[]; 126 #if defined(DDB) || defined(KGDB) 127 extern int ddblow[], ddbsize[]; 128 #endif 129 #ifdef IPKDB 130 extern int ipkdblow[], ipkdbsize[]; 131 #endif 132 #ifdef ALTIVEC 133 register_t msr; 134 #endif 135 uintptr_t exc, exc_base; 136 #if defined(ALTIVEC) || defined(PPC_OEA) 137 register_t scratch; 138 #endif 139 unsigned int cpuvers; 140 size_t size; 141 struct cpu_info * const ci = &cpu_info[0]; 142 143 #ifdef PPC_HIGH_VEC 144 exc_base = EXC_HIGHVEC; 145 #else 146 exc_base = 0; 147 #endif 148 KASSERT(mfspr(SPR_SPRG0) == (uintptr_t)ci); 149 150 cpuvers = mfpvr() >> 16; 151 152 /* 153 * Initialize proc0 and current pcb and pmap pointers. 154 */ 155 (void) ci; 156 KASSERT(ci != NULL); 157 KASSERT(curcpu() == ci); 158 KASSERT(lwp0.l_cpu == ci); 159 160 curpcb = lwp_getpcb(&lwp0); 161 memset(curpcb, 0, sizeof(struct pcb)); 162 163 #ifdef ALTIVEC 164 /* 165 * Initialize the vectors with NaNs 166 */ 167 for (scratch = 0; scratch < 32; scratch++) { 168 curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD; 169 curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD; 170 curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD; 171 curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD; 172 } 173 #endif 174 curpm = curpcb->pcb_pm = pmap_kernel(); 175 176 /* 177 * Cause a PGM trap if we branch to 0. 178 * 179 * XXX GCC4.1 complains about memset on address zero, so 180 * don't use the builtin. 181 */ 182 #undef memset 183 memset(0, 0, 0x100); 184 185 /* 186 * Set up trap vectors. Don't assume vectors are on 0x100. 187 */ 188 for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) { 189 switch (exc - exc_base) { 190 default: 191 size = (size_t)trapsize; 192 memcpy((void *)exc, trapcode, size); 193 break; 194 #if 0 195 case EXC_EXI: 196 /* 197 * This one is (potentially) installed during autoconf 198 */ 199 break; 200 #endif 201 case EXC_SC: 202 size = (size_t)scsize; 203 memcpy((void *)exc, sctrap, size); 204 break; 205 case EXC_ALI: 206 size = (size_t)alisize; 207 memcpy((void *)exc, alitrap, size); 208 break; 209 case EXC_DSI: 210 #ifdef PPC_OEA601 211 if (cpuvers == MPC601) { 212 size = (size_t)dsi601size; 213 memcpy((void *)exc, dsi601trap, size); 214 break; 215 } else 216 #endif /* PPC_OEA601 */ 217 if (oeacpufeat & OEACPU_NOBAT) { 218 size = (size_t)alisize; 219 memcpy((void *)exc, alitrap, size); 220 } else { 221 size = (size_t)dsisize; 222 memcpy((void *)exc, dsitrap, size); 223 } 224 break; 225 case EXC_DECR: 226 size = (size_t)decrsize; 227 memcpy((void *)exc, decrint, size); 228 break; 229 case EXC_IMISS: 230 size = (size_t)tlbimsize; 231 memcpy((void *)exc, tlbimiss, size); 232 break; 233 case EXC_DLMISS: 234 size = (size_t)tlbdlmsize; 235 memcpy((void *)exc, tlbdlmiss, size); 236 break; 237 case EXC_DSMISS: 238 size = (size_t)tlbdsmsize; 239 memcpy((void *)exc, tlbdsmiss, size); 240 break; 241 case EXC_PERF: 242 size = (size_t)trapsize; 243 memcpy((void *)exc, trapcode, size); 244 memcpy((void *)(exc_base + EXC_VEC), trapcode, size); 245 break; 246 #if defined(DDB) || defined(IPKDB) || defined(KGDB) 247 case EXC_RUNMODETRC: 248 #ifdef PPC_OEA601 249 if (cpuvers != MPC601) { 250 #endif 251 size = (size_t)trapsize; 252 memcpy((void *)exc, trapcode, size); 253 break; 254 #ifdef PPC_OEA601 255 } 256 /* FALLTHROUGH */ 257 #endif 258 case EXC_PGM: 259 case EXC_TRC: 260 case EXC_BPT: 261 #if defined(DDB) || defined(KGDB) 262 size = (size_t)ddbsize; 263 memcpy((void *)exc, ddblow, size); 264 #if defined(IPKDB) 265 #error "cannot enable IPKDB with DDB or KGDB" 266 #endif 267 #else 268 size = (size_t)ipkdbsize; 269 memcpy((void *)exc, ipkdblow, size); 270 #endif 271 break; 272 #endif /* DDB || IPKDB || KGDB */ 273 } 274 #if 0 275 exc += roundup(size, 32); 276 #endif 277 } 278 279 /* 280 * Install a branch absolute to trap0 to force a panic. 281 */ 282 if ((uintptr_t)trap0 < 0x2000000) { 283 *(uint32_t *) 0 = 0x7c6802a6; 284 *(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0; 285 } 286 287 /* 288 * Get the cache sizes because install_extint calls __syncicache. 289 */ 290 cpu_probe_cache(); 291 292 #define MxSPR_MASK 0x7c1fffff 293 #define MFSPR_MQ 0x7c0002a6 294 #define MTSPR_MQ 0x7c0003a6 295 #define MTSPR_IBAT0L 0x7c1183a6 296 #define MTSPR_IBAT1L 0x7c1383a6 297 #define NOP 0x60000000 298 #define B 0x48000000 299 #define TLBSYNC 0x7c00046c 300 #define SYNC 0x7c0004ac 301 302 #ifdef ALTIVEC 303 #define MFSPR_VRSAVE 0x7c0042a6 304 #define MTSPR_VRSAVE 0x7c0043a6 305 306 /* 307 * Try to set the VEC bit in the MSR. If it doesn't get set, we are 308 * not on a AltiVec capable processor. 309 */ 310 __asm volatile ( 311 "mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; " 312 "mfmsr %1; mtmsr %0; isync" 313 : "=r"(msr), "=r"(scratch) 314 : "J"(PSL_VEC)); 315 316 /* 317 * If we aren't on an AltiVec capable processor, we need to zap any of 318 * the sequences we save/restore the VRSAVE SPR into NOPs. 319 */ 320 if (scratch & PSL_VEC) { 321 cpu_altivec = 1; 322 } else { 323 int *ip = trapstart; 324 325 for (; ip < trapend; ip++) { 326 if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) { 327 ip[0] = NOP; /* mfspr */ 328 ip[1] = NOP; /* stw */ 329 } else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) { 330 ip[-1] = NOP; /* lwz */ 331 ip[0] = NOP; /* mtspr */ 332 } 333 } 334 } 335 #endif 336 337 /* XXX It would seem like this code could be elided ifndef 601, but 338 * doing so breaks my power3 machine. 339 */ 340 /* 341 * If we aren't on a MPC601 processor, we need to zap any of the 342 * sequences we save/restore the MQ SPR into NOPs, and skip over the 343 * sequences where we zap/restore BAT registers on kernel exit/entry. 344 */ 345 if (cpuvers != MPC601) { 346 int *ip = trapstart; 347 348 for (; ip < trapend; ip++) { 349 if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) { 350 ip[0] = NOP; /* mfspr */ 351 ip[1] = NOP; /* stw */ 352 } else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) { 353 ip[-1] = NOP; /* lwz */ 354 ip[0] = NOP; /* mtspr */ 355 } else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) { 356 if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L) 357 ip[-1] = B | 0x14; /* li */ 358 else 359 ip[-4] = B | 0x24; /* lis */ 360 } 361 } 362 } 363 364 /* 365 * Sync the changed instructions. 366 */ 367 __syncicache((void *) trapstart, 368 (uintptr_t) trapend - (uintptr_t) trapstart); 369 __syncicache(dsitrap_fix_dbat4, 16); 370 __syncicache(dsitrap_fix_dbat7, 8); 371 #ifdef PPC_OEA601 372 373 /* 374 * If we are on a MPC601 processor, we need to zap any tlbsync 375 * instructions into sync. This differs from the above in 376 * examing all kernel text, as opposed to just the exception handling. 377 * We sync the icache on every instruction found since there are 378 * only very few of them. 379 */ 380 if (cpuvers == MPC601) { 381 extern int kernel_text[], etext[]; 382 int *ip; 383 384 for (ip = kernel_text; ip < etext; ip++) 385 if (*ip == TLBSYNC) { 386 *ip = SYNC; 387 __syncicache(ip, sizeof(*ip)); 388 } 389 } 390 #endif /* PPC_OEA601 */ 391 392 /* 393 * Configure a PSL user mask matching this processor. 394 */ 395 cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 396 cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE; 397 #ifdef PPC_OEA601 398 if (cpuvers == MPC601) { 399 cpu_psluserset &= PSL_601_MASK; 400 cpu_pslusermod &= PSL_601_MASK; 401 } 402 #endif 403 #ifdef ALTIVEC 404 if (cpu_altivec) 405 cpu_pslusermod |= PSL_VEC; 406 #endif 407 #ifdef PPC_HIGH_VEC 408 cpu_psluserset |= PSL_IP; /* XXX ok? */ 409 #endif 410 411 /* 412 * external interrupt handler install 413 */ 414 if (handler) 415 oea_install_extint(handler); 416 417 __syncicache((void *)exc_base, EXC_LAST + 0x100); 418 419 /* 420 * Now enable translation (and machine checks/recoverable interrupts). 421 */ 422 #ifdef PPC_OEA 423 __asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync" 424 : "=r"(scratch) 425 : "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI)); 426 #endif 427 428 /* 429 * Let's take all the indirect calls via our stubs and patch 430 * them to be direct calls. 431 */ 432 cpu_fixup_stubs(); 433 434 KASSERT(curcpu() == ci); 435 } 436 437 #ifdef PPC_OEA601 438 void 439 mpc601_ioseg_add(paddr_t pa, register_t len) 440 { 441 const u_int i = pa >> ADDR_SR_SHFT; 442 443 if (len != BAT_BL_256M) 444 panic("mpc601_ioseg_add: len != 256M"); 445 446 /* 447 * Translate into an I/O segment, load it, and stash away for use 448 * in pmap_bootstrap(). 449 */ 450 iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i); 451 __asm volatile ("mtsrin %0,%1" 452 :: "r"(iosrtable[i]), 453 "r"(pa)); 454 } 455 #endif /* PPC_OEA601 */ 456 457 #if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE) 458 #define DBAT_SET(n, batl, batu) \ 459 do { \ 460 mtspr(SPR_DBAT##n##L, (batl)); \ 461 mtspr(SPR_DBAT##n##U, (batu)); \ 462 } while (/*CONSTCOND*/ 0) 463 #define DBAT_RESET(n) DBAT_SET(n, 0, 0) 464 #define DBATU_GET(n) mfspr(SPR_DBAT##n##U) 465 #define IBAT_SET(n, batl, batu) \ 466 do { \ 467 mtspr(SPR_IBAT##n##L, (batl)); \ 468 mtspr(SPR_IBAT##n##U, (batu)); \ 469 } while (/*CONSTCOND*/ 0) 470 #define IBAT_RESET(n) IBAT_SET(n, 0, 0) 471 472 void 473 oea_iobat_add(paddr_t pa, register_t len) 474 { 475 static int z = 1; 476 const u_int n = __SHIFTOUT(len, (BAT_XBL|BAT_BL) & ~BAT_BL_8M); 477 const u_int i = BAT_VA2IDX(pa) & -n; /* in case pa was in the middle */ 478 const int after_bat3 = (oeacpufeat & OEACPU_HIGHBAT) ? 4 : 8; 479 480 KASSERT(len >= BAT_BL_8M); 481 482 const register_t batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW); 483 const register_t batu = BATU(pa, len, BAT_Vs); 484 485 for (u_int j = 0; j < n; j++) { 486 battable[i + j].batl = batl; 487 battable[i + j].batu = batu; 488 } 489 490 /* 491 * Let's start loading the BAT registers. 492 */ 493 switch (z) { 494 case 1: 495 DBAT_SET(1, batl, batu); 496 z = 2; 497 break; 498 case 2: 499 DBAT_SET(2, batl, batu); 500 z = 3; 501 break; 502 case 3: 503 DBAT_SET(3, batl, batu); 504 z = after_bat3; /* no highbat, skip to end */ 505 break; 506 case 4: 507 DBAT_SET(4, batl, batu); 508 z = 5; 509 break; 510 case 5: 511 DBAT_SET(5, batl, batu); 512 z = 6; 513 break; 514 case 6: 515 DBAT_SET(6, batl, batu); 516 z = 7; 517 break; 518 case 7: 519 DBAT_SET(7, batl, batu); 520 z = 8; 521 break; 522 default: 523 break; 524 } 525 } 526 527 void 528 oea_iobat_remove(paddr_t pa) 529 { 530 const u_int i = BAT_VA2IDX(pa); 531 532 if (!BAT_VA_MATCH_P(battable[i].batu, pa) || 533 !BAT_VALID_P(battable[i].batu, PSL_PR)) 534 return; 535 const int n = 536 __SHIFTOUT(battable[i].batu, (BAT_XBL|BAT_BL) & ~BAT_BL_8M) + 1; 537 KASSERT((n & (n-1)) == 0); /* power of 2 */ 538 KASSERT((i & (n-1)) == 0); /* multiple of n */ 539 540 memset(&battable[i], 0, n*sizeof(battable[0])); 541 542 const int maxbat = oeacpufeat & OEACPU_HIGHBAT ? 8 : 4; 543 for (u_int k = 1 ; k < maxbat; k++) { 544 register_t batu; 545 switch (k) { 546 case 1: 547 batu = DBATU_GET(1); 548 if (BAT_VA_MATCH_P(batu, pa) && 549 BAT_VALID_P(batu, PSL_PR)) 550 DBAT_RESET(1); 551 break; 552 case 2: 553 batu = DBATU_GET(2); 554 if (BAT_VA_MATCH_P(batu, pa) && 555 BAT_VALID_P(batu, PSL_PR)) 556 DBAT_RESET(2); 557 break; 558 case 3: 559 batu = DBATU_GET(3); 560 if (BAT_VA_MATCH_P(batu, pa) && 561 BAT_VALID_P(batu, PSL_PR)) 562 DBAT_RESET(3); 563 break; 564 case 4: 565 batu = DBATU_GET(4); 566 if (BAT_VA_MATCH_P(batu, pa) && 567 BAT_VALID_P(batu, PSL_PR)) 568 DBAT_RESET(4); 569 break; 570 case 5: 571 batu = DBATU_GET(5); 572 if (BAT_VA_MATCH_P(batu, pa) && 573 BAT_VALID_P(batu, PSL_PR)) 574 DBAT_RESET(5); 575 break; 576 case 6: 577 batu = DBATU_GET(6); 578 if (BAT_VA_MATCH_P(batu, pa) && 579 BAT_VALID_P(batu, PSL_PR)) 580 DBAT_RESET(6); 581 break; 582 case 7: 583 batu = DBATU_GET(7); 584 if (BAT_VA_MATCH_P(batu, pa) && 585 BAT_VALID_P(batu, PSL_PR)) 586 DBAT_RESET(7); 587 break; 588 default: 589 break; 590 } 591 } 592 } 593 594 void 595 oea_batinit(paddr_t pa, ...) 596 { 597 struct mem_region *allmem, *availmem, *mp; 598 unsigned int cpuvers; 599 register_t msr = mfmsr(); 600 va_list ap; 601 602 cpuvers = mfpvr() >> 16; 603 /* 604 * we need to call this before zapping BATs so OF calls work 605 */ 606 mem_regions(&allmem, &availmem); 607 608 /* 609 * Initialize BAT registers to unmapped to not generate 610 * overlapping mappings below. 611 * 612 * The 601's implementation differs in the Valid bit being situated 613 * in the lower BAT register, and in being a unified BAT only whose 614 * four entries are accessed through the IBAT[0-3] SPRs. 615 * 616 * Also, while the 601 does distinguish between supervisor/user 617 * protection keys, it does _not_ distinguish between validity in 618 * supervisor/user mode. 619 */ 620 if ((msr & (PSL_IR|PSL_DR)) == 0) { 621 #ifdef PPC_OEA601 622 if (cpuvers == MPC601) { 623 __asm volatile ("mtibatl 0,%0" :: "r"(0)); 624 __asm volatile ("mtibatl 1,%0" :: "r"(0)); 625 __asm volatile ("mtibatl 2,%0" :: "r"(0)); 626 __asm volatile ("mtibatl 3,%0" :: "r"(0)); 627 } else 628 #endif /* PPC_OEA601 */ 629 { 630 DBAT_RESET(0); IBAT_RESET(0); 631 DBAT_RESET(1); IBAT_RESET(1); 632 DBAT_RESET(2); IBAT_RESET(2); 633 DBAT_RESET(3); IBAT_RESET(3); 634 if (oeacpufeat & OEACPU_HIGHBAT) { 635 DBAT_RESET(4); IBAT_RESET(4); 636 DBAT_RESET(5); IBAT_RESET(5); 637 DBAT_RESET(6); IBAT_RESET(6); 638 DBAT_RESET(7); IBAT_RESET(7); 639 640 /* 641 * Change the first instruction to branch to 642 * dsitrap_fix_dbat6 643 */ 644 dsitrap_fix_dbat4[0] &= ~0xfffc; 645 dsitrap_fix_dbat4[0] 646 += (uintptr_t)dsitrap_fix_dbat6 647 - (uintptr_t)&dsitrap_fix_dbat4[0]; 648 649 /* 650 * Change the second instruction to branch to 651 * dsitrap_fix_dbat5 if bit 30 (aka bit 1) is 652 * true. 653 */ 654 dsitrap_fix_dbat4[1] = 0x419e0000 655 + (uintptr_t)dsitrap_fix_dbat5 656 - (uintptr_t)&dsitrap_fix_dbat4[1]; 657 658 /* 659 * Change it to load dbat4 instead of dbat2 660 */ 661 dsitrap_fix_dbat4[2] = 0x7fd88ba6; 662 dsitrap_fix_dbat4[3] = 0x7ff98ba6; 663 664 /* 665 * Change it to load dbat7 instead of dbat3 666 */ 667 dsitrap_fix_dbat7[0] = 0x7fde8ba6; 668 dsitrap_fix_dbat7[1] = 0x7fff8ba6; 669 } 670 } 671 } 672 673 /* 674 * Set up BAT to map physical memory 675 */ 676 #ifdef PPC_OEA601 677 if (cpuvers == MPC601) { 678 int i; 679 680 /* 681 * Set up battable to map the lowest 256 MB area. 682 * Map the lowest 32 MB area via BAT[0-3]; 683 * BAT[01] are fixed, BAT[23] are floating. 684 */ 685 for (i = 0; i < 32; i++) { 686 battable[i].batl = BATL601(i << 23, 687 BAT601_BSM_8M, BAT601_V); 688 battable[i].batu = BATU601(i << 23, 689 BAT601_M, BAT601_Ku, BAT601_PP_NONE); 690 } 691 __asm volatile ("mtibatu 0,%1; mtibatl 0,%0" 692 :: "r"(battable[0x00000000 >> 23].batl), 693 "r"(battable[0x00000000 >> 23].batu)); 694 __asm volatile ("mtibatu 1,%1; mtibatl 1,%0" 695 :: "r"(battable[0x00800000 >> 23].batl), 696 "r"(battable[0x00800000 >> 23].batu)); 697 __asm volatile ("mtibatu 2,%1; mtibatl 2,%0" 698 :: "r"(battable[0x01000000 >> 23].batl), 699 "r"(battable[0x01000000 >> 23].batu)); 700 __asm volatile ("mtibatu 3,%1; mtibatl 3,%0" 701 :: "r"(battable[0x01800000 >> 23].batl), 702 "r"(battable[0x01800000 >> 23].batu)); 703 } 704 #endif /* PPC_OEA601 */ 705 706 /* 707 * Now setup other fixed bat registers 708 * 709 * Note that we still run in real mode, and the BAT 710 * registers were cleared above. 711 */ 712 713 va_start(ap, pa); 714 715 /* 716 * Add any I/O BATs specificed; 717 * use I/O segments on the BAT-starved 601. 718 */ 719 #ifdef PPC_OEA601 720 if (cpuvers == MPC601) { 721 while (pa != 0) { 722 register_t len = va_arg(ap, register_t); 723 mpc601_ioseg_add(pa, len); 724 pa = va_arg(ap, paddr_t); 725 } 726 } else 727 #endif 728 { 729 while (pa != 0) { 730 register_t len = va_arg(ap, register_t); 731 oea_iobat_add(pa, len); 732 pa = va_arg(ap, paddr_t); 733 } 734 } 735 736 va_end(ap); 737 738 /* 739 * Set up battable to map all RAM regions. 740 */ 741 #ifdef PPC_OEA601 742 if (cpuvers == MPC601) { 743 for (mp = allmem; mp->size; mp++) { 744 paddr_t paddr = mp->start & 0xff800000; 745 paddr_t end = mp->start + mp->size; 746 747 do { 748 u_int ix = paddr >> 23; 749 750 battable[ix].batl = 751 BATL601(paddr, BAT601_BSM_8M, BAT601_V); 752 battable[ix].batu = 753 BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE); 754 paddr += (1 << 23); 755 } while (paddr < end); 756 } 757 } else 758 #endif 759 { 760 const register_t bat_inc = BAT_IDX2VA(1); 761 for (mp = allmem; mp->size; mp++) { 762 paddr_t paddr = mp->start & -bat_inc; 763 paddr_t end = roundup2(mp->start + mp->size, bat_inc); 764 765 /* 766 * If the next entries are adjacent, merge them 767 * into this one 768 */ 769 while (mp[1].size && end == (mp[1].start & -bat_inc)) { 770 mp++; 771 end = roundup2(mp->start + mp->size, bat_inc); 772 } 773 774 while (paddr < end) { 775 register_t bl = (oeacpufeat & OEACPU_XBSEN 776 ? BAT_BL_2G 777 : BAT_BL_256M); 778 psize_t size = BAT_BL_TO_SIZE(bl); 779 u_int n = BAT_VA2IDX(size); 780 u_int i = BAT_VA2IDX(paddr); 781 782 while ((paddr & (size - 1)) 783 || paddr + size > end) { 784 size >>= 1; 785 bl = (bl >> 1) & (BAT_XBL|BAT_BL); 786 n >>= 1; 787 } 788 789 KASSERT(size >= bat_inc); 790 KASSERT(n >= 1); 791 KASSERT(bl >= BAT_BL_8M); 792 793 register_t batl = BATL(paddr, BAT_M, BAT_PP_RW); 794 register_t batu = BATU(paddr, bl, BAT_Vs); 795 796 for (; n-- > 0; i++) { 797 battable[i].batl = batl; 798 battable[i].batu = batu; 799 } 800 paddr += size; 801 } 802 } 803 /* 804 * Set up BAT0 to only map the lowest area. 805 */ 806 __asm volatile ("mtibatl 0,%0; mtibatu 0,%1;" 807 "mtdbatl 0,%0; mtdbatu 0,%1;" 808 :: "r"(battable[0].batl), "r"(battable[0].batu)); 809 } 810 } 811 #endif /* PPC_OEA || PPC_OEA64_BRIDGE */ 812 813 void 814 oea_install_extint(void (*handler)(void)) 815 { 816 extern int extint[], extsize[]; 817 extern int extint_call[]; 818 uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call; 819 int omsr, msr; 820 821 #ifdef DIAGNOSTIC 822 if (offset > 0x1ffffff) 823 panic("install_extint: %p too far away (%#lx)", handler, 824 (unsigned long) offset); 825 #endif 826 __asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1" 827 : "=r" (omsr), "=r" (msr) 828 : "K" ((u_short)~PSL_EE)); 829 extint_call[0] = (extint_call[0] & 0xfc000003) | offset; 830 __syncicache((void *)extint_call, sizeof extint_call[0]); 831 #ifdef PPC_HIGH_VEC 832 memcpy((void *)(EXC_HIGHVEC + EXC_EXI), extint, (size_t)extsize); 833 __syncicache((void *)(EXC_HIGHVEC + EXC_EXI), (int)extsize); 834 #else 835 memcpy((void *)EXC_EXI, extint, (size_t)extsize); 836 __syncicache((void *)EXC_EXI, (int)extsize); 837 #endif 838 __asm volatile ("mtmsr %0" :: "r"(omsr)); 839 } 840 841 /* 842 * Machine dependent startup code. 843 */ 844 void 845 oea_startup(const char *model) 846 { 847 uintptr_t sz; 848 void *v; 849 vaddr_t minaddr, maxaddr; 850 char pbuf[9]; 851 852 KASSERT(curcpu() != NULL); 853 KASSERT(lwp0.l_cpu != NULL); 854 KASSERT(curcpu()->ci_idepth == -1); 855 856 sz = round_page(MSGBUFSIZE); 857 #ifdef MSGBUFADDR 858 v = (void *) MSGBUFADDR; 859 #else 860 /* 861 * If the msgbuf is not in segment 0, allocate KVA for it and access 862 * it via mapped pages. [This prevents unneeded BAT switches.] 863 */ 864 v = (void *) msgbuf_paddr; 865 if (msgbuf_paddr + sz > SEGMENT_LENGTH) { 866 u_int i; 867 868 minaddr = 0; 869 if (uvm_map(kernel_map, &minaddr, sz, 870 NULL, UVM_UNKNOWN_OFFSET, 0, 871 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, 872 UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) 873 panic("startup: cannot allocate VM for msgbuf"); 874 v = (void *)minaddr; 875 for (i = 0; i < sz; i += PAGE_SIZE) { 876 pmap_kenter_pa(minaddr + i, msgbuf_paddr + i, 877 VM_PROT_READ|VM_PROT_WRITE, 0); 878 } 879 pmap_update(pmap_kernel()); 880 } 881 #endif 882 initmsgbuf(v, sz); 883 884 printf("%s%s", copyright, version); 885 if (model != NULL) 886 printf("Model: %s\n", model); 887 cpu_identify(NULL, 0); 888 889 format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem)); 890 printf("total memory = %s\n", pbuf); 891 892 /* 893 * Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after 894 * the bufpages are allocated in case they overlap since it's not 895 * fatal if we can't allocate these. 896 */ 897 if (KERNEL_SR == 13 || KERNEL2_SR == 14) { 898 int error; 899 minaddr = 0xDEAC0000; 900 error = uvm_map(kernel_map, &minaddr, 0x30000, 901 NULL, UVM_UNKNOWN_OFFSET, 0, 902 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 903 UVM_ADV_NORMAL, UVM_FLAG_FIXED)); 904 if (error != 0 || minaddr != 0xDEAC0000) 905 printf("oea_startup: failed to allocate DEAD " 906 "ZONE: error=%d\n", error); 907 } 908 909 minaddr = 0; 910 911 /* 912 * Allocate a submap for physio 913 */ 914 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 915 VM_PHYS_SIZE, 0, false, NULL); 916 917 format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free)); 918 printf("avail memory = %s\n", pbuf); 919 } 920 921 /* 922 * Crash dump handling. 923 */ 924 925 void 926 oea_dumpsys(void) 927 { 928 printf("dumpsys: TBD\n"); 929 } 930 931 /* 932 * Convert kernel VA to physical address 933 */ 934 paddr_t 935 kvtop(void *addr) 936 { 937 vaddr_t va; 938 paddr_t pa; 939 uintptr_t off; 940 extern char end[]; 941 942 if (addr < (void *)end) 943 return (paddr_t)addr; 944 945 va = trunc_page((vaddr_t)addr); 946 off = (uintptr_t)addr - va; 947 948 if (pmap_extract(pmap_kernel(), va, &pa) == false) { 949 /*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/ 950 return (paddr_t)addr; 951 } 952 953 return(pa + off); 954 } 955 956 /* 957 * Allocate vm space and mapin the I/O address 958 */ 959 void * 960 mapiodev(paddr_t pa, psize_t len, bool prefetchable) 961 { 962 paddr_t faddr; 963 vaddr_t taddr, va; 964 int off; 965 966 faddr = trunc_page(pa); 967 off = pa - faddr; 968 len = round_page(off + len); 969 va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY); 970 971 if (va == 0) 972 return NULL; 973 974 for (; len > 0; len -= PAGE_SIZE) { 975 pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE, 976 (prefetchable ? PMAP_MD_PREFETCHABLE : PMAP_NOCACHE)); 977 faddr += PAGE_SIZE; 978 taddr += PAGE_SIZE; 979 } 980 pmap_update(pmap_kernel()); 981 return (void *)(va + off); 982 } 983 984 void 985 unmapiodev(vaddr_t va, vsize_t len) 986 { 987 paddr_t faddr; 988 989 if (! va) 990 return; 991 992 faddr = trunc_page(va); 993 len = round_page(va - faddr + len); 994 995 pmap_kremove(faddr, len); 996 pmap_update(pmap_kernel()); 997 uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY); 998 } 999 1000 void 1001 trap0(void *lr) 1002 { 1003 panic("call to null-ptr from %p", lr); 1004 } 1005
Indexes created Wed Oct 01 13:09:50 GMT 2025