1 1.9 andvar /* $NetBSD: pic_mpcsoc.c,v 1.9 2022/02/23 21:54:40 andvar Exp $ */ 2 1.1 nisimura 3 1.1 nisimura /*- 4 1.1 nisimura * Copyright (c) 2007 Michael Lorenz 5 1.1 nisimura * All rights reserved. 6 1.1 nisimura * 7 1.1 nisimura * Redistribution and use in source and binary forms, with or without 8 1.1 nisimura * modification, are permitted provided that the following conditions 9 1.1 nisimura * are met: 10 1.1 nisimura * 1. Redistributions of source code must retain the above copyright 11 1.1 nisimura * notice, this list of conditions and the following disclaimer. 12 1.1 nisimura * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 nisimura * notice, this list of conditions and the following disclaimer in the 14 1.1 nisimura * documentation and/or other materials provided with the distribution. 15 1.1 nisimura * 16 1.1 nisimura * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 1.1 nisimura * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.1 nisimura * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1 nisimura * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 1.1 nisimura * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.1 nisimura * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.1 nisimura * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.1 nisimura * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.1 nisimura * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.1 nisimura * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1 nisimura * POSSIBILITY OF SUCH DAMAGE. 27 1.1 nisimura */ 28 1.1 nisimura 29 1.1 nisimura #include <sys/cdefs.h> 30 1.9 andvar __KERNEL_RCSID(0, "$NetBSD: pic_mpcsoc.c,v 1.9 2022/02/23 21:54:40 andvar Exp $"); 31 1.8 rin 32 1.8 rin #ifdef _KERNEL_OPT 33 1.8 rin #include "opt_interrupt.h" 34 1.8 rin #endif 35 1.1 nisimura 36 1.1 nisimura #include <sys/param.h> 37 1.5 matt #include <sys/kmem.h> 38 1.1 nisimura #include <sys/kernel.h> 39 1.1 nisimura 40 1.1 nisimura #include <uvm/uvm_extern.h> 41 1.1 nisimura 42 1.1 nisimura #include <machine/pio.h> 43 1.1 nisimura #include <powerpc/openpic.h> 44 1.1 nisimura 45 1.2 matt #include <powerpc/pic/picvar.h> 46 1.1 nisimura 47 1.1 nisimura static void mpcpic_enable_irq(struct pic_ops *, int, int); 48 1.1 nisimura static void mpcpic_disable_irq(struct pic_ops *, int); 49 1.1 nisimura static void mpcpic_establish_irq(struct pic_ops *, int, int, int); 50 1.1 nisimura static void mpcpic_finish_setup(struct pic_ops *); 51 1.1 nisimura 52 1.1 nisimura static u_int steer8245[] = { 53 1.1 nisimura 0x10200, /* external irq 0 direct/serial */ 54 1.1 nisimura 0x10220, /* external irq 1 direct/serial */ 55 1.1 nisimura 0x10240, /* external irq 2 direct/serial */ 56 1.1 nisimura 0x10260, /* external irq 3 direct/serial */ 57 1.1 nisimura 0x10280, /* external irq 4 direct/serial */ 58 1.1 nisimura 0x102a0, /* external irq 5 serial mode */ 59 1.1 nisimura 0x102c0, /* external irq 6 serial mode */ 60 1.1 nisimura 0x102e0, /* external irq 7 serial mode */ 61 1.1 nisimura 0x10300, /* external irq 8 serial mode */ 62 1.1 nisimura 0x10320, /* external irq 9 serial mode */ 63 1.1 nisimura 0x10340, /* external irq 10 serial mode */ 64 1.1 nisimura 0x10360, /* external irq 11 serial mode */ 65 1.1 nisimura 0x10380, /* external irq 12 serial mode */ 66 1.1 nisimura 0x103a0, /* external irq 13 serial mode */ 67 1.1 nisimura 0x103c0, /* external irq 14 serial mode */ 68 1.1 nisimura 0x103e0, /* external irq 15 serial mode */ 69 1.1 nisimura 0x11020, /* I2C */ 70 1.1 nisimura 0x11040, /* DMA 0 */ 71 1.1 nisimura 0x11060, /* DMA 1 */ 72 1.1 nisimura 0x110c0, /* MU/I2O */ 73 1.1 nisimura 0x01120, /* Timer 0 */ 74 1.1 nisimura 0x01160, /* Timer 1 */ 75 1.1 nisimura 0x011a0, /* Timer 2 */ 76 1.1 nisimura 0x011e0, /* Timer 3 */ 77 1.1 nisimura 0x11120, /* DUART 0, MPC8245 */ 78 1.1 nisimura 0x11140, /* DUART 1, MPC8245 */ 79 1.1 nisimura }; 80 1.1 nisimura #define MPCPIC_IVEC(n) (steer8245[(n)]) 81 1.1 nisimura #define MPCPIC_IDST(n) (steer8245[(n)] + 0x10) 82 1.1 nisimura 83 1.1 nisimura static int i8259iswired = 0; 84 1.1 nisimura 85 1.1 nisimura struct pic_ops * 86 1.1 nisimura setup_mpcpic(void *addr) 87 1.1 nisimura { 88 1.1 nisimura struct openpic_ops *ops; 89 1.1 nisimura struct pic_ops *self; 90 1.1 nisimura int irq; 91 1.1 nisimura u_int x; 92 1.1 nisimura 93 1.1 nisimura openpic_base = addr; 94 1.5 matt ops = kmem_alloc(sizeof(*ops), KM_SLEEP); 95 1.1 nisimura self = &ops->pic; 96 1.1 nisimura 97 1.1 nisimura x = openpic_read(OPENPIC_FEATURE); 98 1.1 nisimura if (((x & 0x07ff0000) >> 16) == 0) 99 1.1 nisimura panic("setup_mpcpic() called on distributed openpic"); 100 1.1 nisimura 101 1.1 nisimura aprint_normal("OpenPIC Version 1.%d: " 102 1.1 nisimura "Supports %d CPUs and %d interrupt sources.\n", 103 1.1 nisimura x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1); 104 1.1 nisimura 105 1.1 nisimura #ifdef PIC_I8259 106 1.1 nisimura i8259iswired = 1; 107 1.1 nisimura #endif 108 1.1 nisimura self->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1; 109 1.1 nisimura self->pic_cookie = addr; 110 1.1 nisimura self->pic_enable_irq = mpcpic_enable_irq; 111 1.1 nisimura self->pic_reenable_irq = mpcpic_enable_irq; 112 1.1 nisimura self->pic_disable_irq = mpcpic_disable_irq; 113 1.1 nisimura self->pic_get_irq = opic_get_irq; 114 1.1 nisimura self->pic_ack_irq = opic_ack_irq; 115 1.1 nisimura self->pic_establish_irq = mpcpic_establish_irq; 116 1.1 nisimura self->pic_finish_setup = mpcpic_finish_setup; 117 1.1 nisimura ops->isu = NULL; 118 1.1 nisimura ops->nrofisus = 0; /* internal only */ 119 1.1 nisimura ops->flags = 0; /* no flags (yet) */ 120 1.1 nisimura ops->irq_per = NULL; /* internal ISU only */ 121 1.1 nisimura strcpy(self->pic_name, "mpcpic"); 122 1.1 nisimura pic_add(self); 123 1.1 nisimura 124 1.1 nisimura openpic_set_priority(0, 15); 125 1.1 nisimura for (irq = 0; irq < self->pic_numintrs; irq++) { 126 1.1 nisimura /* make sure to keep disabled */ 127 1.1 nisimura openpic_write(MPCPIC_IVEC(irq), OPENPIC_IMASK); 128 1.1 nisimura /* send all interrupts to CPU 0 */ 129 1.1 nisimura openpic_write(MPCPIC_IDST(irq), 1 << 0); 130 1.1 nisimura } 131 1.1 nisimura openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff); 132 1.1 nisimura openpic_set_priority(0, 0); 133 1.1 nisimura 134 1.9 andvar /* clear all pending interrupts */ 135 1.1 nisimura for (irq = 0; irq < self->pic_numintrs; irq++) { 136 1.1 nisimura openpic_read_irq(0); 137 1.1 nisimura openpic_eoi(0); 138 1.1 nisimura } 139 1.1 nisimura 140 1.1 nisimura #if 0 141 1.1 nisimura printf("timebase freq=%d\n", openpic_read(0x10f0)); 142 1.1 nisimura #endif 143 1.1 nisimura return self; 144 1.1 nisimura } 145 1.1 nisimura 146 1.1 nisimura void 147 1.4 matt mpcpic_reserv16(void) 148 1.1 nisimura { 149 1.1 nisimura extern int max_base; /* intr.c */ 150 1.1 nisimura 151 1.1 nisimura /* 152 1.1 nisimura * reserve 16 irq slot for the case when no i8259 exists to use. 153 1.1 nisimura */ 154 1.1 nisimura max_base += 16; 155 1.1 nisimura } 156 1.1 nisimura 157 1.1 nisimura static void 158 1.1 nisimura mpcpic_establish_irq(struct pic_ops *pic, int irq, int type, int pri) 159 1.1 nisimura { 160 1.7 riastrad int realpri = uimax(1, uimin(15, pri)); 161 1.1 nisimura u_int x; 162 1.1 nisimura 163 1.1 nisimura x = irq; 164 1.1 nisimura x |= OPENPIC_IMASK; 165 1.3 phx 166 1.3 phx if ((i8259iswired && irq == 0) || 167 1.3 phx type == IST_EDGE_RISING || type == IST_LEVEL_HIGH) 168 1.3 phx x |= OPENPIC_POLARITY_POSITIVE; 169 1.3 phx else 170 1.3 phx x |= OPENPIC_POLARITY_NEGATIVE; 171 1.3 phx 172 1.3 phx if (type == IST_EDGE_FALLING || type == IST_EDGE_RISING) 173 1.3 phx x |= OPENPIC_SENSE_EDGE; 174 1.3 phx else 175 1.3 phx x |= OPENPIC_SENSE_LEVEL; 176 1.3 phx 177 1.1 nisimura x |= realpri << OPENPIC_PRIORITY_SHIFT; 178 1.1 nisimura openpic_write(MPCPIC_IVEC(irq), x); 179 1.1 nisimura 180 1.1 nisimura aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq, 181 1.1 nisimura realpri); 182 1.1 nisimura } 183 1.1 nisimura 184 1.1 nisimura static void 185 1.1 nisimura mpcpic_enable_irq(struct pic_ops *pic, int irq, int type) 186 1.1 nisimura { 187 1.1 nisimura u_int x; 188 1.1 nisimura 189 1.1 nisimura x = openpic_read(MPCPIC_IVEC(irq)); 190 1.1 nisimura x &= ~OPENPIC_IMASK; 191 1.1 nisimura openpic_write(MPCPIC_IVEC(irq), x); 192 1.1 nisimura } 193 1.1 nisimura 194 1.1 nisimura static void 195 1.1 nisimura mpcpic_disable_irq(struct pic_ops *pic, int irq) 196 1.1 nisimura { 197 1.1 nisimura u_int x; 198 1.1 nisimura 199 1.1 nisimura x = openpic_read(MPCPIC_IVEC(irq)); 200 1.1 nisimura x |= OPENPIC_IMASK; 201 1.1 nisimura openpic_write(MPCPIC_IVEC(irq), x); 202 1.1 nisimura } 203 1.1 nisimura 204 1.1 nisimura static void 205 1.1 nisimura mpcpic_finish_setup(struct pic_ops *pic) 206 1.1 nisimura { 207 1.1 nisimura uint32_t cpumask = 1; 208 1.1 nisimura int i; 209 1.1 nisimura 210 1.1 nisimura for (i = 0; i < pic->pic_numintrs; i++) { 211 1.1 nisimura /* send all interrupts to all active CPUs */ 212 1.1 nisimura openpic_write(MPCPIC_IDST(i), cpumask); 213 1.1 nisimura } 214 1.1 nisimura } 215