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pic_openpic.c revision 1.2
      1 /*	$NetBSD: pic_openpic.c,v 1.2 2007/10/17 19:56:46 garbled Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2007 Michael Lorenz
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. Neither the name of The NetBSD Foundation nor the names of its
     16  *    contributors may be used to endorse or promote products derived
     17  *    from this software without specific prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: pic_openpic.c,v 1.2 2007/10/17 19:56:46 garbled Exp $");
     34 
     35 #include <sys/param.h>
     36 #include <sys/malloc.h>
     37 #include <sys/kernel.h>
     38 
     39 #include <uvm/uvm_extern.h>
     40 
     41 #include <machine/pio.h>
     42 #include <powerpc/openpic.h>
     43 
     44 #include <arch/powerpc/pic/picvar.h>
     45 
     46 #include "opt_interrupt.h"
     47 
     48 void openpic_set_priority(int cpu, int pri);
     49 static void opic_enable_irq(struct pic_ops *, int, int);
     50 static void opic_disable_irq(struct pic_ops *, int);
     51 static int  opic_get_irq(struct pic_ops *);
     52 static void opic_ack_irq(struct pic_ops *, int);
     53 static void opic_establish_irq(struct pic_ops*, int, int, int);
     54 static void opic_finish_setup(struct pic_ops *);
     55 
     56 volatile unsigned char *openpic_base;
     57 
     58 struct pic_ops *
     59 setup_openpic(void *addr, int passthrough)
     60 {
     61 	struct pic_ops *pic;
     62 	int irq;
     63 	u_int x;
     64 
     65 	openpic_base = (void *)addr;
     66 	pic = malloc(sizeof(struct pic_ops), M_DEVBUF, M_NOWAIT);
     67 	KASSERT(pic != NULL);
     68 
     69 	x = openpic_read(OPENPIC_FEATURE);
     70 	aprint_normal("OpenPIC Version 1.%d: "
     71 	    "Supports %d CPUs and %d interrupt sources.\n",
     72 	    x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
     73 
     74 	pic->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1;
     75 	pic->pic_cookie = addr;
     76 	pic->pic_enable_irq = opic_enable_irq;
     77 	pic->pic_reenable_irq = opic_enable_irq;
     78 	pic->pic_disable_irq = opic_disable_irq;
     79 	pic->pic_get_irq = opic_get_irq;
     80 	pic->pic_ack_irq = opic_ack_irq;
     81 	pic->pic_establish_irq = opic_establish_irq;
     82 	pic->pic_finish_setup = opic_finish_setup;
     83 	strcpy(pic->pic_name, "openpic");
     84 	pic_add(pic);
     85 
     86 	/*
     87 	 * the following sequence should make the same effects as openpic
     88 	 * controller reset by writing a one at the self-clearing
     89 	 * OPENPIC_CONFIG_RESET bit.  Please check the document of your
     90 	 * OpenPIC compliant interrupt controller and see whether #else
     91 	 * portion can work as described.
     92 	 */
     93 #if 1
     94 	openpic_set_priority(0, 15);
     95 
     96 	for (irq = 0; irq < pic->pic_numintrs; irq++) {
     97 		/* make sure to keep disabled */
     98 		openpic_write(OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK);
     99 		/* send all interrupts to CPU 0 */
    100 		openpic_write(OPENPIC_IDEST(irq), 1 << 0);
    101 	}
    102 
    103 	x = openpic_read(OPENPIC_CONFIG);
    104 	if (passthrough)
    105 		x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
    106 	else
    107 		x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
    108 	openpic_write(OPENPIC_CONFIG, x);
    109 
    110 	openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff);
    111 
    112 	openpic_set_priority(0, 0);
    113 
    114 	/* clear all pending interrunts */
    115 	for (irq = 0; irq < pic->pic_numintrs; irq++) {
    116 		openpic_read_irq(0);
    117 		openpic_eoi(0);
    118 	}
    119 #else
    120 	irq = 0;
    121 	openpic_write(OPENPIC_CONFIG, OPENPIC_CONFIG_RESET);
    122 	do {
    123 		x = openpic_read(OPENPIC_CONFIG);
    124 	} while (x & OPENPIC_CONFIG_RESET); /* S1C bit */
    125 	if (passthrough)
    126 		x &= ~OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
    127 	else
    128 		x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
    129 	openpic_write(OPENPIC_CONFIG, x);
    130 	openpic_set_priority(0, 0);
    131 #endif
    132 
    133 #if 0
    134 	printf("timebase freq=%d\n", openpic_read(0x10f0));
    135 #endif
    136 	return pic;
    137 }
    138 
    139 static void
    140 opic_finish_setup(struct pic_ops *pic)
    141 {
    142 	uint32_t cpumask = 0;
    143 	int i;
    144 
    145 #ifdef OPENPIC_DISTRIBUTE
    146 	for (i = 0; i < ncpu; i++)
    147 		cpumask |= (1 << cpu_info[i].ci_cpuid);
    148 #else
    149 	cpumask = 1;
    150 #endif
    151 	for (i = 0; i < pic->pic_numintrs; i++) {
    152 		/* send all interrupts to all active CPUs */
    153 		openpic_write(OPENPIC_IDEST(i), cpumask);
    154 	}
    155 }
    156 
    157 static void
    158 opic_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
    159 {
    160 	int realpri = max(1, min(15, pri));
    161 	uint32_t x;
    162 
    163 	x = irq;
    164 	x |= OPENPIC_IMASK;
    165 	x |= (irq == 0) ?
    166 	    OPENPIC_POLARITY_POSITIVE :	OPENPIC_POLARITY_NEGATIVE;
    167 	x |= (type == IST_EDGE) ? OPENPIC_SENSE_EDGE : OPENPIC_SENSE_LEVEL;
    168 	x |= realpri << OPENPIC_PRIORITY_SHIFT;
    169 	openpic_write(OPENPIC_SRC_VECTOR(irq), x);
    170 
    171 	aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq, realpri);
    172 }
    173 
    174 void
    175 openpic_set_priority(int cpu, int pri)
    176 {
    177 	u_int x;
    178 
    179 	x = openpic_read(OPENPIC_CPU_PRIORITY(cpu));
    180 	x &= ~OPENPIC_CPU_PRIORITY_MASK;
    181 	x |= pri;
    182 	openpic_write(OPENPIC_CPU_PRIORITY(cpu), x);
    183 }
    184 
    185 static void
    186 opic_enable_irq(struct pic_ops *pic, int irq, int type)
    187 {
    188 	u_int x;
    189 
    190 	x = openpic_read(OPENPIC_SRC_VECTOR(irq));
    191 	x &= ~OPENPIC_IMASK;
    192 	openpic_write(OPENPIC_SRC_VECTOR(irq), x);
    193 }
    194 
    195 static void
    196 opic_disable_irq(struct pic_ops *pic, int irq)
    197 {
    198 	u_int x;
    199 
    200 	x = openpic_read(OPENPIC_SRC_VECTOR(irq));
    201 	x |= OPENPIC_IMASK;
    202 	openpic_write(OPENPIC_SRC_VECTOR(irq), x);
    203 }
    204 
    205 static int
    206 opic_get_irq(struct pic_ops *pic)
    207 {
    208 
    209 	return openpic_read_irq(cpu_number());
    210 }
    211 
    212 static void
    213 opic_ack_irq(struct pic_ops *pic, int irq)
    214 {
    215 
    216 	openpic_eoi(cpu_number());
    217 }
    218