db_interface.c revision 1.47 1 1.47 matt /* $NetBSD: db_interface.c,v 1.47 2011/06/20 05:59:06 matt Exp $ */
2 1.1 sakamoto /* $OpenBSD: db_interface.c,v 1.2 1996/12/28 06:21:50 rahnds Exp $ */
3 1.29 lukem
4 1.29 lukem #include <sys/cdefs.h>
5 1.47 matt __KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.47 2011/06/20 05:59:06 matt Exp $");
6 1.3 jonathan
7 1.10 simonb #define USERACC
8 1.10 simonb
9 1.3 jonathan #include "opt_ddb.h"
10 1.17 dbj #include "opt_kgdb.h"
11 1.10 simonb #include "opt_ppcarch.h"
12 1.1 sakamoto
13 1.1 sakamoto #include <sys/param.h>
14 1.1 sakamoto #include <sys/proc.h>
15 1.4 tsubai #include <sys/systm.h>
16 1.46 matt #include <sys/cpu.h>
17 1.6 kleink
18 1.11 simonb #include <dev/cons.h>
19 1.11 simonb
20 1.47 matt #include <powerpc/db_machdep.h>
21 1.47 matt #include <powerpc/frame.h>
22 1.43 phx #include <powerpc/spr.h>
23 1.43 phx #include <powerpc/pte.h>
24 1.47 matt #include <powerpc/psl.h>
25 1.43 phx
26 1.44 matt #if defined (PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE)
27 1.44 matt #include <powerpc/oea/spr.h>
28 1.46 matt #include <powerpc/oea/bat.h>
29 1.44 matt #endif
30 1.44 matt
31 1.10 simonb #ifdef PPC_IBM4XX
32 1.46 matt #include <powerpc/ibm4xx/cpu.h>
33 1.44 matt #include <powerpc/ibm4xx/spr.h>
34 1.10 simonb #include <machine/tlb.h>
35 1.10 simonb #include <uvm/uvm_extern.h>
36 1.10 simonb #endif
37 1.7 tsubai
38 1.44 matt #ifdef PPC_BOOKE
39 1.45 matt #include <powerpc/booke/cpuvar.h>
40 1.44 matt #include <powerpc/booke/spr.h>
41 1.44 matt #endif
42 1.44 matt
43 1.17 dbj #ifdef DDB
44 1.6 kleink #include <ddb/db_sym.h>
45 1.6 kleink #include <ddb/db_command.h>
46 1.6 kleink #include <ddb/db_extern.h>
47 1.6 kleink #include <ddb/db_access.h>
48 1.22 scw #include <ddb/db_lex.h>
49 1.6 kleink #include <ddb/db_output.h>
50 1.6 kleink #include <ddb/ddbvar.h>
51 1.17 dbj #endif
52 1.17 dbj
53 1.17 dbj #ifdef KGDB
54 1.17 dbj #include <sys/kgdb.h>
55 1.39 garbled #define db_printf printf
56 1.17 dbj #endif
57 1.17 dbj
58 1.17 dbj #include <dev/ofw/openfirm.h>
59 1.1 sakamoto
60 1.11 simonb int db_active = 0;
61 1.11 simonb
62 1.19 matt db_regs_t ddb_regs;
63 1.8 tsubai
64 1.10 simonb void ddb_trap(void); /* Call into trap_subr.S */
65 1.10 simonb int ddb_trap_glue(struct trapframe *); /* Called from trap_subr.S */
66 1.43 phx #if defined (PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE)
67 1.43 phx static void db_show_bat(db_expr_t, bool, db_expr_t, const char *);
68 1.43 phx static void db_show_mmu(db_expr_t, bool, db_expr_t, const char *);
69 1.43 phx #endif /* PPC_OEA || PPC_OEA64 || PPC_OEA64_BRIDGE */
70 1.10 simonb #ifdef PPC_IBM4XX
71 1.37 matt static void db_ppc4xx_ctx(db_expr_t, bool, db_expr_t, const char *);
72 1.37 matt static void db_ppc4xx_pv(db_expr_t, bool, db_expr_t, const char *);
73 1.37 matt static void db_ppc4xx_reset(db_expr_t, bool, db_expr_t, const char *);
74 1.37 matt static void db_ppc4xx_tf(db_expr_t, bool, db_expr_t, const char *);
75 1.37 matt static void db_ppc4xx_dumptlb(db_expr_t, bool, db_expr_t, const char *);
76 1.37 matt static void db_ppc4xx_dcr(db_expr_t, bool, db_expr_t, const char *);
77 1.22 scw static db_expr_t db_ppc4xx_mfdcr(db_expr_t);
78 1.22 scw static void db_ppc4xx_mtdcr(db_expr_t, db_expr_t);
79 1.10 simonb #ifdef USERACC
80 1.37 matt static void db_ppc4xx_useracc(db_expr_t, bool, db_expr_t, const char *);
81 1.10 simonb #endif
82 1.10 simonb #endif /* PPC_IBM4XX */
83 1.9 briggs
84 1.45 matt #ifdef PPC_BOOKE
85 1.45 matt static void db_ppcbooke_reset(db_expr_t, bool, db_expr_t, const char *);
86 1.45 matt static void db_ppcbooke_tf(db_expr_t, bool, db_expr_t, const char *);
87 1.45 matt static void db_ppcbooke_dumptlb(db_expr_t, bool, db_expr_t, const char *);
88 1.45 matt #endif
89 1.45 matt
90 1.17 dbj #ifdef DDB
91 1.43 phx const struct db_command db_machine_command_table[] = {
92 1.43 phx #if defined (PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE)
93 1.43 phx { DDB_ADD_CMD("bat", db_show_bat, 0,
94 1.43 phx "Print BAT register translations", NULL,NULL) },
95 1.43 phx { DDB_ADD_CMD("mmu", db_show_mmu, 0,
96 1.43 phx "Print MMU registers", NULL,NULL) },
97 1.43 phx #endif /* PPC_OEA || PPC_OEA64 || PPC_OEA64_BRIDGE */
98 1.43 phx #ifdef PPC_IBM4XX
99 1.43 phx { DDB_ADD_CMD("ctx", db_ppc4xx_ctx, 0,
100 1.43 phx "Print process MMU context information", NULL,NULL) },
101 1.43 phx { DDB_ADD_CMD("pv", db_ppc4xx_pv, 0,
102 1.43 phx "Print PA->VA mapping information",
103 1.43 phx "address",
104 1.43 phx " address:\tphysical address to look up") },
105 1.43 phx { DDB_ADD_CMD("reset", db_ppc4xx_reset, 0,
106 1.43 phx "Reset the system ", NULL,NULL) },
107 1.43 phx { DDB_ADD_CMD("tf", db_ppc4xx_tf, 0,
108 1.43 phx "Display the contents of the trapframe",
109 1.43 phx "address",
110 1.43 phx " address:\tthe struct trapframe to print") },
111 1.43 phx { DDB_ADD_CMD("tlb", db_ppc4xx_dumptlb, 0,
112 1.43 phx "Display instruction translation storage buffer information.",
113 1.43 phx NULL,NULL) },
114 1.43 phx { DDB_ADD_CMD("dcr", db_ppc4xx_dcr, CS_MORE|CS_SET_DOT,
115 1.43 phx "Set the DCR register",
116 1.43 phx "dcr",
117 1.43 phx " dcr:\tNew DCR value (between 0x0 and 0x3ff)") },
118 1.43 phx #ifdef USERACC
119 1.43 phx { DDB_ADD_CMD("user", db_ppc4xx_useracc, 0,
120 1.43 phx "Display user memory.", "[address][,count]",
121 1.43 phx " address:\tuserspace address to start\n"
122 1.43 phx " count:\tnumber of bytes to display") },
123 1.43 phx #endif
124 1.43 phx #endif /* PPC_IBM4XX */
125 1.45 matt #ifdef PPC_BOOKE
126 1.45 matt { DDB_ADD_CMD("reset", db_ppcbooke_reset, 0,
127 1.45 matt "Reset the system ", NULL,NULL) },
128 1.45 matt { DDB_ADD_CMD("tf", db_ppcbooke_tf, 0,
129 1.45 matt "Display the contents of the trapframe",
130 1.45 matt "address",
131 1.45 matt " address:\tthe struct trapframe to print") },
132 1.45 matt { DDB_ADD_CMD("tlb", db_ppcbooke_dumptlb, 0,
133 1.45 matt "Display instruction translation storage buffer information.",
134 1.45 matt NULL,NULL) },
135 1.45 matt #endif /* PPC_BOOKE */
136 1.43 phx { DDB_ADD_CMD(NULL, NULL, 0,
137 1.43 phx NULL,NULL,NULL) }
138 1.43 phx };
139 1.43 phx
140 1.1 sakamoto void
141 1.31 matt cpu_Debugger(void)
142 1.1 sakamoto {
143 1.45 matt #ifdef PPC_BOOKE
144 1.45 matt const register_t msr = mfmsr();
145 1.45 matt __asm volatile("wrteei 0\n\ttweq\t1,1");
146 1.45 matt mtmsr(msr);
147 1.45 matt __asm volatile("isync");
148 1.45 matt #else
149 1.1 sakamoto ddb_trap();
150 1.45 matt #endif
151 1.1 sakamoto }
152 1.45 matt #endif /* DDB */
153 1.1 sakamoto
154 1.1 sakamoto int
155 1.45 matt ddb_trap_glue(struct trapframe *tf)
156 1.1 sakamoto {
157 1.45 matt #if defined(PPC_IBM4XX) || defined(PPC_BOOKE)
158 1.45 matt if ((tf->tf_srr1 & PSL_PR) == 0)
159 1.45 matt return kdb_trap(tf->tf_exc, tf);
160 1.28 matt #else /* PPC_OEA */
161 1.45 matt if ((tf->tf_srr1 & PSL_PR) == 0 &&
162 1.45 matt (tf->tf_exc == EXC_TRC ||
163 1.45 matt tf->tf_exc == EXC_RUNMODETRC ||
164 1.45 matt (tf->tf_exc == EXC_PGM && (tf->tf_srr1 & 0x20000)) ||
165 1.45 matt tf->tf_exc == EXC_BPT ||
166 1.45 matt tf->tf_exc == EXC_DSI)) {
167 1.45 matt int type = tf->tf_exc;
168 1.45 matt if (type == EXC_PGM && (tf->tf_srr1 & 0x20000)) {
169 1.17 dbj type = T_BREAKPOINT;
170 1.17 dbj }
171 1.45 matt return kdb_trap(type, tf);
172 1.1 sakamoto }
173 1.25 thorpej #endif
174 1.1 sakamoto return 0;
175 1.8 tsubai }
176 1.8 tsubai
177 1.8 tsubai int
178 1.31 matt kdb_trap(int type, void *v)
179 1.8 tsubai {
180 1.45 matt struct trapframe *tf = v;
181 1.8 tsubai
182 1.17 dbj #ifdef DDB
183 1.30 matt if (db_recover != 0 && (type != -1 && type != T_BREAKPOINT)) {
184 1.30 matt db_error("Faulted in DDB; continuing...\n");
185 1.30 matt /* NOTREACHED */
186 1.8 tsubai }
187 1.17 dbj #endif
188 1.8 tsubai
189 1.8 tsubai /* XXX Should switch to kdb's own stack here. */
190 1.8 tsubai
191 1.45 matt memcpy(DDB_REGS->r, tf->tf_fixreg, 32 * sizeof(u_int32_t));
192 1.45 matt DDB_REGS->iar = tf->tf_srr0;
193 1.45 matt DDB_REGS->msr = tf->tf_srr1;
194 1.45 matt DDB_REGS->lr = tf->tf_lr;
195 1.45 matt DDB_REGS->ctr = tf->tf_ctr;
196 1.45 matt DDB_REGS->cr = tf->tf_cr;
197 1.45 matt DDB_REGS->xer = tf->tf_xer;
198 1.28 matt #ifdef PPC_OEA
199 1.45 matt DDB_REGS->mq = tf->tf_mq;
200 1.45 matt #elif defined(PPC_IBM4XX) || defined(PPC_BOOKE)
201 1.45 matt DDB_REGS->dear = tf->tf_dear;
202 1.45 matt DDB_REGS->esr = tf->tf_esr;
203 1.45 matt DDB_REGS->pid = tf->tf_pid;
204 1.10 simonb #endif
205 1.8 tsubai
206 1.17 dbj #ifdef DDB
207 1.11 simonb db_active++;
208 1.11 simonb cnpollc(1);
209 1.15 dbj db_trap(type, 0);
210 1.11 simonb cnpollc(0);
211 1.11 simonb db_active--;
212 1.17 dbj #elif defined(KGDB)
213 1.17 dbj if (!kgdb_trap(type, DDB_REGS))
214 1.17 dbj return 0;
215 1.17 dbj #endif
216 1.17 dbj
217 1.17 dbj /* KGDB isn't smart about advancing PC if we
218 1.17 dbj * take a breakpoint trap after kgdb_active is set.
219 1.17 dbj * Therefore, we help out here.
220 1.17 dbj */
221 1.17 dbj if (IS_BREAKPOINT_TRAP(type, 0)) {
222 1.17 dbj int bkpt;
223 1.17 dbj db_read_bytes(PC_REGS(DDB_REGS),BKPT_SIZE,(void *)&bkpt);
224 1.17 dbj if (bkpt== BKPT_INST) {
225 1.17 dbj PC_REGS(DDB_REGS) += BKPT_SIZE;
226 1.17 dbj }
227 1.17 dbj }
228 1.8 tsubai
229 1.45 matt memcpy(tf->tf_fixreg, DDB_REGS->r, 32 * sizeof(u_int32_t));
230 1.45 matt tf->tf_srr0 = DDB_REGS->iar;
231 1.45 matt tf->tf_srr1 = DDB_REGS->msr;
232 1.45 matt tf->tf_lr = DDB_REGS->lr;
233 1.45 matt tf->tf_ctr = DDB_REGS->ctr;
234 1.45 matt tf->tf_cr = DDB_REGS->cr;
235 1.45 matt tf->tf_xer = DDB_REGS->xer;
236 1.28 matt #ifdef PPC_OEA
237 1.45 matt tf->tf_mq = DDB_REGS->mq;
238 1.27 matt #endif
239 1.45 matt #if defined(PPC_IBM4XX) || defined(PPC_BOOKE)
240 1.45 matt tf->tf_dear = DDB_REGS->dear;
241 1.45 matt tf->tf_esr = DDB_REGS->esr;
242 1.45 matt tf->tf_pid = DDB_REGS->pid;
243 1.10 simonb #endif
244 1.8 tsubai
245 1.8 tsubai return 1;
246 1.1 sakamoto }
247 1.10 simonb
248 1.43 phx #if defined (PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE)
249 1.43 phx static void
250 1.43 phx print_battranslation(struct bat *bat, unsigned int blidx)
251 1.43 phx {
252 1.43 phx static const char *const batsizes[] = {
253 1.43 phx "128kB",
254 1.43 phx "256kB",
255 1.43 phx "512kB",
256 1.43 phx "1MB",
257 1.43 phx "2MB",
258 1.43 phx "4MB",
259 1.43 phx "8MB",
260 1.43 phx "16MB",
261 1.43 phx "32MB",
262 1.43 phx "64MB",
263 1.43 phx "128MB",
264 1.43 phx "256MB"
265 1.43 phx };
266 1.43 phx vsize_t len;
267 1.43 phx
268 1.43 phx len = (0x20000L << blidx) - 1;
269 1.43 phx db_printf("\t%08lx %08lx %5s: 0x%08lx..0x%08lx -> 0x%08lx physical\n",
270 1.43 phx bat->batu, bat->batl, batsizes[blidx], bat->batu & ~len,
271 1.43 phx (bat->batu & ~len) + len, bat->batl & ~len);
272 1.43 phx }
273 1.43 phx
274 1.43 phx static void
275 1.43 phx print_batmodes(register_t super, register_t user, register_t pp)
276 1.43 phx {
277 1.43 phx static const char *const accessmodes[] = {
278 1.43 phx "none",
279 1.43 phx "ro soft",
280 1.43 phx "read/write",
281 1.43 phx "read only"
282 1.43 phx };
283 1.43 phx
284 1.43 phx db_printf("\tvalid: %c%c access: %-10s memory:",
285 1.43 phx super ? 'S' : '-', user ? 'U' : '-', accessmodes[pp]);
286 1.43 phx }
287 1.43 phx
288 1.43 phx static void
289 1.43 phx print_wimg(register_t wimg)
290 1.43 phx {
291 1.43 phx if (wimg & BAT_W)
292 1.43 phx db_printf(" wrthrough");
293 1.43 phx if (wimg & BAT_I)
294 1.43 phx db_printf(" nocache");
295 1.43 phx if (wimg & BAT_M)
296 1.43 phx db_printf(" coherent");
297 1.43 phx if (wimg & BAT_G)
298 1.43 phx db_printf(" guard");
299 1.43 phx }
300 1.43 phx
301 1.43 phx static void
302 1.43 phx print_bat(struct bat *bat)
303 1.43 phx {
304 1.43 phx if ((bat->batu & BAT_V) == 0) {
305 1.43 phx db_printf("\tdisabled\n\n");
306 1.43 phx return;
307 1.43 phx }
308 1.43 phx print_battranslation(bat, 30 - __builtin_clz((bat->batu & BAT_BL)|2));
309 1.43 phx print_batmodes(bat->batu & BAT_Vs, bat->batu & BAT_Vu,
310 1.43 phx bat->batl & BAT_PP);
311 1.43 phx print_wimg(bat->batl & BAT_WIMG);
312 1.43 phx db_printf("\n");
313 1.43 phx }
314 1.43 phx
315 1.43 phx #ifdef PPC_OEA601
316 1.43 phx static void
317 1.43 phx print_bat601(struct bat *bat)
318 1.43 phx {
319 1.43 phx if ((bat->batl & BAT601_V) == 0) {
320 1.43 phx db_printf("\tdisabled\n\n");
321 1.43 phx return;
322 1.43 phx }
323 1.43 phx print_battranslation(bat, 32 - __builtin_clz(bat->batl & BAT601_BSM));
324 1.43 phx print_batmodes(bat->batu & BAT601_Ks, bat->batu & BAT601_Ku,
325 1.43 phx bat->batu & BAT601_PP);
326 1.43 phx print_wimg(bat->batu & (BAT601_W | BAT601_I | BAT601_M));
327 1.43 phx db_printf("\n");
328 1.43 phx }
329 1.43 phx #endif
330 1.43 phx
331 1.43 phx static void
332 1.43 phx db_show_bat(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
333 1.43 phx {
334 1.43 phx struct bat ibat[4];
335 1.43 phx struct bat dbat[4];
336 1.43 phx unsigned int cpuvers;
337 1.43 phx int i;
338 1.43 phx
339 1.43 phx cpuvers = mfpvr() >> 16;
340 1.43 phx
341 1.43 phx __asm volatile ("mfibatu %0,0" : "=r"(ibat[0].batu));
342 1.43 phx __asm volatile ("mfibatl %0,0" : "=r"(ibat[0].batl));
343 1.43 phx __asm volatile ("mfibatu %0,1" : "=r"(ibat[1].batu));
344 1.43 phx __asm volatile ("mfibatl %0,1" : "=r"(ibat[1].batl));
345 1.43 phx __asm volatile ("mfibatu %0,2" : "=r"(ibat[2].batu));
346 1.43 phx __asm volatile ("mfibatl %0,2" : "=r"(ibat[2].batl));
347 1.43 phx __asm volatile ("mfibatu %0,3" : "=r"(ibat[3].batu));
348 1.43 phx __asm volatile ("mfibatl %0,3" : "=r"(ibat[3].batl));
349 1.43 phx
350 1.43 phx if (cpuvers != MPC601) {
351 1.43 phx /* The 601 has only four unified BATs */
352 1.43 phx __asm volatile ("mfdbatu %0,0" : "=r"(dbat[0].batu));
353 1.43 phx __asm volatile ("mfdbatl %0,0" : "=r"(dbat[0].batl));
354 1.43 phx __asm volatile ("mfdbatu %0,1" : "=r"(dbat[1].batu));
355 1.43 phx __asm volatile ("mfdbatl %0,1" : "=r"(dbat[1].batl));
356 1.43 phx __asm volatile ("mfdbatu %0,2" : "=r"(dbat[2].batu));
357 1.43 phx __asm volatile ("mfdbatl %0,2" : "=r"(dbat[2].batl));
358 1.43 phx __asm volatile ("mfdbatu %0,3" : "=r"(dbat[3].batu));
359 1.43 phx __asm volatile ("mfdbatl %0,3" : "=r"(dbat[3].batl));
360 1.43 phx }
361 1.43 phx
362 1.43 phx for (i = 0; i < 4; i++) {
363 1.43 phx #ifdef PPC_OEA601
364 1.43 phx if (cpuvers == MPC601) {
365 1.43 phx db_printf("bat%d:", i);
366 1.43 phx print_bat601(&ibat[i]);
367 1.43 phx } else
368 1.43 phx #endif
369 1.43 phx {
370 1.43 phx db_printf("ibat%d:", i);
371 1.43 phx print_bat(&ibat[i]);
372 1.43 phx }
373 1.43 phx }
374 1.43 phx if (cpuvers != MPC601) {
375 1.43 phx for (i = 0; i < 4; i++) {
376 1.43 phx db_printf("dbat%d:", i);
377 1.43 phx print_bat(&dbat[i]);
378 1.43 phx }
379 1.43 phx }
380 1.43 phx }
381 1.43 phx
382 1.43 phx static void
383 1.43 phx db_show_mmu(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
384 1.43 phx {
385 1.43 phx paddr_t sdr1;
386 1.43 phx #if !defined(PPC_OEA64) && !defined(PPC_OEA64_BRIDGE)
387 1.43 phx register_t sr;
388 1.43 phx vaddr_t saddr;
389 1.43 phx int i;
390 1.43 phx #endif
391 1.43 phx
392 1.43 phx __asm volatile ("mfsdr1 %0" : "=r"(sdr1));
393 1.43 phx db_printf("sdr1\t\t0x%08lx\n", sdr1);
394 1.43 phx
395 1.43 phx #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE)
396 1.43 phx __asm volatile ("mfasr %0" : "=r"(sdr1));
397 1.43 phx db_printf("asr\t\t0x%08lx\n", sdr1);
398 1.43 phx #else
399 1.43 phx saddr = 0;
400 1.43 phx for (i = 0; i<= 0xf; i++) {
401 1.43 phx if ((i & 3) == 0)
402 1.43 phx db_printf("sr%d-%d\t\t", i, i+3);
403 1.43 phx __asm volatile ("mfsrin %0,%1" : "=r"(sr) : "r"(saddr));
404 1.43 phx db_printf("0x%08lx %c", sr, (i&3) == 3 ? '\n' : ' ');
405 1.43 phx saddr += 1 << ADDR_SR_SHFT;
406 1.43 phx }
407 1.43 phx #endif
408 1.43 phx }
409 1.43 phx #endif /* PPC_OEA || PPC_OEA64 || PPC_OEA64_BRIDGE */
410 1.43 phx
411 1.45 matt #if defined(PPC_IBM4XX) || defined(PPC_BOOKE)
412 1.24 scw db_addr_t
413 1.24 scw branch_taken(int inst, db_addr_t pc, db_regs_t *regs)
414 1.24 scw {
415 1.24 scw
416 1.24 scw if ((inst & M_B ) == I_B || (inst & M_B ) == I_BL) {
417 1.24 scw db_expr_t off;
418 1.24 scw off = ((db_expr_t)((inst & 0x03fffffc) << 6)) >> 6;
419 1.24 scw return (((inst & 0x2) ? 0 : pc) + off);
420 1.24 scw }
421 1.24 scw
422 1.24 scw if ((inst & M_BC) == I_BC || (inst & M_BC) == I_BCL) {
423 1.24 scw db_expr_t off;
424 1.24 scw off = ((db_expr_t)((inst & 0x0000fffc) << 16)) >> 16;
425 1.24 scw return (((inst & 0x2) ? 0 : pc) + off);
426 1.24 scw }
427 1.24 scw
428 1.24 scw if ((inst & M_RTS) == I_RTS || (inst & M_RTS) == I_BLRL)
429 1.24 scw return (regs->lr);
430 1.24 scw
431 1.24 scw if ((inst & M_BCTR) == I_BCTR || (inst & M_BCTR) == I_BCTRL)
432 1.24 scw return (regs->ctr);
433 1.24 scw
434 1.24 scw db_printf("branch_taken: can't figure out branch target for 0x%x!\n",
435 1.24 scw inst);
436 1.24 scw return (0);
437 1.24 scw }
438 1.45 matt #endif /* PPC_IBM4XX || PPC_BOOKE */
439 1.24 scw
440 1.43 phx
441 1.45 matt #ifdef PPC_IBM4XX
442 1.42 phx #ifdef DDB
443 1.10 simonb static void
444 1.37 matt db_ppc4xx_ctx(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
445 1.10 simonb {
446 1.10 simonb struct proc *p;
447 1.10 simonb
448 1.10 simonb /* XXX LOCKING XXX */
449 1.10 simonb for (p = allproc.lh_first; p != 0; p = p->p_list.le_next) {
450 1.10 simonb if (p->p_stat) {
451 1.10 simonb db_printf("process %p:", p);
452 1.10 simonb db_printf("pid:%d pmap:%p ctx:%d %s\n",
453 1.10 simonb p->p_pid, p->p_vmspace->vm_map.pmap,
454 1.10 simonb p->p_vmspace->vm_map.pmap->pm_ctx,
455 1.10 simonb p->p_comm);
456 1.10 simonb }
457 1.10 simonb }
458 1.10 simonb return;
459 1.10 simonb }
460 1.10 simonb
461 1.10 simonb static void
462 1.37 matt db_ppc4xx_pv(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
463 1.10 simonb {
464 1.10 simonb struct pv_entry {
465 1.10 simonb struct pv_entry *pv_next; /* Linked list of mappings */
466 1.10 simonb vaddr_t pv_va; /* virtual address of mapping */
467 1.10 simonb struct pmap *pv_pm;
468 1.10 simonb };
469 1.10 simonb struct pv_entry *pa_to_pv(paddr_t);
470 1.10 simonb struct pv_entry *pv;
471 1.10 simonb
472 1.10 simonb if (!have_addr) {
473 1.10 simonb db_printf("pv: <pa>\n");
474 1.10 simonb return;
475 1.10 simonb }
476 1.10 simonb pv = pa_to_pv(addr);
477 1.10 simonb db_printf("pv at %p\n", pv);
478 1.10 simonb while (pv && pv->pv_pm) {
479 1.10 simonb db_printf("next %p va %p pmap %p\n", pv->pv_next,
480 1.10 simonb (void *)pv->pv_va, pv->pv_pm);
481 1.10 simonb pv = pv->pv_next;
482 1.10 simonb }
483 1.10 simonb }
484 1.10 simonb
485 1.10 simonb static void
486 1.37 matt db_ppc4xx_reset(db_expr_t addr, bool have_addr, db_expr_t count,
487 1.34 scw const char *modif)
488 1.10 simonb {
489 1.10 simonb printf("Reseting...\n");
490 1.10 simonb ppc4xx_reset();
491 1.10 simonb }
492 1.10 simonb
493 1.10 simonb static void
494 1.37 matt db_ppc4xx_tf(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
495 1.10 simonb {
496 1.45 matt struct trapframe *tf;
497 1.10 simonb
498 1.10 simonb
499 1.10 simonb if (have_addr) {
500 1.45 matt tf = (struct trapframe *)addr;
501 1.10 simonb
502 1.27 matt db_printf("r0-r3: \t%8.8lx %8.8lx %8.8lx %8.8lx\n",
503 1.45 matt tf->tf_fixreg[0], tf->tf_fixreg[1],
504 1.45 matt tf->tf_fixreg[2], tf->tf_fixreg[3]);
505 1.27 matt db_printf("r4-r7: \t%8.8lx %8.8lx %8.8lx %8.8lx\n",
506 1.45 matt tf->tf_fixreg[4], tf->tf_fixreg[5],
507 1.45 matt tf->tf_fixreg[6], tf->tf_fixreg[7]);
508 1.27 matt db_printf("r8-r11: \t%8.8lx %8.8lx %8.8lx %8.8lx\n",
509 1.45 matt tf->tf_fixreg[8], tf->tf_fixreg[9],
510 1.45 matt tf->tf_fixreg[10], tf->tf_fixreg[11]);
511 1.27 matt db_printf("r12-r15:\t%8.8lx %8.8lx %8.8lx %8.8lx\n",
512 1.45 matt tf->tf_fixreg[12], tf->tf_fixreg[13],
513 1.45 matt tf->tf_fixreg[14], tf->tf_fixreg[15]);
514 1.27 matt db_printf("r16-r19:\t%8.8lx %8.8lx %8.8lx %8.8lx\n",
515 1.45 matt tf->tf_fixreg[16], tf->tf_fixreg[17],
516 1.45 matt tf->tf_fixreg[18], tf->tf_fixreg[19]);
517 1.27 matt db_printf("r20-r23:\t%8.8lx %8.8lx %8.8lx %8.8lx\n",
518 1.45 matt tf->tf_fixreg[20], tf->tf_fixreg[21],
519 1.45 matt tf->tf_fixreg[22], tf->tf_fixreg[23]);
520 1.27 matt db_printf("r24-r27:\t%8.8lx %8.8lx %8.8lx %8.8lx\n",
521 1.45 matt tf->tf_fixreg[24], tf->tf_fixreg[25],
522 1.45 matt tf->tf_fixreg[26], tf->tf_fixreg[27]);
523 1.27 matt db_printf("r28-r31:\t%8.8lx %8.8lx %8.8lx %8.8lx\n",
524 1.45 matt tf->tf_fixreg[28], tf->tf_fixreg[29],
525 1.45 matt tf->tf_fixreg[30], tf->tf_fixreg[31]);
526 1.10 simonb
527 1.27 matt db_printf("lr: %8.8lx cr: %8.8x xer: %8.8x ctr: %8.8lx\n",
528 1.45 matt tf->tf_lr, tf->tf_cr, tf->tf_xer, tf->tf_ctr);
529 1.27 matt db_printf("srr0(pc): %8.8lx srr1(msr): %8.8lx "
530 1.27 matt "dear: %8.8lx esr: %8.8x\n",
531 1.45 matt tf->tf_srr0, tf->tf_srr1, tf->tf_dear, tf->tf_esr);
532 1.10 simonb db_printf("exc: %8.8x pid: %8.8x\n",
533 1.45 matt tf->tf_exc, tf->tf_pid);
534 1.10 simonb }
535 1.10 simonb return;
536 1.10 simonb }
537 1.10 simonb
538 1.10 simonb static const char *const tlbsizes[] = {
539 1.10 simonb "1kB",
540 1.10 simonb "4kB",
541 1.10 simonb "16kB",
542 1.10 simonb "64kB",
543 1.10 simonb "256kB",
544 1.10 simonb "1MB",
545 1.10 simonb "4MB",
546 1.10 simonb "16MB"
547 1.10 simonb };
548 1.10 simonb
549 1.10 simonb static void
550 1.37 matt db_ppc4xx_dumptlb(db_expr_t addr, bool have_addr, db_expr_t count,
551 1.34 scw const char *modif)
552 1.10 simonb {
553 1.10 simonb int i, zone, tlbsize;
554 1.10 simonb u_int zpr, pid, opid, msr;
555 1.10 simonb u_long tlblo, tlbhi, tlbmask;
556 1.10 simonb
557 1.10 simonb zpr = mfspr(SPR_ZPR);
558 1.10 simonb for (i = 0; i < NTLB; i++) {
559 1.36 perry __asm volatile("mfmsr %3;"
560 1.10 simonb "mfpid %4;"
561 1.10 simonb "li %0,0;"
562 1.10 simonb "mtmsr %0;"
563 1.10 simonb "sync; isync;"
564 1.21 thorpej "tlbrelo %0,%5;"
565 1.21 thorpej "tlbrehi %1,%5;"
566 1.10 simonb "mfpid %2;"
567 1.10 simonb "mtpid %4;"
568 1.10 simonb "mtmsr %3;"
569 1.10 simonb "sync; isync"
570 1.10 simonb : "=&r" (tlblo), "=&r" (tlbhi), "=r" (pid),
571 1.10 simonb "=&r" (msr), "=&r" (opid) : "r" (i));
572 1.10 simonb
573 1.10 simonb if (strchr(modif, 'v') && !(tlbhi & TLB_VALID))
574 1.10 simonb continue;
575 1.10 simonb
576 1.10 simonb tlbsize = (tlbhi & TLB_SIZE_MASK) >> TLB_SIZE_SHFT;
577 1.10 simonb /* map tlbsize 0 .. 7 to masks for 1kB .. 16MB */
578 1.10 simonb tlbmask = ~(1 << (tlbsize * 2 + 10)) + 1;
579 1.10 simonb
580 1.10 simonb if (have_addr && ((tlbhi & tlbmask) != (addr & tlbmask)))
581 1.10 simonb continue;
582 1.10 simonb
583 1.10 simonb zone = (tlblo & TLB_ZSEL_MASK) >> TLB_ZSEL_SHFT;
584 1.10 simonb db_printf("tlb%c%2d", tlbhi & TLB_VALID ? ' ' : '*', i);
585 1.10 simonb db_printf(" PID %3d EPN 0x%08lx %-5s",
586 1.10 simonb pid,
587 1.10 simonb tlbhi & tlbmask,
588 1.10 simonb tlbsizes[tlbsize]);
589 1.10 simonb db_printf(" RPN 0x%08lx ZONE %2d%c %s %s %c%c%c%c%c %s",
590 1.10 simonb tlblo & tlbmask,
591 1.10 simonb zone,
592 1.10 simonb "NTTA"[(zpr >> ((15 - zone) * 2)) & 3],
593 1.10 simonb tlblo & TLB_EX ? "EX" : " ",
594 1.10 simonb tlblo & TLB_WR ? "WR" : " ",
595 1.10 simonb tlblo & TLB_W ? 'W' : ' ',
596 1.10 simonb tlblo & TLB_I ? 'I' : ' ',
597 1.10 simonb tlblo & TLB_M ? 'M' : ' ',
598 1.10 simonb tlblo & TLB_G ? 'G' : ' ',
599 1.10 simonb tlbhi & TLB_ENDIAN ? 'E' : ' ',
600 1.10 simonb tlbhi & TLB_U0 ? "U0" : " ");
601 1.10 simonb db_printf("\n");
602 1.10 simonb }
603 1.22 scw }
604 1.22 scw
605 1.22 scw static void
606 1.37 matt db_ppc4xx_dcr(db_expr_t address, bool have_addr, db_expr_t count,
607 1.34 scw const char *modif)
608 1.22 scw {
609 1.22 scw db_expr_t new_value;
610 1.22 scw db_expr_t addr;
611 1.23 scw
612 1.23 scw if (address < 0 || address > 0x3ff)
613 1.23 scw db_error("Invalid DCR address (Valid range is 0x0 - 0x3ff)\n");
614 1.22 scw
615 1.22 scw addr = address;
616 1.22 scw
617 1.22 scw while (db_expression(&new_value)) {
618 1.22 scw db_printf("dcr 0x%lx\t\t%s = ", addr,
619 1.22 scw db_num_to_str(db_ppc4xx_mfdcr(addr)));
620 1.22 scw db_ppc4xx_mtdcr(addr, new_value);
621 1.22 scw db_printf("%s\n", db_num_to_str(db_ppc4xx_mfdcr(addr)));
622 1.22 scw addr += 1;
623 1.22 scw }
624 1.22 scw
625 1.22 scw if (addr == address) {
626 1.22 scw db_next = (db_addr_t)addr + 1;
627 1.22 scw db_prev = (db_addr_t)addr;
628 1.22 scw db_printf("dcr 0x%lx\t\t%s\n", addr,
629 1.22 scw db_num_to_str(db_ppc4xx_mfdcr(addr)));
630 1.22 scw } else {
631 1.22 scw db_next = (db_addr_t)addr;
632 1.22 scw db_prev = (db_addr_t)addr - 1;
633 1.22 scw }
634 1.22 scw
635 1.22 scw db_skip_to_eol();
636 1.22 scw }
637 1.22 scw
638 1.22 scw /*
639 1.22 scw * XXX Grossness Alert! XXX
640 1.22 scw *
641 1.22 scw * Please look away now if you don't like self-modifying code
642 1.22 scw */
643 1.22 scw static u_int32_t db_ppc4xx_dcrfunc[4];
644 1.22 scw
645 1.22 scw static db_expr_t
646 1.22 scw db_ppc4xx_mfdcr(db_expr_t reg)
647 1.22 scw {
648 1.22 scw db_expr_t (*func)(void);
649 1.22 scw
650 1.22 scw reg = (((reg & 0x1f) << 5) | ((reg >> 5) & 0x1f)) << 11;
651 1.22 scw db_ppc4xx_dcrfunc[0] = 0x7c0004ac; /* sync */
652 1.22 scw db_ppc4xx_dcrfunc[1] = 0x4c00012c; /* isync */
653 1.22 scw db_ppc4xx_dcrfunc[2] = 0x7c600286 | reg; /* mfdcr reg, r3 */
654 1.22 scw db_ppc4xx_dcrfunc[3] = 0x4e800020; /* blr */
655 1.22 scw
656 1.22 scw __syncicache((void *)db_ppc4xx_dcrfunc, sizeof(db_ppc4xx_dcrfunc));
657 1.22 scw func = (db_expr_t (*)(void))(void *)db_ppc4xx_dcrfunc;
658 1.22 scw
659 1.22 scw return ((*func)());
660 1.22 scw }
661 1.22 scw
662 1.22 scw static void
663 1.22 scw db_ppc4xx_mtdcr(db_expr_t reg, db_expr_t val)
664 1.22 scw {
665 1.22 scw db_expr_t (*func)(db_expr_t);
666 1.22 scw
667 1.22 scw reg = (((reg & 0x1f) << 5) | ((reg >> 5) & 0x1f)) << 11;
668 1.22 scw db_ppc4xx_dcrfunc[0] = 0x7c0004ac; /* sync */
669 1.22 scw db_ppc4xx_dcrfunc[1] = 0x4c00012c; /* isync */
670 1.22 scw db_ppc4xx_dcrfunc[2] = 0x7c600386 | reg; /* mtdcr r3, reg */
671 1.22 scw db_ppc4xx_dcrfunc[3] = 0x4e800020; /* blr */
672 1.22 scw
673 1.22 scw __syncicache((void *)db_ppc4xx_dcrfunc, sizeof(db_ppc4xx_dcrfunc));
674 1.22 scw func = (db_expr_t (*)(db_expr_t))(void *)db_ppc4xx_dcrfunc;
675 1.22 scw
676 1.22 scw (*func)(val);
677 1.10 simonb }
678 1.10 simonb
679 1.10 simonb #ifdef USERACC
680 1.10 simonb static void
681 1.37 matt db_ppc4xx_useracc(db_expr_t addr, bool have_addr, db_expr_t count,
682 1.34 scw const char *modif)
683 1.10 simonb {
684 1.10 simonb static paddr_t oldaddr = -1;
685 1.10 simonb int instr = 0;
686 1.10 simonb int data;
687 1.10 simonb extern vaddr_t opc_disasm(vaddr_t loc, int);
688 1.10 simonb
689 1.10 simonb
690 1.10 simonb if (!have_addr) {
691 1.10 simonb addr = oldaddr;
692 1.10 simonb }
693 1.10 simonb if (addr == -1) {
694 1.10 simonb db_printf("no address\n");
695 1.10 simonb return;
696 1.10 simonb }
697 1.10 simonb addr &= ~0x3; /* align */
698 1.10 simonb {
699 1.34 scw const char *cp = modif;
700 1.34 scw char c;
701 1.10 simonb while ((c = *cp++) != 0)
702 1.10 simonb if (c == 'i')
703 1.10 simonb instr = 1;
704 1.10 simonb }
705 1.10 simonb while (count--) {
706 1.10 simonb if (db_print_position() == 0) {
707 1.10 simonb /* Always print the address. */
708 1.10 simonb db_printf("%8.4lx:\t", addr);
709 1.10 simonb }
710 1.10 simonb oldaddr=addr;
711 1.10 simonb copyin((void *)addr, &data, sizeof(data));
712 1.10 simonb if (instr) {
713 1.10 simonb opc_disasm(addr, data);
714 1.10 simonb } else {
715 1.10 simonb db_printf("%4.4x\n", data);
716 1.10 simonb }
717 1.10 simonb addr += 4;
718 1.10 simonb db_end_line();
719 1.10 simonb }
720 1.10 simonb
721 1.10 simonb }
722 1.10 simonb #endif
723 1.10 simonb
724 1.39 garbled #endif /* DDB */
725 1.39 garbled
726 1.10 simonb #endif /* PPC_IBM4XX */
727 1.45 matt
728 1.45 matt #ifdef PPC_BOOKE
729 1.45 matt static void
730 1.45 matt db_ppcbooke_reset(db_expr_t addr, bool have_addr, db_expr_t count,
731 1.45 matt const char *modif)
732 1.45 matt {
733 1.45 matt printf("Reseting...\n");
734 1.45 matt (*cpu_md_ops.md_cpu_reset)();
735 1.45 matt }
736 1.45 matt
737 1.45 matt static void
738 1.45 matt db_ppcbooke_tf(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
739 1.45 matt {
740 1.45 matt if (!have_addr)
741 1.45 matt return;
742 1.45 matt
743 1.45 matt const struct trapframe * const tf = (const struct trapframe *)addr;
744 1.45 matt
745 1.45 matt db_printf("trapframe %p (exc=%x srr0/1=%#lx/%#lx esr/dear=%#x/%#lx)\n",
746 1.45 matt tf, tf->tf_exc, tf->tf_srr0, tf->tf_srr1, tf->tf_esr, tf->tf_dear);
747 1.45 matt db_printf("lr =%08lx ctr=%08lx cr =%08x xer=%08x\n",
748 1.45 matt tf->tf_lr, tf->tf_ctr, tf->tf_cr, tf->tf_xer);
749 1.45 matt for (u_int r = 0; r < 32; r += 4) {
750 1.45 matt db_printf("r%02u=%08lx r%02u=%08lx r%02u=%08lx r%02u=%08lx\n",
751 1.45 matt r+0, tf->tf_fixreg[r+0], r+1, tf->tf_fixreg[r+1],
752 1.45 matt r+2, tf->tf_fixreg[r+2], r+3, tf->tf_fixreg[r+3]);
753 1.45 matt }
754 1.45 matt }
755 1.45 matt
756 1.45 matt static void
757 1.45 matt db_ppcbooke_dumptlb(db_expr_t addr, bool have_addr, db_expr_t count,
758 1.45 matt const char *modif)
759 1.45 matt {
760 1.45 matt tlb_dump(db_printf);
761 1.45 matt }
762 1.45 matt #endif /* PPC_BOOKE */
763