bus.h revision 1.3
1/* $NetBSD: bus.h,v 1.3 2000/06/26 04:55:57 simonb Exp $ */ 2/* $OpenBSD: bus.h,v 1.1 1997/10/13 10:53:42 pefo Exp $ */ 3 4/*- 5 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41/* 42 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 43 * Copyright (c) 1996 Jason R. Thorpe. All rights reserved. 44 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by Christopher G. Demetriou 57 * for the NetBSD Project. 58 * 4. The name of the author may not be used to endorse or promote products 59 * derived from this software without specific prior written permission 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 62 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 63 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 64 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 65 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 66 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 67 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 68 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 69 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 70 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 71 */ 72 73/* 74 * Copyright (c) 1997 Per Fogelstrom. All rights reserved. 75 * Copyright (c) 1996 Niklas Hallqvist. All rights reserved. 76 * 77 * Redistribution and use in source and binary forms, with or without 78 * modification, are permitted provided that the following conditions 79 * are met: 80 * 1. Redistributions of source code must retain the above copyright 81 * notice, this list of conditions and the following disclaimer. 82 * 2. Redistributions in binary form must reproduce the above copyright 83 * notice, this list of conditions and the following disclaimer in the 84 * documentation and/or other materials provided with the distribution. 85 * 3. All advertising materials mentioning features or use of this software 86 * must display the following acknowledgement: 87 * This product includes software developed by Christopher G. Demetriou 88 * for the NetBSD Project. 89 * 4. The name of the author may not be used to endorse or promote products 90 * derived from this software without specific prior written permission 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 93 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 94 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 95 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 96 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 97 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 98 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 99 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 100 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 101 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 102 */ 103 104#ifndef _PREP_BUS_H_ 105#define _PREP_BUS_H_ 106 107#include <machine/pio.h> 108 109/* 110 * Values for the Be bus space tag, not to be used directly by MI code. 111 */ 112#define PREP_BUS_SPACE_IO 0x80000000 /* i/o space */ 113#define PREP_BUS_SPACE_MEM 0xC0000000 /* mem space */ 114 115/* 116 * Address conversion as seen from a PCI master. 117 */ 118#define MPC105_DIRECT_MAPPED_SPACE 0x80000000 119#define PHYS_TO_PCI_MEM(x) ((x) | MPC105_DIRECT_MAPPED_SPACE) 120#define PCI_MEM_TO_PHYS(x) ((x) & ~MPC105_DIRECT_MAPPED_SPACE) 121 122/* 123 * Bus access types. 124 */ 125typedef u_int32_t bus_addr_t; 126typedef u_int32_t bus_size_t; 127typedef u_int32_t bus_space_handle_t; 128typedef u_int32_t bus_space_tag_t; 129 130#define BUS_SPACE_MAP_CACHEABLE 0x01 131#define BUS_SPACE_MAP_LINEAR 0x02 132#define BUS_SPACE_MAP_PREFETCHABLE 0x04 133 134#ifdef __STDC__ 135#define CAT(a,b) a##b 136#define CAT3(a,b,c) a##b##c 137#else 138#define CAT(a,b) a/**/b 139#define CAT3(a,b,c) a/**/b/**/c 140#endif 141 142/* 143 * Access methods for bus resources 144 */ 145 146#define __BUS_SPACE_HAS_STREAM_METHODS 147 148/* 149 * int bus_space_map __P((bus_space_tag_t t, bus_addr_t addr, 150 * bus_size_t size, int flags, bus_space_handle_t *bshp)); 151 * 152 * Map a region of bus space. 153 */ 154 155int prep_memio_map __P((bus_space_tag_t t, bus_addr_t addr, 156 bus_size_t size, int flags, bus_space_handle_t *bshp)); 157 158#define bus_space_map(t, a, s, f, hp) \ 159 prep_memio_map((t), (a), (s), (f), (hp)) 160 161/* 162 * int bus_space_unmap __P((bus_space_tag_t t, 163 * bus_space_handle_t bsh, bus_size_t size)); 164 * 165 * Unmap a region of bus space. 166 */ 167 168void prep_memio_unmap __P((bus_space_tag_t t, bus_space_handle_t bsh, 169 bus_size_t size)); 170 171#define bus_space_unmap(t, h, s) \ 172 prep_memio_unmap((t), (h), (s)) 173 174/* 175 * int bus_space_subregion __P((bus_space_tag_t t, 176 * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, 177 * bus_space_handle_t *nbshp)); 178 * 179 * Get a new handle for a subregion of an already-mapped area of bus space. 180 */ 181 182#define bus_space_subregion(t, h, o, s, hp) \ 183 ((*(hp) = (h) + (o)), 0) 184 185/* 186 * int bus_space_alloc __P((bus_space_tag_t t, bus_addr_t rstart, 187 * bus_addr_t rend, bus_size_t size, bus_size_t align, 188 * bus_size_t boundary, int flags, bus_addr_t *bpap, 189 * bus_space_handle_t *bshp)); 190 * 191 * Allocate a region of bus space. 192 */ 193 194int prep_memio_alloc __P((bus_space_tag_t t, bus_addr_t rstart, 195 bus_addr_t rend, bus_size_t size, bus_size_t align, 196 bus_size_t boundary, int flags, bus_addr_t *bpap, 197 bus_space_handle_t *bshp)); 198 199#define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \ 200 prep_memio_alloc((t), (rs), (re), (s), (a), (b), (f), (ap), (hp)) 201 202/* 203 * int bus_space_free __P((bus_space_tag_t t, 204 * bus_space_handle_t bsh, bus_size_t size)); 205 * 206 * Free a region of bus space. 207 */ 208 209void prep_memio_free __P((bus_space_tag_t t, bus_space_handle_t bsh, 210 bus_size_t size)); 211 212#define bus_space_free(t, h, s) \ 213 prep_memio_free((t), (h), (s)) 214 215/* 216 * u_intN_t bus_space_read_N __P((bus_space_tag_t tag, 217 * bus_space_handle_t bsh, bus_size_t offset)); 218 * 219 * Read a 1, 2, 4, or 8 byte quantity from bus space 220 * described by tag/handle/offset. 221 */ 222 223#define bus_space_read(n,m) \ 224static __inline CAT3(u_int,m,_t) \ 225CAT(bus_space_read_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \ 226 bus_size_t offset) \ 227{ \ 228 return CAT3(in,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (offset))); \ 229} 230 231bus_space_read(1,8) 232bus_space_read(2,16) 233bus_space_read(4,32) 234#define bus_space_read_8 !!! bus_space_read_8 unimplemented !!! 235 236/* 237 * u_intN_t bus_space_read_stream_N __P((bus_space_tag_t tag, 238 * bus_space_handle_t bsh, bus_size_t offset)); 239 * 240 * Read a 2, 4, or 8 byte stream quantity from bus space 241 * described by tag/handle/offset. 242 */ 243 244#define bus_space_read_stream(n,m) \ 245static __inline CAT3(u_int,m,_t) \ 246CAT(bus_space_read_stream_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \ 247 bus_size_t offset) \ 248{ \ 249 return CAT(in,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset))); \ 250} 251 252bus_space_read_stream(2,16) 253bus_space_read_stream(4,32) 254#define bus_space_read_stream_8 !!! bus_space_read_stream_8 unimplemented !!! 255 256/* 257 * void bus_space_read_multi_N __P((bus_space_tag_t tag, 258 * bus_space_handle_t bsh, bus_size_t offset, 259 * u_intN_t *addr, size_t count)); 260 * 261 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 262 * described by tag/handle/offset and copy into buffer provided. 263 */ 264 265#define bus_space_read_multi(n,m) \ 266static __inline void \ 267CAT(bus_space_read_multi_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \ 268 bus_size_t offset, CAT3(u_int,m,_t) *addr, size_t count) \ 269{ \ 270 CAT3(ins,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), \ 271 (CAT3(u_int,m,_t) *)addr, (size_t)count); \ 272} 273 274bus_space_read_multi(1,8) 275bus_space_read_multi(2,16) 276bus_space_read_multi(4,32) 277#define bus_space_read_multi_8 !!! bus_space_read_multi_8 not implemented !!! 278 279/* 280 * void bus_space_read_multi_stream_N __P((bus_space_tag_t tag, 281 * bus_space_handle_t bsh, bus_size_t offset, 282 * u_intN_t *addr, size_t count)); 283 * 284 * Read `count' 2, 4, or 8 byte stream quantities from bus space 285 * described by tag/handle/offset and copy into buffer provided. 286 */ 287 288#define bus_space_read_multi_stream(n,m) \ 289static __inline void \ 290CAT(bus_space_read_multi_stream_,n)(bus_space_tag_t tag, \ 291 bus_space_handle_t bsh, \ 292 bus_size_t offset, CAT3(u_int,m,_t) *addr, size_t count) \ 293{ \ 294 CAT(ins,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), \ 295 (CAT3(u_int,m,_t) *)addr, (size_t)count); \ 296} 297 298bus_space_read_multi_stream(2,16) 299bus_space_read_multi_stream(4,32) 300#define bus_space_read_multi_stream_8 \ 301 !!! bus_space_read_multi_stream_8 not implemented !!! 302 303/* 304 * void bus_space_write_N __P((bus_space_tag_t tag, 305 * bus_space_handle_t bsh, bus_size_t offset, 306 * u_intN_t value)); 307 * 308 * Write the 1, 2, 4, or 8 byte value `value' to bus space 309 * described by tag/handle/offset. 310 */ 311 312#define bus_space_write(n,m) \ 313static __inline void \ 314CAT(bus_space_write_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \ 315 bus_size_t offset, CAT3(u_int,m,_t) x) \ 316{ \ 317 CAT3(out,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), x); \ 318} 319 320bus_space_write(1,8) 321bus_space_write(2,16) 322bus_space_write(4,32) 323#define bus_space_write_8 !!! bus_space_write_8 unimplemented !!! 324 325/* 326 * void bus_space_write_stream_N __P((bus_space_tag_t tag, 327 * bus_space_handle_t bsh, bus_size_t offset, 328 * u_intN_t value)); 329 * 330 * Write the 2, 4, or 8 byte stream value `value' to bus space 331 * described by tag/handle/offset. 332 */ 333 334#define bus_space_write_stream(n,m) \ 335static __inline void \ 336CAT(bus_space_write_stream_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \ 337 bus_size_t offset, CAT3(u_int,m,_t) x) \ 338{ \ 339 CAT(out,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), x); \ 340} 341 342bus_space_write_stream(2,16) 343bus_space_write_stream(4,32) 344#define bus_space_write_stream_8 !!! bus_space_write_stream_8 unimplemented !!! 345 346/* 347 * void bus_space_write_multi_N __P((bus_space_tag_t tag, 348 * bus_space_handle_t bsh, bus_size_t offset, 349 * const u_intN_t *addr, size_t count)); 350 * 351 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer 352 * provided to bus space described by tag/handle/offset. 353 */ 354 355#define bus_space_write_multi(n,m) \ 356static __inline void \ 357CAT(bus_space_write_multi_,n)(bus_space_tag_t tag, bus_space_handle_t bsh, \ 358 bus_size_t offset, const CAT3(u_int,m,_t) *addr, size_t count) \ 359{ \ 360 CAT3(outs,m,rb)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), \ 361 (CAT3(u_int,m,_t) *)addr, (size_t)count); \ 362} 363 364bus_space_write_multi(1,8) 365bus_space_write_multi(2,16) 366bus_space_write_multi(4,32) 367#define bus_space_write_multi_8 !!! bus_space_write_multi_8 not implemented !!! 368 369/* 370 * void bus_space_write_multi_stream_N __P((bus_space_tag_t tag, 371 * bus_space_handle_t bsh, bus_size_t offset, 372 * const u_intN_t *addr, size_t count)); 373 * 374 * Write `count' 2, 4, or 8 byte stream quantities from the buffer 375 * provided to bus space described by tag/handle/offset. 376 */ 377 378#define bus_space_write_multi_stream(n,m) \ 379static __inline void \ 380CAT(bus_space_write_multi_stream_,n)(bus_space_tag_t tag, \ 381 bus_space_handle_t bsh, \ 382 bus_size_t offset, const CAT3(u_int,m,_t) *addr, size_t count) \ 383{ \ 384 CAT(outs,m)((volatile CAT3(u_int,m,_t) *)(bsh + (offset)), \ 385 (CAT3(u_int,m,_t) *)addr, (size_t)count); \ 386} 387 388bus_space_write_multi_stream(2,16) 389bus_space_write_multi_stream(4,32) 390#define bus_space_write_multi_stream_8 \ 391 !!! bus_space_write_multi_stream_8 not implemented !!! 392 393/* 394 * void bus_space_read_region_N __P((bus_space_tag_t tag, 395 * bus_space_handle_t bsh, bus_size_t offset, 396 * u_intN_t *addr, size_t count)); 397 * 398 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 399 * described by tag/handle and starting at `offset' and copy into 400 * buffer provided. 401 */ 402static __inline void bus_space_read_region_1 __P((bus_space_tag_t, 403 bus_space_handle_t, bus_size_t, u_int8_t *, size_t)); 404static __inline void bus_space_read_region_2 __P((bus_space_tag_t, 405 bus_space_handle_t, bus_size_t, u_int16_t *, size_t)); 406static __inline void bus_space_read_region_4 __P((bus_space_tag_t, 407 bus_space_handle_t, bus_size_t, u_int32_t *, size_t)); 408 409static __inline void 410bus_space_read_region_1(tag, bsh, offset, addr, count) 411 bus_space_tag_t tag; 412 bus_space_handle_t bsh; 413 bus_size_t offset; 414 u_int8_t *addr; 415 size_t count; 416{ 417 volatile u_int8_t *s; 418 419 s = (volatile u_int8_t *)(bsh + offset); 420 while (count--) 421 *addr++ = *s++; 422 __asm__ volatile("eieio; sync"); 423} 424 425static __inline void 426bus_space_read_region_2(tag, bsh, offset, addr, count) 427 bus_space_tag_t tag; 428 bus_space_handle_t bsh; 429 bus_size_t offset; 430 u_int16_t *addr; 431 size_t count; 432{ 433 volatile u_int16_t *s; 434 435 s = (volatile u_int16_t *)(bsh + offset); 436 while (count--) 437 __asm__ volatile("lhbrx %0, 0, %1" : 438 "=r"(*addr++) : "r"(s++)); 439 __asm__ volatile("eieio; sync"); 440} 441 442static __inline void 443bus_space_read_region_4(tag, bsh, offset, addr, count) 444 bus_space_tag_t tag; 445 bus_space_handle_t bsh; 446 bus_size_t offset; 447 u_int32_t *addr; 448 size_t count; 449{ 450 volatile u_int32_t *s; 451 452 s = (volatile u_int32_t *)(bsh + offset); 453 while (count--) 454 __asm__ volatile("lwbrx %0, 0, %1" : 455 "=r"(*addr++) : "r"(s++)); 456 __asm__ volatile("eieio; sync"); 457} 458 459#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!! 460 461/* 462 * void bus_space_read_region_stream_N __P((bus_space_tag_t tag, 463 * bus_space_handle_t bsh, bus_size_t offset, 464 * u_intN_t *addr, size_t count)); 465 * 466 * Read `count' 2, 4, or 8 byte stream quantities from bus space 467 * described by tag/handle and starting at `offset' and copy into 468 * buffer provided. 469 */ 470static __inline void bus_space_read_region_stream_2 __P((bus_space_tag_t, 471 bus_space_handle_t, bus_size_t, u_int16_t *, size_t)); 472static __inline void bus_space_read_region_stream_4 __P((bus_space_tag_t, 473 bus_space_handle_t, bus_size_t, u_int32_t *, size_t)); 474 475static __inline void 476bus_space_read_region_stream_2(tag, bsh, offset, addr, count) 477 bus_space_tag_t tag; 478 bus_space_handle_t bsh; 479 bus_size_t offset; 480 u_int16_t *addr; 481 size_t count; 482{ 483 volatile u_int16_t *s; 484 485 s = (volatile u_int16_t *)(bsh + offset); 486 while (count--) 487 *addr++ = *s++; 488 __asm__ volatile("eieio; sync"); 489} 490 491static __inline void 492bus_space_read_region_stream_4(tag, bsh, offset, addr, count) 493 bus_space_tag_t tag; 494 bus_space_handle_t bsh; 495 bus_size_t offset; 496 u_int32_t *addr; 497 size_t count; 498{ 499 volatile u_int32_t *s; 500 501 s = (volatile u_int32_t *)(bsh + offset); 502 while (count--) 503 *addr++ = *s++; 504 __asm__ volatile("eieio; sync"); 505} 506 507#define bus_space_read_region_stream_8 \ 508 !!! bus_space_read_region_stream_8 unimplemented !!! 509 510/* 511 * void bus_space_write_region_N __P((bus_space_tag_t tag, 512 * bus_space_handle_t bsh, bus_size_t offset, 513 * const u_intN_t *addr, size_t count)); 514 * 515 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 516 * to bus space described by tag/handle starting at `offset'. 517 */ 518static __inline void bus_space_write_region_1 __P((bus_space_tag_t, 519 bus_space_handle_t, bus_size_t, const u_int8_t *, size_t)); 520static __inline void bus_space_write_region_2 __P((bus_space_tag_t, 521 bus_space_handle_t, bus_size_t, const u_int16_t *, size_t)); 522static __inline void bus_space_write_region_4 __P((bus_space_tag_t, 523 bus_space_handle_t, bus_size_t, const u_int32_t *, size_t)); 524 525static __inline void 526bus_space_write_region_1(tag, bsh, offset, addr, count) 527 bus_space_tag_t tag; 528 bus_space_handle_t bsh; 529 bus_size_t offset; 530 const u_int8_t *addr; 531 size_t count; 532{ 533 volatile u_int8_t *d; 534 535 d = (volatile u_int8_t *)(bsh + offset); 536 while (count--) 537 *d++ = *addr++; 538 __asm__ volatile("eieio; sync"); 539} 540 541static __inline void 542bus_space_write_region_2(tag, bsh, offset, addr, count) 543 bus_space_tag_t tag; 544 bus_space_handle_t bsh; 545 bus_size_t offset; 546 const u_int16_t *addr; 547 size_t count; 548{ 549 volatile u_int16_t *d; 550 551 d = (volatile u_int16_t *)(bsh + offset); 552 while (count--) 553 __asm__ volatile("sthbrx %0, 0, %1" :: 554 "r"(*addr++), "r"(d++)); 555 __asm__ volatile("eieio; sync"); 556} 557 558static __inline void 559bus_space_write_region_4(tag, bsh, offset, addr, count) 560 bus_space_tag_t tag; 561 bus_space_handle_t bsh; 562 bus_size_t offset; 563 const u_int32_t *addr; 564 size_t count; 565{ 566 volatile u_int32_t *d; 567 568 d = (volatile u_int32_t *)(bsh + offset); 569 while (count--) 570 __asm__ volatile("stwbrx %0, 0, %1" :: 571 "r"(*addr++), "r"(d++)); 572 __asm__ volatile("eieio; sync"); 573} 574 575#define bus_space_write_region_8 !!! bus_space_write_region_8 unimplemented !!! 576 577/* 578 * void bus_space_write_region_stream_N __P((bus_space_tag_t tag, 579 * bus_space_handle_t bsh, bus_size_t offset, 580 * const u_intN_t *addr, size_t count)); 581 * 582 * Write `count' 2, 4, or 8 byte stream quantities from the buffer provided 583 * to bus space described by tag/handle starting at `offset'. 584 */ 585static __inline void bus_space_write_region_stream_2 __P((bus_space_tag_t, 586 bus_space_handle_t, bus_size_t, const u_int16_t *, size_t)); 587static __inline void bus_space_write_region_stream_4 __P((bus_space_tag_t, 588 bus_space_handle_t, bus_size_t, const u_int32_t *, size_t)); 589 590static __inline void 591bus_space_write_region_stream_2(tag, bsh, offset, addr, count) 592 bus_space_tag_t tag; 593 bus_space_handle_t bsh; 594 bus_size_t offset; 595 const u_int16_t *addr; 596 size_t count; 597{ 598 volatile u_int16_t *d; 599 600 d = (volatile u_int16_t *)(bsh + offset); 601 while (count--) 602 *d++ = *addr++; 603 __asm__ volatile("eieio; sync"); 604} 605 606static __inline void 607bus_space_write_region_stream_4(tag, bsh, offset, addr, count) 608 bus_space_tag_t tag; 609 bus_space_handle_t bsh; 610 bus_size_t offset; 611 const u_int32_t *addr; 612 size_t count; 613{ 614 volatile u_int32_t *d; 615 616 d = (volatile u_int32_t *)(bsh + offset); 617 while (count--) 618 *d++ = *addr++; 619 __asm__ volatile("eieio; sync"); 620} 621 622#define bus_space_write_region_stream_8 \ 623 !!! bus_space_write_region_stream_8 unimplemented !!! 624 625/* 626 * void bus_space_set_multi_N __P((bus_space_tag_t tag, 627 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 628 * size_t count)); 629 * 630 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 631 * by tag/handle/offset `count' times. 632 */ 633static __inline void bus_space_set_multi_1 __P((bus_space_tag_t, 634 bus_space_handle_t, bus_size_t, u_int8_t, size_t)); 635static __inline void bus_space_set_multi_2 __P((bus_space_tag_t, 636 bus_space_handle_t, bus_size_t, u_int16_t, size_t)); 637static __inline void bus_space_set_multi_4 __P((bus_space_tag_t, 638 bus_space_handle_t, bus_size_t, u_int32_t, size_t)); 639 640static __inline void 641bus_space_set_multi_1(tag, bsh, offset, val, count) 642 bus_space_tag_t tag; 643 bus_space_handle_t bsh; 644 bus_size_t offset; 645 u_int8_t val; 646 size_t count; 647{ 648 volatile u_int8_t *d; 649 650 d = (volatile u_int8_t *)(bsh + offset); 651 while (count--) 652 *d = val; 653 __asm__ volatile("eieio; sync"); 654} 655 656static __inline void 657bus_space_set_multi_2(tag, bsh, offset, val, count) 658 bus_space_tag_t tag; 659 bus_space_handle_t bsh; 660 bus_size_t offset; 661 u_int16_t val; 662 size_t count; 663{ 664 volatile u_int16_t *d; 665 666 d = (volatile u_int16_t *)(bsh + offset); 667 while (count--) 668 __asm__ volatile("sthbrx %0, 0, %1" :: 669 "r"(val), "r"(d)); 670 __asm__ volatile("eieio; sync"); 671} 672 673static __inline void 674bus_space_set_multi_4(tag, bsh, offset, val, count) 675 bus_space_tag_t tag; 676 bus_space_handle_t bsh; 677 bus_size_t offset; 678 u_int32_t val; 679 size_t count; 680{ 681 volatile u_int32_t *d; 682 683 d = (volatile u_int32_t *)(bsh + offset); 684 while (count--) 685 __asm__ volatile("stwbrx %0, 0, %1" :: 686 "r"(val), "r"(d)); 687 __asm__ volatile("eieio; sync"); 688} 689 690#define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! 691 692/* 693 * void bus_space_set_multi_stream_N __P((bus_space_tag_t tag, 694 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 695 * size_t count)); 696 * 697 * Write the 2, 4, or 8 byte stream value `val' to bus space described 698 * by tag/handle/offset `count' times. 699 */ 700static __inline void bus_space_set_multi_stream_2 __P((bus_space_tag_t, 701 bus_space_handle_t, bus_size_t, u_int16_t, size_t)); 702static __inline void bus_space_set_multi_stream_4 __P((bus_space_tag_t, 703 bus_space_handle_t, bus_size_t, u_int32_t, size_t)); 704 705static __inline void 706bus_space_set_multi_stream_2(tag, bsh, offset, val, count) 707 bus_space_tag_t tag; 708 bus_space_handle_t bsh; 709 bus_size_t offset; 710 u_int16_t val; 711 size_t count; 712{ 713 volatile u_int16_t *d; 714 715 d = (volatile u_int16_t *)(bsh + offset); 716 while (count--) 717 *d = val; 718 __asm__ volatile("eieio; sync"); 719} 720 721static __inline void 722bus_space_set_multi_stream_4(tag, bsh, offset, val, count) 723 bus_space_tag_t tag; 724 bus_space_handle_t bsh; 725 bus_size_t offset; 726 u_int32_t val; 727 size_t count; 728{ 729 volatile u_int32_t *d; 730 731 d = (volatile u_int32_t *)(bsh + offset); 732 while (count--) 733 *d = val; 734 __asm__ volatile("eieio; sync"); 735} 736 737#define bus_space_set_multi_stream_8 \ 738 !!! bus_space_set_multi_stream_8 unimplemented !!! 739 740/* 741 * void bus_space_set_region_N __P((bus_space_tag_t tag, 742 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 743 * size_t count)); 744 * 745 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described 746 * by tag/handle starting at `offset'. 747 */ 748static __inline void bus_space_set_region_1 __P((bus_space_tag_t, 749 bus_space_handle_t, bus_size_t, u_int8_t, size_t)); 750static __inline void bus_space_set_region_2 __P((bus_space_tag_t, 751 bus_space_handle_t, bus_size_t, u_int16_t, size_t)); 752static __inline void bus_space_set_region_4 __P((bus_space_tag_t, 753 bus_space_handle_t, bus_size_t, u_int32_t, size_t)); 754 755static __inline void 756bus_space_set_region_1(tag, bsh, offset, val, count) 757 bus_space_tag_t tag; 758 bus_space_handle_t bsh; 759 bus_size_t offset; 760 u_int8_t val; 761 size_t count; 762{ 763 volatile u_int8_t *d; 764 765 d = (volatile u_int8_t *)(bsh + offset); 766 while (count--) 767 *d++ = val; 768 __asm__ volatile("eieio; sync"); 769} 770 771static __inline void 772bus_space_set_region_2(tag, bsh, offset, val, count) 773 bus_space_tag_t tag; 774 bus_space_handle_t bsh; 775 bus_size_t offset; 776 u_int16_t val; 777 size_t count; 778{ 779 volatile u_int16_t *d; 780 781 d = (volatile u_int16_t *)(bsh + offset); 782 while (count--) 783 __asm__ volatile("sthbrx %0, 0, %1" :: 784 "r"(val), "r"(d++)); 785 __asm__ volatile("eieio; sync"); 786} 787 788static __inline void 789bus_space_set_region_4(tag, bsh, offset, val, count) 790 bus_space_tag_t tag; 791 bus_space_handle_t bsh; 792 bus_size_t offset; 793 u_int32_t val; 794 size_t count; 795{ 796 volatile u_int32_t *d; 797 798 d = (volatile u_int32_t *)(bsh + offset); 799 while (count--) 800 __asm__ volatile("stwbrx %0, 0, %1" :: 801 "r"(val), "r"(d++)); 802 __asm__ volatile("eieio; sync"); 803} 804 805#define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!! 806 807/* 808 * void bus_space_set_region_stream_N __P((bus_space_tag_t tag, 809 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val, 810 * size_t count)); 811 * 812 * Write `count' 2, 4, or 8 byte stream value `val' to bus space described 813 * by tag/handle starting at `offset'. 814 */ 815static __inline void bus_space_set_region_stream_2 __P((bus_space_tag_t, 816 bus_space_handle_t, bus_size_t, u_int16_t, size_t)); 817static __inline void bus_space_set_region_stream_4 __P((bus_space_tag_t, 818 bus_space_handle_t, bus_size_t, u_int32_t, size_t)); 819 820 821static __inline void 822bus_space_set_region_stream_2(tag, bsh, offset, val, count) 823 bus_space_tag_t tag; 824 bus_space_handle_t bsh; 825 bus_size_t offset; 826 u_int16_t val; 827 size_t count; 828{ 829 volatile u_int16_t *d; 830 831 d = (volatile u_int16_t *)(bsh + offset); 832 while (count--) 833 *d++ = val; 834 __asm__ volatile("eieio; sync"); 835} 836 837static __inline void 838bus_space_set_region_stream_4(tag, bsh, offset, val, count) 839 bus_space_tag_t tag; 840 bus_space_handle_t bsh; 841 bus_size_t offset; 842 u_int32_t val; 843 size_t count; 844{ 845 volatile u_int32_t *d; 846 847 d = (volatile u_int32_t *)(bsh + offset); 848 while (count--) 849 *d++ = val; 850 __asm__ volatile("eieio; sync"); 851} 852 853#define bus_space_set_region_stream_8 \ 854 !!! bus_space_set_region_stream_8 unimplemented !!! 855 856/* 857 * void bus_space_copy_region_N __P((bus_space_tag_t tag, 858 * bus_space_handle_t bsh1, bus_size_t off1, 859 * bus_space_handle_t bsh2, bus_size_t off2, 860 * size_t count)); 861 * 862 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting 863 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. 864 */ 865 866static __inline void bus_space_copy_region_1 __P((bus_space_tag_t, 867 bus_space_handle_t, bus_size_t, bus_space_handle_t, 868 bus_size_t, size_t)); 869static __inline void bus_space_copy_region_2 __P((bus_space_tag_t, 870 bus_space_handle_t, bus_size_t, bus_space_handle_t, 871 bus_size_t, size_t)); 872static __inline void bus_space_copy_region_4 __P((bus_space_tag_t, 873 bus_space_handle_t, bus_size_t, bus_space_handle_t, 874 bus_size_t, size_t)); 875 876static __inline void 877bus_space_copy_region_1(t, h1, o1, h2, o2, c) 878 bus_space_tag_t t; 879 bus_space_handle_t h1; 880 bus_size_t o1; 881 bus_space_handle_t h2; 882 bus_size_t o2; 883 size_t c; 884{ 885 bus_addr_t addr1 = h1 + o1; 886 bus_addr_t addr2 = h2 + o2; 887 888 if (addr1 >= addr2) { 889 /* src after dest: copy forward */ 890 for (; c != 0; c--, addr1++, addr2++) 891 *(volatile u_int8_t *)(addr2) = 892 *(volatile u_int8_t *)(addr1); 893 } else { 894 /* dest after src: copy backwards */ 895 for (addr1 += (c - 1), addr2 += (c - 1); 896 c != 0; c--, addr1--, addr2--) 897 *(volatile u_int8_t *)(addr2) = 898 *(volatile u_int8_t *)(addr1); 899 } 900} 901 902static __inline void 903bus_space_copy_region_2(t, h1, o1, h2, o2, c) 904 bus_space_tag_t t; 905 bus_space_handle_t h1; 906 bus_size_t o1; 907 bus_space_handle_t h2; 908 bus_size_t o2; 909 size_t c; 910{ 911 bus_addr_t addr1 = h1 + o1; 912 bus_addr_t addr2 = h2 + o2; 913 914 if (addr1 >= addr2) { 915 /* src after dest: copy forward */ 916 for (; c != 0; c--, addr1 += 2, addr2 += 2) 917 *(volatile u_int16_t *)(addr2) = 918 *(volatile u_int16_t *)(addr1); 919 } else { 920 /* dest after src: copy backwards */ 921 for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1); 922 c != 0; c--, addr1 -= 2, addr2 -= 2) 923 *(volatile u_int16_t *)(addr2) = 924 *(volatile u_int16_t *)(addr1); 925 } 926} 927 928static __inline void 929bus_space_copy_region_4(t, h1, o1, h2, o2, c) 930 bus_space_tag_t t; 931 bus_space_handle_t h1; 932 bus_size_t o1; 933 bus_space_handle_t h2; 934 bus_size_t o2; 935 size_t c; 936{ 937 bus_addr_t addr1 = h1 + o1; 938 bus_addr_t addr2 = h2 + o2; 939 940 if (addr1 >= addr2) { 941 /* src after dest: copy forward */ 942 for (; c != 0; c--, addr1 += 4, addr2 += 4) 943 *(volatile u_int32_t *)(addr2) = 944 *(volatile u_int32_t *)(addr1); 945 } else { 946 /* dest after src: copy backwards */ 947 for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1); 948 c != 0; c--, addr1 -= 4, addr2 -= 4) 949 *(volatile u_int32_t *)(addr2) = 950 *(volatile u_int32_t *)(addr1); 951 } 952} 953 954#define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!! 955 956/* 957 * Bus read/write barrier methods. 958 * 959 * void bus_space_barrier __P((bus_space_tag_t tag, 960 * bus_space_handle_t bsh, bus_size_t offset, 961 * bus_size_t len, int flags)); 962 * 963 */ 964#define bus_space_barrier(t, h, o, l, f) \ 965 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f))) 966#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 967#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 968 969#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 970 971/* 972 * Bus DMA methods. 973 */ 974 975/* 976 * Flags used in various bus DMA methods. 977 */ 978#define BUS_DMA_WAITOK 0x00 /* safe to sleep (pseudo-flag) */ 979#define BUS_DMA_NOWAIT 0x01 /* not safe to sleep */ 980#define BUS_DMA_ALLOCNOW 0x02 /* perform resource allocation now */ 981#define BUS_DMA_COHERENT 0x04 /* hint: map memory DMA coherent */ 982#define BUS_DMA_BUS1 0x10 /* placeholders for bus functions... */ 983#define BUS_DMA_BUS2 0x20 984#define BUS_DMA_BUS3 0x40 985#define BUS_DMA_BUS4 0x80 986 987/* Forwards needed by prototypes below. */ 988struct mbuf; 989struct uio; 990 991/* 992 * Operations performed by bus_dmamap_sync(). 993 */ 994#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 995#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 996#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 997#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 998 999typedef struct prep_bus_dma_tag *bus_dma_tag_t; 1000typedef struct prep_bus_dmamap *bus_dmamap_t; 1001 1002/* 1003 * bus_dma_segment_t 1004 * 1005 * Describes a single contiguous DMA transaction. Values 1006 * are suitable for programming into DMA registers. 1007 */ 1008struct prep_bus_dma_segment { 1009 bus_addr_t ds_addr; /* DMA address */ 1010 bus_size_t ds_len; /* length of transfer */ 1011}; 1012typedef struct prep_bus_dma_segment bus_dma_segment_t; 1013 1014/* 1015 * bus_dma_tag_t 1016 * 1017 * A machine-dependent opaque type describing the implementation of 1018 * DMA for a given bus. 1019 */ 1020 1021struct prep_bus_dma_tag { 1022 /* 1023 * The `bounce threshold' is checked while we are loading 1024 * the DMA map. If the physical address of the segment 1025 * exceeds the threshold, an error will be returned. The 1026 * caller can then take whatever action is necessary to 1027 * bounce the transfer. If this value is 0, it will be 1028 * ignored. 1029 */ 1030 bus_addr_t _bounce_thresh; 1031 1032 /* 1033 * DMA mapping methods. 1034 */ 1035 int (*_dmamap_create) __P((bus_dma_tag_t, bus_size_t, int, 1036 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 1037 void (*_dmamap_destroy) __P((bus_dma_tag_t, bus_dmamap_t)); 1038 int (*_dmamap_load) __P((bus_dma_tag_t, bus_dmamap_t, void *, 1039 bus_size_t, struct proc *, int)); 1040 int (*_dmamap_load_mbuf) __P((bus_dma_tag_t, bus_dmamap_t, 1041 struct mbuf *, int)); 1042 int (*_dmamap_load_uio) __P((bus_dma_tag_t, bus_dmamap_t, 1043 struct uio *, int)); 1044 int (*_dmamap_load_raw) __P((bus_dma_tag_t, bus_dmamap_t, 1045 bus_dma_segment_t *, int, bus_size_t, int)); 1046 void (*_dmamap_unload) __P((bus_dma_tag_t, bus_dmamap_t)); 1047 void (*_dmamap_sync) __P((bus_dma_tag_t, bus_dmamap_t, 1048 bus_addr_t, bus_size_t, int)); 1049 1050 /* 1051 * DMA memory utility functions. 1052 */ 1053 int (*_dmamem_alloc) __P((bus_dma_tag_t, bus_size_t, bus_size_t, 1054 bus_size_t, bus_dma_segment_t *, int, int *, int)); 1055 void (*_dmamem_free) __P((bus_dma_tag_t, 1056 bus_dma_segment_t *, int)); 1057 int (*_dmamem_map) __P((bus_dma_tag_t, bus_dma_segment_t *, 1058 int, size_t, caddr_t *, int)); 1059 void (*_dmamem_unmap) __P((bus_dma_tag_t, caddr_t, size_t)); 1060 paddr_t (*_dmamem_mmap) __P((bus_dma_tag_t, bus_dma_segment_t *, 1061 int, off_t, int, int)); 1062}; 1063 1064#define bus_dmamap_create(t, s, n, m, b, f, p) \ 1065 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 1066#define bus_dmamap_destroy(t, p) \ 1067 (*(t)->_dmamap_destroy)((t), (p)) 1068#define bus_dmamap_load(t, m, b, s, p, f) \ 1069 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 1070#define bus_dmamap_load_mbuf(t, m, b, f) \ 1071 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 1072#define bus_dmamap_load_uio(t, m, u, f) \ 1073 (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 1074#define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 1075 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 1076#define bus_dmamap_unload(t, p) \ 1077 (*(t)->_dmamap_unload)((t), (p)) 1078#define bus_dmamap_sync(t, p, o, l, ops) \ 1079 (void)((t)->_dmamap_sync ? \ 1080 (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) : (void)0) 1081 1082#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 1083 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) 1084#define bus_dmamem_free(t, sg, n) \ 1085 (*(t)->_dmamem_free)((t), (sg), (n)) 1086#define bus_dmamem_map(t, sg, n, s, k, f) \ 1087 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) 1088#define bus_dmamem_unmap(t, k, s) \ 1089 (*(t)->_dmamem_unmap)((t), (k), (s)) 1090#define bus_dmamem_mmap(t, sg, n, o, p, f) \ 1091 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) 1092 1093/* 1094 * bus_dmamap_t 1095 * 1096 * Describes a DMA mapping. 1097 */ 1098struct prep_bus_dmamap { 1099 /* 1100 * PRIVATE MEMBERS: not for use my machine-independent code. 1101 */ 1102 bus_size_t _dm_size; /* largest DMA transfer mappable */ 1103 int _dm_segcnt; /* number of segs this map can map */ 1104 bus_size_t _dm_maxsegsz; /* largest possible segment */ 1105 bus_size_t _dm_boundary; /* don't cross this */ 1106 bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */ 1107 int _dm_flags; /* misc. flags */ 1108 1109 void *_dm_cookie; /* cookie for bus-specific functions */ 1110 1111 /* 1112 * PUBLIC MEMBERS: these are used by machine-independent code. 1113 */ 1114 bus_size_t dm_mapsize; /* size of the mapping */ 1115 int dm_nsegs; /* # valid segments in mapping */ 1116 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 1117}; 1118 1119#ifdef _PREP_BUS_DMA_PRIVATE 1120int _bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 1121 bus_size_t, int, bus_dmamap_t *)); 1122void _bus_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 1123int _bus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 1124 bus_size_t, struct proc *, int)); 1125int _bus_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, 1126 struct mbuf *, int)); 1127int _bus_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, 1128 struct uio *, int)); 1129int _bus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 1130 bus_dma_segment_t *, int, bus_size_t, int)); 1131void _bus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 1132void _bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1133 bus_size_t, int)); 1134 1135int _bus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 1136 bus_size_t alignment, bus_size_t boundary, 1137 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags)); 1138void _bus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 1139 int nsegs)); 1140int _bus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 1141 int nsegs, size_t size, caddr_t *kvap, int flags)); 1142void _bus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva, 1143 size_t size)); 1144paddr_t _bus_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 1145 int nsegs, off_t off, int prot, int flags)); 1146 1147int _bus_dmamem_alloc_range __P((bus_dma_tag_t tag, bus_size_t size, 1148 bus_size_t alignment, bus_size_t boundary, 1149 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags, 1150 paddr_t low, paddr_t high)); 1151#endif /* _PREP_BUS_DMA_PRIVATE */ 1152#endif /* _PREP_BUS_H_ */ 1153