chpidpnp.h revision 1.3
1 /* $NetBSD: chpidpnp.h,v 1.3 2007/10/17 19:56:49 garbled Exp $ */ 2 /*- 3 * Copyright (c) 2006 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Tim Rightnour 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Based on: 40 * IBM Power Personal Systems Architecture: Residual Data 41 * Document Number: PPS-AR-FW0001 Rev 0.5 April 3, 1996 42 */ 43 44 #ifndef _CHPIDPNP_H_ 45 #define _CHPIDPNP_H_ 46 47 #define ChipID_Packet 0x70 /* tag for ChipIdPack without size */ 48 49 /* the words MOT and IBM are made from these two bytes */ 50 #define CHIP_VENDOR_IBM0 0x24 51 #define CHIP_VENDOR_IBM1 0x4d 52 #define CHIP_VENDOR_MOT0 0x35 53 #define CHIP_VENDOR_MOT1 0xf4 54 55 /* 56 * The chipid is the vendor id followed by 4 hex digits, e.g. for IBM 57 * platforms: Chip_ID=IBMxxxx. To avoid confusion with PnP Device IDs, IBM 58 * Chip IDs will begin at 0x8000. 59 */ 60 typedef enum _Chip_Type { 61 Chip_MemCont = 0, 62 Chip_ISABridge = 1, 63 Chip_PCIBridge = 2, 64 Chip_PCMCIABridge = 3, 65 Chip_EISABridge = 4, 66 Chip_MCABridge = 5, 67 Chip_L2Cache = 6, 68 Chip_PM = 7, 69 Chip_IntrCont = 8, 70 Chip_MiscPlanar = 9, 71 } Chip_Type; 72 73 typedef enum _Chip_ID { 74 75 /* Memory Controllers Memory Controller range: IBM80xx */ 76 Dakota = 0x8001, /* IBM8001: IBM North/South Dakota */ 77 Idaho = 0x8002, /* IBM8002: IBM Idaho */ 78 Eagle = 0x8003, /* IBM8003: Motorola Eagle */ 79 Kauai_Lanai = 0x8004, /* IBM8004: IBM Kauai/Lanai */ 80 Montana_Nevada = 0x8005, /* IBM8005: IBM Montana/Nevada */ 81 Union = 0x8006, /* IBM8006: IBM Union */ 82 Cobra_Viper = 0x8007, /* IBM8007: IBM Cobra/Viper */ 83 Grackle = 0x8008, /* IBM8008: Motorola Grackle */ 84 85 /* ISA Bridge chips Bus Bridge Range: IBM81xx */ 86 SIO_ZB = 0x8100, /* IBM8100: Intel 82378ZB */ 87 FireCoral = 0x8101, /* IBM8101: IBM FireCoral */ 88 89 /* PCI Bridge chips */ 90 Python = 0x8102, /* IBM8102: IBM Python */ 91 DEC21050 = 0x8103, /* IBM8103: PCI-PCI (dec 21050) */ 92 IBM2782351 = 0x8106, /* IBM8106: PCI-PCI */ 93 IBM2782352 = 0x8109, /* IBM8109: PCI-PCI352 */ 94 95 /* PCMCIA Bridge Chips */ 96 INTEL_8236SL = 0x8104, /* IBM8104: Intel 8236SL */ 97 RICOH_RF5C366C = 0x8105, /* IBM8105: RICOH RF5C366C */ 98 99 /* EISA Bridge Chips */ 100 INTEL_82374 = 0x8108, /* IBM8108: Intel 82374/82375 */ 101 102 /* MCA Bridge Chips */ 103 MCACoral = 0x8107, /* IBM8107: 6xxxMx - T=1 MCA (servers) */ 104 105 /* L2 Cache controller L2 Controller Range: IBM82xx */ 106 Cheyenne = 0x8200, /* IBM8200: IBM Cheyenne */ 107 IDT = 0x8201, /* IBM8201: IDT */ 108 Sony1PB = 0x8202, /* IBM8202: Sony1PB */ 109 Mamba = 0x8203, /* IBM8203: IBM Mamba */ 110 Alaska = 0x8204, /* IBM8204: IBM Alaska */ 111 Glance = 0x8205, /* IBM8205: IBM Glance */ 112 Ocelot = 0x8206, /* IBM8206: IBM Ocelot */ 113 114 /* Power management chips PM Range: IBM83xx */ 115 Carrera = 0x8300, /* IBM8300: IBM Carrera */ 116 Sig750 = 0x8301, /* IBM8301: Signetics 87C750 */ 117 118 /* Interrupt controller chips PIC Chip range: IBM84xx */ 119 MPIC_2 = 0x8400, /* IBM8400: IBM MPIC-2 */ 120 121 /* Miscellaneous Planar chips MISC Chip Range: IBM8Fxx */ 122 DallasRTC = 0x8F00, /* IBM8F00: Dallas 1385 compatible */ 123 Dallas1585 = 0x8F01, /* IBM8F01: Dallas 1585 compatible */ 124 Timer8254 = 0x8F10, /* IBM8F10: 8254-compatible timer */ 125 HarddiskLt = 0x8FF0, /* IBM8FF0: Op Panel HD light */ 126 MOTmk48 = 0x3040, /* MOT3040: mk48txx compatible */ 127 } Chip_ID; 128 129 /* small tag = 0x7n with n bytes. Type == 1 for ChipID 130 * VendorID0: 131 * bit(7) = 0 132 * bits(6:2) 1st character in compressed ASCII 133 * bits(1:0) 2nd character in compressed ASCII bits(4:3) 134 * VendorID1: 135 * bits(7:5) 2nd character in compressed ASCII bits(2:0) 136 * bits(4:0) 3rd character in compressed ASCII 137 * Name: 138 * Example: IBM8001 139 * I,B,M = 01001, 00010, 01101 140 * bytes 0,1 = 00100100,01001101 141 * = 2 4 4 D 142 * byte0 = 24 byte1 = 4D byte2 = 01 byte3 = 80 143 */ 144 typedef struct _ChipIDPack { 145 unsigned char Tag; 146 unsigned char Type; 147 unsigned char VendorID0; 148 unsigned char VendorID1; 149 unsigned char Name[2]; 150 } ChipIDPack; 151 152 #endif /* _CHPIDPNP_H_ */ 153
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