intr.h revision 1.24
1 /* $NetBSD: intr.h,v 1.24 2006/05/03 17:47:06 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _PREP_INTR_H_ 40 #define _PREP_INTR_H_ 41 42 /* Interrupt priority `levels'. */ 43 #define IPL_NONE 9 /* nothing */ 44 #define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45 #define IPL_SOFTNET 7 /* software network interrupt */ 46 #define IPL_BIO 6 /* block I/O */ 47 #define IPL_NET 5 /* network */ 48 #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49 #define IPL_TTY 3 /* terminal */ 50 #define IPL_VM 3 /* memory allocation */ 51 #define IPL_AUDIO 2 /* audio */ 52 #define IPL_CLOCK 1 /* clock */ 53 #define IPL_HIGH 1 /* everything */ 54 #define IPL_SERIAL 0 /* serial */ 55 #define NIPL 10 56 57 /* Interrupt sharing types. */ 58 #define IST_NONE 0 /* none */ 59 #define IST_PULSE 1 /* pulsed */ 60 #define IST_EDGE 2 /* edge-triggered */ 61 #define IST_LEVEL 3 /* level-triggered */ 62 63 #ifndef _LOCORE 64 #include <powerpc/softintr.h> 65 66 /* 67 * Interrupt handler chains. intr_establish() inserts a handler into 68 * the list. The handler is called with its (single) argument. 69 */ 70 struct intrhand { 71 int (*ih_fun)(void *); 72 void *ih_arg; 73 u_long ih_count; 74 struct intrhand *ih_next; 75 int ih_level; 76 int ih_irq; 77 }; 78 79 void do_pending_int(void); 80 81 void init_intr(void); 82 void init_intr_ivr(void); 83 void init_intr_openpic(void); 84 85 void enable_intr(void); 86 void disable_intr(void); 87 88 void *intr_establish(int, int, int, int (*)(void *), void *); 89 void intr_disestablish(void *); 90 91 void softnet(int); 92 void softserial(void); 93 int isa_intr(void); 94 void isa_intr_mask(int); 95 void isa_intr_clr(int); 96 void isa_setirqstat(int, int, int); 97 98 static __inline int splraise(int); 99 static __inline void spllower(int); 100 static __inline void set_sint(int); 101 102 extern volatile int cpl, ipending, astpending, tickspending; 103 extern int imen; 104 extern int imask[]; 105 extern long intrcnt[]; 106 extern unsigned intrcnt2[]; 107 extern struct intrhand *intrhand[]; 108 extern int intrtype[]; 109 extern vaddr_t prep_intr_reg; 110 111 /* 112 * Reorder protection in the following inline functions is 113 * achieved with the "eieio" instruction which the assembler 114 * seems to detect and then doesn't move instructions past.... 115 */ 116 static __inline int 117 splraise(int newcpl) 118 { 119 int oldcpl; 120 121 __asm volatile("sync; eieio\n"); /* don't reorder.... */ 122 oldcpl = cpl; 123 cpl = oldcpl | newcpl; 124 __asm volatile("sync; eieio\n"); /* reorder protect */ 125 return(oldcpl); 126 } 127 128 static __inline void 129 spllower(int newcpl) 130 { 131 132 __asm volatile("sync; eieio\n"); /* reorder protect */ 133 cpl = newcpl; 134 if(ipending & ~newcpl) 135 do_pending_int(); 136 __asm volatile("sync; eieio\n"); /* reorder protect */ 137 } 138 139 /* Following code should be implemented with lwarx/stwcx to avoid 140 * the disable/enable. i need to read the manual once more.... */ 141 static __inline void 142 set_sint(int pending) 143 { 144 int msrsave; 145 146 __asm ("mfmsr %0" : "=r"(msrsave)); 147 __asm volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 148 ipending |= pending; 149 __asm volatile ("mtmsr %0" :: "r"(msrsave)); 150 } 151 152 #define ICU_LEN 32 153 #define IRQ_SLAVE 2 154 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 155 #define I8259_INTR_NUM 16 156 #define OPENPIC_INTR_NUM ((ICU_LEN)-(I8259_INTR_NUM)) 157 #define CLKF_BASEPRI(frame) ((frame)->pri == 0) 158 159 #define PREP_INTR_REG 0xbffff000 160 #define INTR_VECTOR_REG 0xff0 161 162 #define SINT_CLOCK 0x20000000 163 #define SINT_NET 0x40000000 164 #define SINT_SERIAL 0x80000000 165 #define SPL_CLOCK 0x00000001 166 #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 167 168 #define CNT_SINT_NET 29 169 #define CNT_SINT_CLOCK 30 170 #define CNT_SINT_SERIAL 31 171 #define CNT_CLOCK 0 172 173 #define splbio() splraise(imask[IPL_BIO]) 174 #define splnet() splraise(imask[IPL_NET]) 175 #define spltty() splraise(imask[IPL_TTY]) 176 #define splclock() splraise(imask[IPL_CLOCK]) 177 #define splvm() splraise(imask[IPL_VM]) 178 #define splaudio() splraise(imask[IPL_AUDIO]) 179 #define splserial() splraise(imask[IPL_SERIAL]) 180 #define splstatclock() splclock() 181 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 182 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 183 #define splsoftnet() splraise(imask[IPL_SOFTNET]) 184 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 185 186 #define spllpt() spltty() 187 188 #define setsoftclock() set_sint(SINT_CLOCK); 189 #define setsoftnet() set_sint(SINT_NET); 190 #define setsoftserial() set_sint(SINT_SERIAL); 191 192 #define splhigh() splraise(imask[IPL_HIGH]) 193 #define splsched() splhigh() 194 #define spllock() splhigh() 195 #define splx(x) spllower(x) 196 #define spl0() spllower(0) 197 198 #endif /* !_LOCORE */ 199 200 #endif /* !_PREP_INTR_H_ */ 201
Indexes created Mon Sep 22 21:09:42 GMT 2025