intr.h revision 1.8
1 /* $NetBSD: intr.h,v 1.8 2001/06/17 15:57:12 nonaka Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _PREP_INTR_H_ 40 #define _PREP_INTR_H_ 41 42 /* Interrupt priority `levels'. */ 43 #define IPL_NONE 9 /* nothing */ 44 #define IPL_SOFTCLOCK 8 /* software clock interrupt */ 45 #define IPL_SOFTNET 7 /* software network interrupt */ 46 #define IPL_BIO 6 /* block I/O */ 47 #define IPL_NET 5 /* network */ 48 #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 49 #define IPL_TTY 3 /* terminal */ 50 #define IPL_IMP 3 /* memory allocation */ 51 #define IPL_AUDIO 2 /* audio */ 52 #define IPL_CLOCK 1 /* clock */ 53 #define IPL_HIGH 1 /* everything */ 54 #define IPL_SERIAL 0 /* serial */ 55 #define NIPL 10 56 57 /* Interrupt sharing types. */ 58 #define IST_NONE 0 /* none */ 59 #define IST_PULSE 1 /* pulsed */ 60 #define IST_EDGE 2 /* edge-triggered */ 61 #define IST_LEVEL 3 /* level-triggered */ 62 63 #ifndef _LOCORE 64 65 /* 66 * Interrupt handler chains. intr_establish() inserts a handler into 67 * the list. The handler is called with its (single) argument. 68 */ 69 struct intrhand { 70 int (*ih_fun) __P((void *)); 71 void *ih_arg; 72 u_long ih_count; 73 struct intrhand *ih_next; 74 int ih_level; 75 int ih_irq; 76 }; 77 78 void setsoftclock __P((void)); 79 void clearsoftclock __P((void)); 80 int splsoftclock __P((void)); 81 void setsoftnet __P((void)); 82 void clearsoftnet __P((void)); 83 int splsoftnet __P((void)); 84 85 void do_pending_int __P((void)); 86 87 void ext_intr __P((void)); 88 89 void enable_intr __P((void)); 90 void disable_intr __P((void)); 91 92 void *intr_establish __P((int, int, int, int (*) __P((void *)), void *)); 93 void intr_disestablish __P((void *)); 94 95 void softnet __P((void)); 96 void softserial __P((void)); 97 98 static __inline int splraise __P((int)); 99 static __inline void spllower __P((int)); 100 static __inline void set_sint __P((int)); 101 102 extern volatile int cpl, ipending, astpending, tickspending; 103 extern int imask[]; 104 extern long intrcnt[]; 105 extern struct intrhand *intrhand[]; 106 extern int intrtype[]; 107 108 extern paddr_t prep_intr_reg; 109 110 /* 111 * Reorder protection in the following inline functions is 112 * achived with the "eieio" instruction which the assembler 113 * seems to detect and then doen't move instructions past.... 114 */ 115 static __inline int 116 splraise(newcpl) 117 int newcpl; 118 { 119 int oldcpl; 120 121 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 122 oldcpl = cpl; 123 cpl = oldcpl | newcpl; 124 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 125 return(oldcpl); 126 } 127 128 static __inline void 129 spllower(newcpl) 130 int newcpl; 131 { 132 133 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 134 cpl = newcpl; 135 if(ipending & ~newcpl) 136 do_pending_int(); 137 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 138 } 139 140 /* Following code should be implemented with lwarx/stwcx to avoid 141 * the disable/enable. i need to read the manual once more.... */ 142 static __inline void 143 set_sint(pending) 144 int pending; 145 { 146 int msrsave; 147 148 __asm__ ("mfmsr %0" : "=r"(msrsave)); 149 __asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 150 ipending |= pending; 151 __asm__ volatile ("mtmsr %0" :: "r"(msrsave)); 152 } 153 154 #define ICU_LEN 32 155 #define IRQ_SLAVE 2 156 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE) 157 158 #define PREP_INTR_REG 0xbffff000 159 #define INTR_VECTOR_REG 0xff0 160 161 #define SINT_CLOCK 0x20000000 162 #define SINT_NET 0x40000000 163 #define SINT_SERIAL 0x80000000 164 #define SPL_CLOCK 0x00000001 165 #define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL) 166 167 #define CNT_SINT_NET 29 168 #define CNT_SINT_CLOCK 30 169 #define CNT_SINT_SERIAL 31 170 #define CNT_CLOCK 0 171 172 #define splbio() splraise(imask[IPL_BIO]) 173 #define splnet() splraise(imask[IPL_NET]) 174 #define spltty() splraise(imask[IPL_TTY]) 175 #define splclock() splraise(imask[IPL_CLOCK]) 176 #define splvm() splraise(imask[IPL_IMP]) 177 #define splaudio() splraise(imask[IPL_AUDIO]) 178 #define splserial() splraise(imask[IPL_SERIAL]) 179 #define splstatclock() splclock() 180 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 181 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 182 #define splsoftnet() splraise(imask[IPL_SOFTNET]) 183 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 184 185 #define spllpt() spltty() 186 187 #define setsoftclock() set_sint(SINT_CLOCK); 188 #define setsoftnet() set_sint(SINT_NET); 189 #define setsoftserial() set_sint(SINT_SERIAL); 190 191 #define splhigh() splraise(imask[IPL_HIGH]) 192 #define splsched() splhigh() 193 #define spllock() splhigh() 194 #define splx(x) spllower(x) 195 #define spl0() spllower(0) 196 197 #endif /* !_LOCORE */ 198 199 #endif /* !_PREP_INTR_H_ */ 200
Indexes created Tue Sep 23 23:09:58 GMT 2025