plic.c revision 1.1 1 1.1 skrll /* $NetBSD: plic.c,v 1.1 2023/05/07 12:41:48 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2022 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * Portions of this code is derived from software contributed to The NetBSD
8 1.1 skrll * Foundation by Simon Burge.
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include "opt_multiprocessor.h"
33 1.1 skrll
34 1.1 skrll #include <sys/cdefs.h>
35 1.1 skrll __KERNEL_RCSID(0, "$NetBSD: plic.c,v 1.1 2023/05/07 12:41:48 skrll Exp $");
36 1.1 skrll
37 1.1 skrll #include <sys/param.h>
38 1.1 skrll
39 1.1 skrll #include <sys/bus.h>
40 1.1 skrll #include <sys/cpu.h>
41 1.1 skrll #include <sys/kmem.h>
42 1.1 skrll
43 1.1 skrll #include <riscv/sysreg.h>
44 1.1 skrll #include <riscv/dev/plicreg.h>
45 1.1 skrll #include <riscv/dev/plicvar.h>
46 1.1 skrll
47 1.1 skrll #define PLIC_PRIORITY(irq) (PLIC_PRIORITY_BASE + (irq) * 4)
48 1.1 skrll
49 1.1 skrll #define PLIC_ENABLE(sc, c, irq) (PLIC_ENABLE_BASE + \
50 1.1 skrll sc->sc_context[(c)] * PLIC_ENABLE_SIZE + \
51 1.1 skrll ((irq / 32) * sizeof(uint32_t)))
52 1.1 skrll
53 1.1 skrll #define PLIC_CONTEXT(sc, c) (PLIC_CONTEXT_BASE + \
54 1.1 skrll sc->sc_context[(c)] * PLIC_CONTEXT_SIZE)
55 1.1 skrll #define PLIC_CLAIM(sc, c) (PLIC_CONTEXT(sc, c) + PLIC_CLAIM_COMPLETE_OFFS)
56 1.1 skrll #define PLIC_COMPLETE(sc, c) PLIC_CLAIM(sc, c) /* same address */
57 1.1 skrll #define PLIC_THRESHOLD(sc, c) (PLIC_CONTEXT(sc, c) + PLIC_THRESHOLD_OFFS)
58 1.1 skrll
59 1.1 skrll #define PLIC_READ(sc, reg) \
60 1.1 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
61 1.1 skrll #define PLIC_WRITE(sc, reg, val) \
62 1.1 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
63 1.1 skrll
64 1.1 skrll
65 1.1 skrll struct plic_softc *plic_sc;
66 1.1 skrll
67 1.1 skrll
68 1.1 skrll void *
69 1.1 skrll plic_intr_establish_xname(u_int irq, int ipl, int flags,
70 1.1 skrll int (*func)(void *), void *arg, const char *xname)
71 1.1 skrll {
72 1.1 skrll struct plic_softc * const sc = plic_sc;
73 1.1 skrll struct plic_intrhand *ih;
74 1.1 skrll
75 1.1 skrll /* XXX need a better CPU selection method */
76 1.1 skrll // u_int cidx = cpu_index(curcpu());
77 1.1 skrll u_int cidx = 0;
78 1.1 skrll
79 1.1 skrll evcnt_attach_dynamic(&sc->sc_intrevs[irq], EVCNT_TYPE_INTR, NULL,
80 1.1 skrll "plic", xname);
81 1.1 skrll
82 1.1 skrll ih = &sc->sc_intr[irq];
83 1.1 skrll KASSERTMSG(ih->ih_func == NULL,
84 1.1 skrll "Oops, we need to chain PLIC interrupt handlers");
85 1.1 skrll if (ih->ih_func != NULL) {
86 1.1 skrll aprint_error_dev(sc->sc_dev, "irq slot %d already used\n", irq);
87 1.1 skrll return NULL;
88 1.1 skrll }
89 1.1 skrll ih->ih_mpsafe = (flags & IST_MPSAFE) != 0;
90 1.1 skrll ih->ih_func = func;
91 1.1 skrll ih->ih_arg = arg;
92 1.1 skrll ih->ih_irq = irq;
93 1.1 skrll ih->ih_cidx = cidx;
94 1.1 skrll
95 1.1 skrll plic_set_priority(sc, irq, 1);
96 1.1 skrll plic_enable(sc, cidx, irq);
97 1.1 skrll
98 1.1 skrll return ih;
99 1.1 skrll }
100 1.1 skrll
101 1.1 skrll void
102 1.1 skrll plic_intr_disestablish(void *cookie)
103 1.1 skrll {
104 1.1 skrll struct plic_softc * const sc = plic_sc;
105 1.1 skrll struct plic_intrhand * const ih = cookie;
106 1.1 skrll const u_int cidx = ih->ih_cidx;
107 1.1 skrll const u_int irq = ih->ih_irq;
108 1.1 skrll
109 1.1 skrll plic_disable(sc, cidx, irq);
110 1.1 skrll plic_set_priority(sc, irq, 0);
111 1.1 skrll
112 1.1 skrll memset(&sc->sc_intr[irq], 0, sizeof(*sc->sc_intr));
113 1.1 skrll }
114 1.1 skrll
115 1.1 skrll int
116 1.1 skrll plic_intr(void *arg)
117 1.1 skrll {
118 1.1 skrll struct plic_softc * const sc = arg;
119 1.1 skrll const cpuid_t cpuid = cpu_number();
120 1.1 skrll const bus_addr_t claim_addr = PLIC_CLAIM(sc, cpuid);
121 1.1 skrll const bus_addr_t complete_addr = PLIC_COMPLETE(sc, cpuid);
122 1.1 skrll uint32_t pending;
123 1.1 skrll int rv = 0;
124 1.1 skrll
125 1.1 skrll while ((pending = PLIC_READ(sc, claim_addr)) > 0) {
126 1.1 skrll struct plic_intrhand *ih = &sc->sc_intr[pending];
127 1.1 skrll
128 1.1 skrll sc->sc_intrevs[pending].ev_count++;
129 1.1 skrll
130 1.1 skrll KASSERT(ih->ih_func != NULL);
131 1.1 skrll #ifdef MULTIPROCESSOR
132 1.1 skrll if (!ih->ih_mpsafe) {
133 1.1 skrll KERNEL_LOCK(1, NULL);
134 1.1 skrll rv |= ih->ih_func(ih->ih_arg);
135 1.1 skrll KERNEL_UNLOCK_ONE(NULL);
136 1.1 skrll } else
137 1.1 skrll #endif
138 1.1 skrll rv |= ih->ih_func(ih->ih_arg);
139 1.1 skrll
140 1.1 skrll PLIC_WRITE(sc, complete_addr, pending);
141 1.1 skrll }
142 1.1 skrll
143 1.1 skrll return rv;
144 1.1 skrll }
145 1.1 skrll
146 1.1 skrll void
147 1.1 skrll plic_enable(struct plic_softc *sc, u_int cpu, u_int irq)
148 1.1 skrll {
149 1.1 skrll KASSERT(irq < PLIC_NIRQ);
150 1.1 skrll const bus_addr_t addr = PLIC_ENABLE(sc, cpu, irq);
151 1.1 skrll const uint32_t mask = __BIT(irq % 32);
152 1.1 skrll
153 1.1 skrll uint32_t reg = PLIC_READ(sc, addr);
154 1.1 skrll reg |= mask;
155 1.1 skrll PLIC_WRITE(sc, addr, reg);
156 1.1 skrll }
157 1.1 skrll
158 1.1 skrll void
159 1.1 skrll plic_disable(struct plic_softc *sc, u_int cpu, u_int irq)
160 1.1 skrll {
161 1.1 skrll KASSERT(irq < PLIC_NIRQ);
162 1.1 skrll const bus_addr_t addr = PLIC_ENABLE(sc, cpu, irq);
163 1.1 skrll const uint32_t mask = __BIT(irq % 32);
164 1.1 skrll
165 1.1 skrll uint32_t reg = PLIC_READ(sc, addr);
166 1.1 skrll reg &= ~mask;
167 1.1 skrll PLIC_WRITE(sc, addr, reg);
168 1.1 skrll }
169 1.1 skrll
170 1.1 skrll void
171 1.1 skrll plic_set_priority(struct plic_softc *sc, u_int irq, uint32_t priority)
172 1.1 skrll {
173 1.1 skrll KASSERT(irq < PLIC_NIRQ);
174 1.1 skrll const bus_addr_t addr = PLIC_PRIORITY(irq);
175 1.1 skrll
176 1.1 skrll PLIC_WRITE(sc, addr, priority);
177 1.1 skrll }
178 1.1 skrll
179 1.1 skrll void
180 1.1 skrll plic_set_threshold(struct plic_softc *sc, cpuid_t cpu, uint32_t threshold)
181 1.1 skrll {
182 1.1 skrll const bus_addr_t addr = PLIC_THRESHOLD(sc, cpu);
183 1.1 skrll
184 1.1 skrll PLIC_WRITE(sc, addr, threshold);
185 1.1 skrll }
186 1.1 skrll
187 1.1 skrll int
188 1.1 skrll plic_attach_common(struct plic_softc *sc, bus_addr_t addr, bus_size_t size)
189 1.1 skrll {
190 1.1 skrll struct cpu_info *ci;
191 1.1 skrll CPU_INFO_ITERATOR cii;
192 1.1 skrll u_int irq;
193 1.1 skrll
194 1.1 skrll sc->sc_intr = kmem_zalloc(sizeof(*sc->sc_intr) * sc->sc_ndev,
195 1.1 skrll KM_SLEEP);
196 1.1 skrll sc->sc_intrevs = kmem_zalloc(sizeof(*sc->sc_intrevs) * sc->sc_ndev,
197 1.1 skrll KM_SLEEP);
198 1.1 skrll
199 1.1 skrll if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
200 1.1 skrll aprint_error("couldn't map registers\n");
201 1.1 skrll return -1;
202 1.1 skrll }
203 1.1 skrll
204 1.1 skrll aprint_naive("\n");
205 1.1 skrll aprint_normal("RISC-V PLIC (%u IRQs)\n", sc->sc_ndev);
206 1.1 skrll
207 1.1 skrll plic_sc = sc;
208 1.1 skrll
209 1.1 skrll /* Start with all interrupts disabled. */
210 1.1 skrll for (irq = PLIC_FIRST_IRQ; irq < sc->sc_ndev; irq++) {
211 1.1 skrll plic_set_priority(sc, irq, 0);
212 1.1 skrll }
213 1.1 skrll
214 1.1 skrll /* Set priority thresholds for all interrupts to 0 (not masked). */
215 1.1 skrll for (CPU_INFO_FOREACH(cii, ci)) {
216 1.1 skrll plic_set_threshold(sc, ci->ci_cpuid, 0);
217 1.1 skrll }
218 1.1 skrll
219 1.1 skrll return 0;
220 1.1 skrll }
221