xref: /src/sys/arch/riscv/include/frame.h

/* $NetBSD: frame.h,v 1.4 2020/11/04 07:51:08 skrll Exp $ */

/*-
 * Copyright (c) 2014 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Matt Thomas of 3am Software Foundry.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _RISCV_FRAME_H_
#define _RISCV_FRAME_H_

#include <riscv/reg.h>

struct trapframe {
	struct reg tf_regs __aligned(8);
	register_t tf_tval;		// supervisor trap value
	register_t tf_pc;		// supervisor exception program counter
	register_t tf_cause;		// supervisor cause register
	register_t tf_sr;		// supervisor status register
#define tf_reg		tf_regs.r_reg
#define tf_a0		tf_reg[_X_A0]
#define tf_t0		tf_reg[_X_T0]
#define tf_v0		tf_reg[_X_V0]
#define tf_v1		tf_reg[_X_V1]
#define tf_ra		tf_reg[_X_RA]
#define tf_sp		tf_reg[_X_SP]
};

#endif /* _RISCV_FRAME_H_ */