insn.h revision 1.1
1 /* $NetBSD: insn.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */ 2 /*- 3 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _RISCV_INSN_H_ 32 #define _RISCV_INSN_H_ 33 34 union riscv_insn { 35 uint32_t val; 36 struct { 37 unsigned int r_opcode : 7; 38 unsigned int r_rd : 5; 39 unsigned int r_funct3 : 3; 40 unsigned int r_rs1 : 5; 41 unsigned int r_rs2 : 5; 42 unsigned int r_funct7 : 7; 43 } type_r; 44 struct { 45 unsigned int rs_opcode : 7; 46 unsigned int rs_rd : 5; 47 unsigned int rs_funct3 : 3; 48 unsigned int rs_rs1 : 5; 49 unsigned int rs_shmat : 6; 50 unsigned int rs_funct6 : 6; 51 } type_rs; 52 struct { 53 unsigned int ra_opcode : 7; 54 unsigned int ra_rd : 5; 55 unsigned int ra_funct3 : 3; 56 unsigned int ra_rs1 : 5; 57 unsigned int ra_rs2 : 5; 58 unsigned int ra_rl : 1; 59 unsigned int ra_aq : 1; 60 unsigned int ra_funct5 : 6; 61 } type_ra; 62 struct { 63 unsigned int rf_opcode : 7; 64 unsigned int rf_rd : 5; 65 unsigned int rf_rm : 3; 66 unsigned int rf_rs1 : 5; 67 unsigned int rf_rs2 : 5; 68 unsigned int rf_funct2 : 2; 69 unsigned int rf_rs3 : 5; 70 } type_rf; 71 struct { 72 unsigned int i_opcode : 7; 73 unsigned int i_rd : 5; 74 unsigned int i_funct3 : 3; 75 unsigned int i_rs1 : 5; 76 signed int i_imm11to0 : 12; 77 } type_i; 78 struct { 79 unsigned int s_opcode : 7; 80 unsigned int s_imm4_to_0 : 5; 81 unsigned int s_funct3 : 3; 82 unsigned int s_rs1 : 5; 83 unsigned int s_rs2 : 5; 84 signed int s_imm11_to_5 : 7; 85 } type_s; 86 struct { 87 unsigned int sb_opcode : 7; 88 unsigned int sb_imm11 : 1; 89 unsigned int sb_imm4to1 : 4; 90 unsigned int sb_funct3 : 3; 91 unsigned int sb_rs1 : 5; 92 unsigned int sb_rs2 : 5; 93 unsigned int sb_imm10to5 : 6; 94 signed int sb_imm12 : 1; 95 } type_sb; 96 struct { 97 unsigned int u_opcode : 7; 98 unsigned int u_rd : 5; 99 signed int u_imm31to12 : 20; 100 } type_u; 101 struct { 102 unsigned int uj_opcode : 7; 103 unsigned int uj_rd : 5; 104 unsigned int uj_imm19to12 : 9; 105 unsigned int uj_imm11 : 1; 106 unsigned int uj_imm10to1 : 9; 107 signed int uj_imm20 : 1; 108 } type_uj; 109 }; 110 111 #define OPCODE_P(i, x) (((i) & 0b1111111) == ((OPCODE_##x<<2)|0b11)) 112 113 #define OPCODE_LOAD 0b00000 114 #define OPCODE_LOADFP 0b00001 115 #define OPCODE_CUSTOM0 0b00010 116 #define OPCODE_MISCMEM 0b00011 117 #define OPCODE_OPIMM 0b00100 118 #define OPCODE_AUIPC 0b00101 119 #define OPCODE_OPIMM32 0b00110 120 #define OPCODE_X48a 0b00111 121 122 #define OPCODE_STORE 0b01000 123 #define OPCODE_STOREFP 0b01001 124 #define OPCODE_CUSTOM1 0b01010 125 #define OPCODE_AMO 0b01011 126 #define OPCODE_OP 0b01100 127 #define OPCODE_LUI 0b01101 128 #define OPCODE_OP32 0b01110 129 #define OPCODE_X64 0b01111 130 131 #define OPCODE_MADD 0b10000 // FMADD.[S,D] 132 #define OPCODE_MSUB 0b10001 // FMSUB.[S,D] 133 #define OPCODE_NMSUB 0b10010 // FNMADD.[S,D] 134 #define OPCODE_NMADD 0b10011 // FNMSUB.[S,D] 135 #define OPCODE_OPFP 0b10100 136 #define OPCODE_rsvd21 0b10101 137 #define OPCODE_CUSTOM2 0b10110 138 #define OPCODE_X48b 0b10111 139 140 #define OPCODE_BRANCH 0b11000 141 #define OPCODE_JALR 0b11001 142 #define OPCODE_rsvd26 0b11010 143 #define OPCODE_JAL 0b11011 144 #define OPCODE_SYSTEM 0b11100 145 #define OPCODE_rsvd29 0b11101 146 #define OPCODE_CUSTOM3 0b11110 147 #define OPCODE_X80 0b11111 148 149 // LOAD (0x00000) 150 #define LOAD_LB 0b000 151 #define LOAD_LH 0b001 152 #define LOAD_LW 0b010 153 #define LOAD_LD 0b011 // RV64I 154 #define LOAD_LBU 0b100 155 #define LOAD_LHU 0b101 156 #define LOAD_LWU 0b110 // RV64I 157 158 // LOADFP (0x00001) 159 #define LOADFP_FLW 0b010 160 #define LOADFP_FLD 0b011 161 162 // MISCMEM (0x00010) 163 #define MISCMEM_FENCE 0b000 164 #define MISCMEM_FENCEI 0b001 165 166 // OPIMM (0b00100) and OPIMM32 (0b00110) -- see OP (0b01100) 167 168 // AUIPC (0b00101) - no functions 169 170 // STORE (0b01000) 171 #define STORE_SB 0b000 172 #define STORE_SH 0b001 173 #define STORE_SW 0b010 174 #define STORE_SD 0b011 // RV64I 175 176 // STOREFP (0b01001) 177 #define STOREFP_FSW 0b010 178 #define STOREFP_FSD 0b011 179 180 // AMO (0b01011) 181 #define AMO_W 0b010 182 #define AMO_D 0b011 183 184 // AMO funct5 185 #define AMO_ADD 0b00000 186 #define AMO_SWAP 0b00001 187 #define AMO_LR 0b00010 188 #define AMO_SC 0b00011 189 #define AMO_XOR 0b00100 190 #define AMO_OR 0b01000 191 #define AMO_AND 0b01100 192 #define AMO_MIN 0b10000 193 #define AMO_MAX 0b10100 194 #define AMO_MINU 0b11000 195 #define AMO_MAXU 0b11100 196 197 // OPIMM (0b00100), OPIMM32 (0b00110), OP (0b01100), OP32 (0b01110) 198 #define OP_ADDSUB 0b000 199 #define OP_SLL 0b001 200 #define OP_SLT 0b010 201 #define OP_SLTU 0b011 202 #define OP_XOR 0b100 203 #define OP_SRX 0b101 204 #define OP_OR 0b110 205 #define OP_AND 0b111 206 207 #define OP_FUNCT6_SRX_SRL 0b000000 208 #define OP_FUNCT6_SRX_SRA 0b010000 209 210 #define OP_FUNCT7_ADD 0b0000000 211 #define OP_FUNCT7_SUB 0b0100000 212 213 #define OP_MUL 0b000 214 #define OP_MULH 0b001 215 #define OP_MULHSU 0b010 216 #define OP_MULHU 0b011 217 #define OP_DIV 0b100 218 #define OP_DIVU 0b101 219 #define OP_REM 0b110 220 #define OP_REMU 0b111 221 222 #define OP_FUNCT7_MULDIV 0b0000001 223 224 // LUI (0b01101) - no functions 225 226 // MADD (0b10000) 227 228 #define MXXX_S 0b00 229 //#define MXXX_S 0b01 230 231 // MSUB (0b10001) 232 // NMADD (0b10010) 233 // NMSUB (0b10011) 234 // OPFP (0b10100) 235 236 #define OPFP_ADD 0b00000 237 #define OPFP_SUB 0b00001 238 #define OPFP_MUL 0b00010 239 #define OPFP_DIV 0b00011 240 #define OPFP_SGNJ 0b00100 241 #define OPFP_MINMAX 0b00101 242 #define OPFP_SQRT 0b01011 243 #define OPFP_CMP 0b10100 244 #define OPFP_CVT 0b11000 245 #define OPFP_MV 0b11100 246 #define OPFP_MV 0b11100 247 248 #define SJGN_SGNJ 0b000 249 #define SJGN_SGNJN 0b001 250 #define SJGN_SGNJX 0b010 251 252 // BRANCH (0b11000) 253 #define BRANCH_BEQ 0b000 254 #define BRANCH_BNE 0b001 255 #define BRANCH_BLT 0b100 256 #define BRANCH_BGE 0b101 257 #define BRANCH_BLTU 0b110 258 #define BRANCH_BGEU 0b111 259 260 // JALR (0b11001) - no functions 261 // JAL (0b11011) - no functions 262 // SYSTEM (0b11100) 263 264 #define SYSTEM_SFUNC 0b000 265 #define SYSTEM_RDREG 0b010 266 267 #define SFUNC_RS_SCALL 0b00000 268 #define SFUNC_RS_SBREAK 0b00001 269 270 #define RDREG_LO 0b1100000 271 #define RDREG_HI 0b1100100 272 #define RDREG_RS_CYCLE 0b00000 273 #define RDREG_RS_TIME 0b00001 274 #define RDREG_RS_INSTRET 0b00010 275 276 #endif /* _RISCV_INSN_H_ */ 277
Indexes created Mon Sep 29 21:09:56 GMT 2025