insn.h revision 1.1.34.1
1 /* $NetBSD: insn.h,v 1.1.34.1 2020/12/14 14:38:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _RISCV_INSN_H_ 33 #define _RISCV_INSN_H_ 34 35 union riscv_insn { 36 uint32_t val; 37 struct { 38 unsigned int r_opcode : 7; 39 unsigned int r_rd : 5; 40 unsigned int r_funct3 : 3; 41 unsigned int r_rs1 : 5; 42 unsigned int r_rs2 : 5; 43 unsigned int r_funct7 : 7; 44 } type_r; 45 struct { 46 unsigned int rs_opcode : 7; 47 unsigned int rs_rd : 5; 48 unsigned int rs_funct3 : 3; 49 unsigned int rs_rs1 : 5; 50 unsigned int rs_shmat : 6; 51 unsigned int rs_funct6 : 6; 52 } type_rs; 53 struct { 54 unsigned int ra_opcode : 7; 55 unsigned int ra_rd : 5; 56 unsigned int ra_funct3 : 3; 57 unsigned int ra_rs1 : 5; 58 unsigned int ra_rs2 : 5; 59 unsigned int ra_rl : 1; 60 unsigned int ra_aq : 1; 61 unsigned int ra_funct5 : 6; 62 } type_ra; 63 struct { 64 unsigned int rf_opcode : 7; 65 unsigned int rf_rd : 5; 66 unsigned int rf_rm : 3; 67 unsigned int rf_rs1 : 5; 68 unsigned int rf_rs2 : 5; 69 unsigned int rf_funct2 : 2; 70 unsigned int rf_rs3 : 5; 71 } type_rf; 72 struct { 73 unsigned int i_opcode : 7; 74 unsigned int i_rd : 5; 75 unsigned int i_funct3 : 3; 76 unsigned int i_rs1 : 5; 77 signed int i_imm11to0 : 12; 78 } type_i; 79 struct { 80 unsigned int s_opcode : 7; 81 unsigned int s_imm4_to_0 : 5; 82 unsigned int s_funct3 : 3; 83 unsigned int s_rs1 : 5; 84 unsigned int s_rs2 : 5; 85 signed int s_imm11_to_5 : 7; 86 } type_s; 87 struct { 88 unsigned int sb_opcode : 7; 89 unsigned int sb_imm11 : 1; 90 unsigned int sb_imm4to1 : 4; 91 unsigned int sb_funct3 : 3; 92 unsigned int sb_rs1 : 5; 93 unsigned int sb_rs2 : 5; 94 unsigned int sb_imm10to5 : 6; 95 signed int sb_imm12 : 1; 96 } type_sb; 97 struct { 98 unsigned int u_opcode : 7; 99 unsigned int u_rd : 5; 100 signed int u_imm31to12 : 20; 101 } type_u; 102 struct { 103 unsigned int uj_opcode : 7; 104 unsigned int uj_rd : 5; 105 unsigned int uj_imm19to12 : 9; 106 unsigned int uj_imm11 : 1; 107 unsigned int uj_imm10to1 : 9; 108 signed int uj_imm20 : 1; 109 } type_uj; 110 }; 111 112 #define OPCODE_P(i, x) (((i) & 0b1111111) == ((OPCODE_##x<<2)|0b11)) 113 114 #define OPCODE_LOAD 0b00000 115 #define OPCODE_LOADFP 0b00001 116 #define OPCODE_CUSTOM0 0b00010 117 #define OPCODE_MISCMEM 0b00011 118 #define OPCODE_OPIMM 0b00100 119 #define OPCODE_AUIPC 0b00101 120 #define OPCODE_OPIMM32 0b00110 121 #define OPCODE_X48a 0b00111 122 123 #define OPCODE_STORE 0b01000 124 #define OPCODE_STOREFP 0b01001 125 #define OPCODE_CUSTOM1 0b01010 126 #define OPCODE_AMO 0b01011 127 #define OPCODE_OP 0b01100 128 #define OPCODE_LUI 0b01101 129 #define OPCODE_OP32 0b01110 130 #define OPCODE_X64 0b01111 131 132 #define OPCODE_MADD 0b10000 // FMADD.[S,D] 133 #define OPCODE_MSUB 0b10001 // FMSUB.[S,D] 134 #define OPCODE_NMSUB 0b10010 // FNMADD.[S,D] 135 #define OPCODE_NMADD 0b10011 // FNMSUB.[S,D] 136 #define OPCODE_OPFP 0b10100 137 #define OPCODE_rsvd21 0b10101 138 #define OPCODE_CUSTOM2 0b10110 139 #define OPCODE_X48b 0b10111 140 141 #define OPCODE_BRANCH 0b11000 142 #define OPCODE_JALR 0b11001 143 #define OPCODE_rsvd26 0b11010 144 #define OPCODE_JAL 0b11011 145 #define OPCODE_SYSTEM 0b11100 146 #define OPCODE_rsvd29 0b11101 147 #define OPCODE_CUSTOM3 0b11110 148 #define OPCODE_X80 0b11111 149 150 // LOAD (0x00000) 151 #define LOAD_LB 0b000 152 #define LOAD_LH 0b001 153 #define LOAD_LW 0b010 154 #define LOAD_LD 0b011 // RV64I 155 #define LOAD_LBU 0b100 156 #define LOAD_LHU 0b101 157 #define LOAD_LWU 0b110 // RV64I 158 159 // LOADFP (0x00001) 160 #define LOADFP_FLW 0b010 161 #define LOADFP_FLD 0b011 162 163 // MISCMEM (0x00010) 164 #define MISCMEM_FENCE 0b000 165 #define MISCMEM_FENCEI 0b001 166 167 // OPIMM (0b00100) and OPIMM32 (0b00110) -- see OP (0b01100) 168 169 // AUIPC (0b00101) - no functions 170 171 // STORE (0b01000) 172 #define STORE_SB 0b000 173 #define STORE_SH 0b001 174 #define STORE_SW 0b010 175 #define STORE_SD 0b011 // RV64I 176 177 // STOREFP (0b01001) 178 #define STOREFP_FSW 0b010 179 #define STOREFP_FSD 0b011 180 181 // AMO (0b01011) 182 #define AMO_W 0b010 183 #define AMO_D 0b011 184 185 // AMO funct5 186 #define AMO_ADD 0b00000 187 #define AMO_SWAP 0b00001 188 #define AMO_LR 0b00010 189 #define AMO_SC 0b00011 190 #define AMO_XOR 0b00100 191 #define AMO_OR 0b01000 192 #define AMO_AND 0b01100 193 #define AMO_MIN 0b10000 194 #define AMO_MAX 0b10100 195 #define AMO_MINU 0b11000 196 #define AMO_MAXU 0b11100 197 198 // OPIMM (0b00100), OPIMM32 (0b00110), OP (0b01100), OP32 (0b01110) 199 #define OP_ADDSUB 0b000 200 #define OP_SLL 0b001 201 #define OP_SLT 0b010 202 #define OP_SLTU 0b011 203 #define OP_XOR 0b100 204 #define OP_SRX 0b101 205 #define OP_OR 0b110 206 #define OP_AND 0b111 207 208 #define OP_FUNCT6_SRX_SRL 0b000000 209 #define OP_FUNCT6_SRX_SRA 0b010000 210 211 #define OP_FUNCT7_ADD 0b0000000 212 #define OP_FUNCT7_SUB 0b0100000 213 214 #define OP_MUL 0b000 215 #define OP_MULH 0b001 216 #define OP_MULHSU 0b010 217 #define OP_MULHU 0b011 218 #define OP_DIV 0b100 219 #define OP_DIVU 0b101 220 #define OP_REM 0b110 221 #define OP_REMU 0b111 222 223 #define OP_FUNCT7_MULDIV 0b0000001 224 225 // LUI (0b01101) - no functions 226 227 // MADD (0b10000) 228 229 #define MXXX_S 0b00 230 //#define MXXX_S 0b01 231 232 // MSUB (0b10001) 233 // NMADD (0b10010) 234 // NMSUB (0b10011) 235 // OPFP (0b10100) 236 237 #define OPFP_ADD 0b00000 238 #define OPFP_SUB 0b00001 239 #define OPFP_MUL 0b00010 240 #define OPFP_DIV 0b00011 241 #define OPFP_SGNJ 0b00100 242 #define OPFP_MINMAX 0b00101 243 #define OPFP_SQRT 0b01011 244 #define OPFP_CMP 0b10100 245 #define OPFP_CVT 0b11000 246 #define OPFP_MV 0b11100 247 #define OPFP_MV 0b11100 248 249 #define SJGN_SGNJ 0b000 250 #define SJGN_SGNJN 0b001 251 #define SJGN_SGNJX 0b010 252 253 // BRANCH (0b11000) 254 #define BRANCH_BEQ 0b000 255 #define BRANCH_BNE 0b001 256 #define BRANCH_BLT 0b100 257 #define BRANCH_BGE 0b101 258 #define BRANCH_BLTU 0b110 259 #define BRANCH_BGEU 0b111 260 261 // JALR (0b11001) - no functions 262 // JAL (0b11011) - no functions 263 // SYSTEM (0b11100) 264 265 #define SYSTEM_SFUNC 0b000 266 #define SYSTEM_RDREG 0b010 267 268 #define SFUNC_RS_SCALL 0b00000 269 #define SFUNC_RS_SBREAK 0b00001 270 271 #define RDREG_LO 0b1100000 272 #define RDREG_HI 0b1100100 273 #define RDREG_RS_CYCLE 0b00000 274 #define RDREG_RS_TIME 0b00001 275 #define RDREG_RS_INSTRET 0b00010 276 277 #endif /* _RISCV_INSN_H_ */ 278
Indexes created Wed Oct 22 13:09:56 GMT 2025