jh7100_clkc.c revision 1.6
1 /* $NetBSD: jh7100_clkc.c,v 1.6 2025/01/18 17:21:26 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: jh7100_clkc.c,v 1.6 2025/01/18 17:21:26 skrll Exp $"); 34 35 #include <sys/param.h> 36 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 40 #include <dev/clk/clk_backend.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <riscv/starfive/jh71x0_clkc.h> 45 46 47 #define JH7100_CLK_CPUNDBUS_ROOT 0 48 #define JH7100_CLK_DSP_ROOT 2 49 #define JH7100_CLK_GMACUSB_ROOT 3 50 #define JH7100_CLK_PERH0_ROOT 4 51 #define JH7100_CLK_PERH1_ROOT 5 52 #define JH7100_CLK_VOUT_ROOT 7 53 #define JH7100_CLK_AUDIO_ROOT 8 54 #define JH7100_CLK_VOUTBUS_ROOT 11 55 #define JH7100_CLK_CPUNBUS_ROOT_DIV 12 56 #define JH7100_CLK_DSP_ROOT_DIV 13 57 #define JH7100_CLK_PERH0_SRC 14 58 #define JH7100_CLK_PERH1_SRC 15 59 #define JH7100_CLK_PLL2_REF 19 60 #define JH7100_CLK_CPU_CORE 20 61 #define JH7100_CLK_CPU_AXI 21 62 #define JH7100_CLK_AHB_BUS 22 63 #define JH7100_CLK_APB1_BUS 23 64 #define JH7100_CLK_APB2_BUS 24 65 #define JH7100_CLK_DOM7AHB_BUS 26 66 #define JH7100_CLK_SGDMA2P_AXI 31 67 #define JH7100_CLK_SGDMA2P_AHB 33 68 #define JH7100_CLK_VP6_CORE 38 69 #define JH7100_CLK_JPEG_APB 50 70 #define JH7100_CLK_SGDMA1P_BUS 84 71 #define JH7100_CLK_SGDMA1P_AXI 85 72 #define JH7100_CLK_AUDIO_DIV 95 73 #define JH7100_CLK_AUDIO_SRC 96 74 #define JH7100_CLK_AUDIO_12288 97 75 #define JH7100_CLK_VOUT_SRC 109 76 #define JH7100_CLK_DISPBUS_SRC 110 77 #define JH7100_CLK_DISP_BUS 111 78 #define JH7100_CLK_DISP_AXI 112 79 #define JH7100_CLK_SDIO0_AHB 114 80 #define JH7100_CLK_SDIO0_CCLKINT 115 81 #define JH7100_CLK_SDIO0_CCLKINT_INV 116 82 #define JH7100_CLK_SDIO1_AHB 117 83 #define JH7100_CLK_SDIO1_CCLKINT 118 84 #define JH7100_CLK_SDIO1_CCLKINT_INV 119 85 #define JH7100_CLK_GMAC_AHB 120 86 #define JH7100_CLK_GMAC_ROOT_DIV 121 87 #define JH7100_CLK_GMAC_PTP_REF 122 88 #define JH7100_CLK_GMAC_GTX 123 89 #define JH7100_CLK_GMAC_RMII_TX 124 90 #define JH7100_CLK_GMAC_RMII_RX 125 91 #define JH7100_CLK_GMAC_TX 126 92 #define JH7100_CLK_GMAC_TX_INV 127 93 #define JH7100_CLK_GMAC_RX_PRE 128 94 #define JH7100_CLK_GMAC_RX_INV 129 95 #define JH7100_CLK_GMAC_RMII 130 96 #define JH7100_CLK_GMAC_TOPHYREF 131 97 #define JH7100_CLK_QSPI_AHB 137 98 #define JH7100_CLK_SEC_AHB 140 99 #define JH7100_CLK_TRNG_APB 144 100 #define JH7100_CLK_OTP_APB 145 101 #define JH7100_CLK_UART0_APB 146 102 #define JH7100_CLK_UART0_CORE 147 103 #define JH7100_CLK_UART1_APB 148 104 #define JH7100_CLK_UART1_CORE 149 105 #define JH7100_CLK_SPI0_APB 150 106 #define JH7100_CLK_SPI0_CORE 151 107 #define JH7100_CLK_SPI1_APB 152 108 #define JH7100_CLK_SPI1_CORE 153 109 #define JH7100_CLK_I2C0_APB 154 110 #define JH7100_CLK_I2C0_CORE 155 111 #define JH7100_CLK_I2C1_APB 156 112 #define JH7100_CLK_I2C1_CORE 157 113 #define JH7100_CLK_GPIO_APB 158 114 #define JH7100_CLK_UART2_APB 159 115 #define JH7100_CLK_UART2_CORE 160 116 #define JH7100_CLK_UART3_APB 161 117 #define JH7100_CLK_UART3_CORE 162 118 #define JH7100_CLK_SPI2_APB 163 119 #define JH7100_CLK_SPI2_CORE 164 120 #define JH7100_CLK_SPI3_APB 165 121 #define JH7100_CLK_SPI3_CORE 166 122 #define JH7100_CLK_I2C2_APB 167 123 #define JH7100_CLK_I2C2_CORE 168 124 #define JH7100_CLK_I2C3_APB 169 125 #define JH7100_CLK_I2C3_CORE 170 126 #define JH7100_CLK_WDTIMER_APB 171 127 #define JH7100_CLK_WDT_CORE 172 128 #define JH7100_CLK_PWM_APB 181 129 #define JH7100_CLK_TEMP_APB 183 130 #define JH7100_CLK_TEMP_SENSE 184 131 132 #define JH7100_CLK_PLL0_OUT 186 133 #define JH7100_CLK_PLL1_OUT 187 134 #define JH7100_CLK_PLL2_OUT 188 135 136 #define JH7100_NCLKS 189 137 138 #define JH7100_AUDCLK_ADC_MCLK 0 139 #define JH7100_AUDCLK_I2S1_MCLK 1 140 #define JH7100_AUDCLK_I2SADC_APB 2 141 #define JH7100_AUDCLK_I2SADC_BCLK 3 142 #define JH7100_AUDCLK_I2SADC_BCLK_N 4 143 #define JH7100_AUDCLK_I2SADC_LRCLK 5 144 #define JH7100_AUDCLK_PDM_APB 6 145 #define JH7100_AUDCLK_PDM_MCLK 7 146 #define JH7100_AUDCLK_I2SVAD_APB 8 147 #define JH7100_AUDCLK_SPDIF 9 148 #define JH7100_AUDCLK_SPDIF_APB 10 149 #define JH7100_AUDCLK_PWMDAC_APB 11 150 #define JH7100_AUDCLK_DAC_MCLK 12 151 #define JH7100_AUDCLK_I2SDAC_APB 13 152 #define JH7100_AUDCLK_I2SDAC_BCLK 14 153 #define JH7100_AUDCLK_I2SDAC_BCLK_N 15 154 #define JH7100_AUDCLK_I2SDAC_LRCLK 16 155 #define JH7100_AUDCLK_I2S1_APB 17 156 #define JH7100_AUDCLK_I2S1_BCLK 18 157 #define JH7100_AUDCLK_I2S1_BCLK_N 19 158 #define JH7100_AUDCLK_I2S1_LRCLK 20 159 #define JH7100_AUDCLK_I2SDAC16K_APB 21 160 #define JH7100_AUDCLK_APB0_BUS 22 161 #define JH7100_AUDCLK_DMA1P_AHB 23 162 #define JH7100_AUDCLK_USB_APB 24 163 #define JH7100_AUDCLK_USB_LPM 25 164 #define JH7100_AUDCLK_USB_STB 26 165 #define JH7100_AUDCLK_APB_EN 27 166 #define JH7100_AUDCLK_VAD_MEM 28 167 168 #define JH7100_AUDCLK_NCLKS 29 169 170 171 static const char *cpundbus_root_parents[] = { 172 "osc_sys", "pll0_out", "pll1_out", "pll2_out", 173 }; 174 175 static const char *dsp_root_parents[] = { 176 "osc_sys", "pll0_out", "pll1_out", "pll2_out", 177 }; 178 179 static const char *gmacusb_root_parents[] = { 180 "osc_sys", "pll0_out", "pll2_out", 181 }; 182 183 static const char *perh0_root_parents[] = { 184 "osc_sys", "pll0_out", 185 }; 186 187 static const char *perh1_root_parents[] = { 188 "osc_sys", "pll2_out", 189 }; 190 191 static const char *pll2_refclk_parents[] = { 192 "osc_sys", "osc_aud", 193 }; 194 195 static const char *vout_root_parents[] = { 196 "osc_aud", "pll0_out", "pll2_out", 197 }; 198 199 static const char *gmac_rx_pre_parents[] = { 200 "gmac_gr_mii_rxclk", "gmac_rmii_rxclk", 201 }; 202 203 static const char *gmac_tx_parents[] = { 204 "gmac_gtxclk", "gmac_tx_inv", "gmac_rmii_txclk", 205 }; 206 207 208 static struct jh71x0_clkc_clk jh7100_clocks[] = { 209 JH71X0CLKC_FIXED_FACTOR(JH7100_CLK_PLL0_OUT, "pll0_out", "osc_sys", 1, 40), 210 JH71X0CLKC_FIXED_FACTOR(JH7100_CLK_PLL1_OUT, "pll1_out", "osc_sys", 1, 64), 211 JH71X0CLKC_FIXED_FACTOR(JH7100_CLK_PLL2_OUT, "pll2_out", "pll2_refclk", 1, 55), 212 213 JH71X0CLKC_MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", cpundbus_root_parents), 214 JH71X0CLKC_MUX(JH7100_CLK_DSP_ROOT, "dsp_root", dsp_root_parents), 215 JH71X0CLKC_MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", gmacusb_root_parents), 216 JH71X0CLKC_MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", perh0_root_parents), 217 JH71X0CLKC_MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", perh1_root_parents), 218 JH71X0CLKC_MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", pll2_refclk_parents), 219 220 JH71X0CLKC_MUX(JH7100_CLK_VOUT_ROOT, "vout_root", vout_root_parents), 221 JH71X0CLKC_MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", vout_root_parents), 222 223 JH71X0CLKC_MUX_FLAGS(JH7100_CLK_GMAC_TX, "gmac_tx", gmac_tx_parents, CLK_SET_RATE_PARENT), 224 225 JH71X0CLKC_MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", gmac_rx_pre_parents), 226 227 JH71X0CLKC_DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 228 2, "cpundbus_root"), 229 JH71X0CLKC_DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, "perh0_root"), 230 JH71X0CLKC_DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, "perh1_root"), 231 232 JH71X0CLKC_DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, "cpunbus_root_div"), 233 JH71X0CLKC_DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, "ahb_bus"), 234 JH71X0CLKC_DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, "ahb_bus"), 235 JH71X0CLKC_DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, "cpunbus_root_div"), 236 JH71X0CLKC_DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, "cpu_core"), 237 JH71X0CLKC_DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, "gmacusb_root"), 238 JH71X0CLKC_DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, "dsp_root"), 239 JH71X0CLKC_DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, "cpunbus_root_div"), 240 241 JH71X0CLKC_DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, "voutbus_root"), 242 243 JH71X0CLKC_DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, "dispbus_src"), 244 245 JH71X0CLKC_GATE(JH7100_CLK_UART0_APB, "uart0_apb", "apb1_bus"), 246 JH71X0CLKC_GATE(JH7100_CLK_UART1_APB, "uart1_apb", "apb1_bus"), 247 JH71X0CLKC_GATE(JH7100_CLK_UART2_APB, "uart2_apb", "apb2_bus"), 248 JH71X0CLKC_GATE(JH7100_CLK_UART3_APB, "uart3_apb", "apb2_bus"), 249 JH71X0CLKC_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", "cpu_axi"), 250 JH71X0CLKC_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", "ahb_bus"), 251 JH71X0CLKC_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", "sgdma1p_bus"), 252 JH71X0CLKC_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", "apb1_bus"), 253 JH71X0CLKC_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", "apb1_bus"), 254 JH71X0CLKC_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", "apb1_bus"), 255 JH71X0CLKC_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", "apb2_bus"), 256 JH71X0CLKC_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", "apb2_bus"), 257 JH71X0CLKC_GATE(JH7100_CLK_TRNG_APB, "trng_apb", "apb1_bus"), 258 JH71X0CLKC_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", "ahb_bus"), 259 JH71X0CLKC_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", "ahb_bus"), 260 JH71X0CLKC_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", "ahb_bus"), 261 JH71X0CLKC_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", "apb1_bus"), 262 JH71X0CLKC_GATE(JH7100_CLK_PWM_APB, "pwm_apb", "apb2_bus"), 263 JH71X0CLKC_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", "ahb_bus"), 264 JH71X0CLKC_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", "apb1_bus"), 265 JH71X0CLKC_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", "apb1_bus"), 266 JH71X0CLKC_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", "apb2_bus"), 267 JH71X0CLKC_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", "apb2_bus"), 268 JH71X0CLKC_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", "ahb_bus"), 269 JH71X0CLKC_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", "ahb_bus"), 270 JH71X0CLKC_GATE(JH7100_CLK_OTP_APB, "otp_apb", "apb1_bus"), 271 JH71X0CLKC_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", "ahb_bus"), 272 JH71X0CLKC_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", "audio_div"), 273 JH71X0CLKC_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", "osc_aud"), 274 275 JH71X0CLKC_GATE(JH7100_CLK_DISP_AXI, "disp_axi", "disp_bus"), 276 277 JH71X0CLKC_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", "gmac_rmii_ref"), 278 279 JH71X0CLKC_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", "apb2_bus"), 280 281 JH71X0CLKC_GATE(JH7100_CLK_TEMP_APB, "temp_apb", "apb2_bus"), 282 283 JH71X0CLKC_GATEDIV(JH7100_CLK_UART0_CORE, "uart0_core", 63, "perh1_src"), 284 JH71X0CLKC_GATEDIV(JH7100_CLK_UART1_CORE, "uart1_core", 63, "perh1_src"), 285 JH71X0CLKC_GATEDIV(JH7100_CLK_UART2_CORE, "uart2_core", 63, "perh0_src"), 286 JH71X0CLKC_GATEDIV(JH7100_CLK_UART3_CORE, "uart3_core", 63, "perh0_src"), 287 JH71X0CLKC_GATEDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 63, "perh1_src"), 288 JH71X0CLKC_GATEDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 63, "perh1_src"), 289 JH71X0CLKC_GATEDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 63, "perh0_src"), 290 JH71X0CLKC_GATEDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 63, "perh0_src"), 291 JH71X0CLKC_GATEDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 31, "gmac_root_div"), 292 JH71X0CLKC_GATEDIV(JH7100_CLK_VP6_CORE, "vp6_core", 4, "dsp_root_div"), 293 JH71X0CLKC_GATEDIV(JH7100_CLK_VP6_CORE, "vp6_core", 4, "dsp_root_div"), 294 JH71X0CLKC_GATEDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 63, "perh1_src"), 295 JH71X0CLKC_GATEDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 63, "perh1_src"), 296 JH71X0CLKC_GATEDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 63, "perh0_src"), 297 JH71X0CLKC_GATEDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 63, "perh0_src"), 298 JH71X0CLKC_GATEDIV(JH7100_CLK_VP6_CORE, "vp6_core", 4, "dsp_root_div"), 299 JH71X0CLKC_GATEDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 24, "perh0_src"), 300 JH71X0CLKC_GATEDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 24, "perh1_src"), 301 JH71X0CLKC_GATEDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 8, "pll0_out"), 302 JH71X0CLKC_GATEDIV(JH7100_CLK_VOUT_SRC, "vout_src", 4, "vout_root"), 303 JH71X0CLKC_GATEDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 63, "perh0_src"), 304 JH71X0CLKC_GATEDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 255, "gmac_root_div"), 305 JH71X0CLKC_GATEDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 8, "gmac_rmii_ref"), 306 JH71X0CLKC_GATEDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 8, "gmac_rmii_ref"), 307 JH71X0CLKC_GATEDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 127, "gmac_root_div"), 308 JH71X0CLKC_GATEDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 31, "osc_sys"), 309 310 JH71X0CLKC_FRACDIV(JH7100_CLK_AUDIO_DIV, "audio_div", "audio_root"), 311 312 JH71X0CLKC_INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", "sdio0_cclkint"), 313 JH71X0CLKC_INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", "sdio1_cclkint"), 314 JH71X0CLKC_INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", "gmac_rx_pre"), 315 JH71X0CLKC_INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", "gmac_tx"), 316 }; 317 318 319 static const char *adc_mclk_parents[] = { 320 "audio_src", "audio_12288", 321 }; 322 323 static const char *i2s1_mclk_parents[] = { 324 "audio_src", "audio_12288", 325 }; 326 327 static const char *i2sadc_bclk_parents[] = { 328 "adc_mclk", "i2sadc_bclk_iopad" 329 }; 330 331 static const char *i2sadc_lrclk_parents[] = { 332 "i2sadc_bclk_n", "i2sadc_lrclk_iopad", "i2sadc_bclk", 333 }; 334 335 static const char *pdm_mclk_parents[] = { 336 "audio_src", "audio_12288", 337 }; 338 339 static const char *spdif_parents[] = { 340 "audio_src", "audio_12288", 341 }; 342 343 static const char *dac_mclk_parents[] = { 344 "audio_src", "audio_12288", 345 }; 346 347 static const char *i2sdac_bclk_parents[] = { 348 "dac_mclk", "i2sadc_blk_iopad", 349 }; 350 351 static const char *i2sdac_lrclk_parents[] = { 352 "i2s1_mclk", "i2sadc_blk_iopad", 353 }; 354 355 static const char *i2s1_bclk_parents[] = { 356 "i2s1_mclk", "i2sadc_blk_iopad", 357 }; 358 359 static const char *i2s1_lrclk_parents[] = { 360 "i2s1_bclk_n", "i2sadc_lrclk_iopad", 361 }; 362 363 static const char *vad_mem_parents[] = { 364 "vad_intmem", "audio_12288", 365 }; 366 367 368 static struct jh71x0_clkc_clk jh7100_audclk_clocks[] = { 369 JH71X0CLKC_MUXDIVGATE(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 15, adc_mclk_parents), 370 JH71X0CLKC_MUXDIVGATE(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 15, i2s1_mclk_parents), 371 372 JH71X0CLKC_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", "apb0_bus"), 373 374 JH71X0CLKC_MUXDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, i2sadc_bclk_parents), 375 376 JH71X0CLKC_INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", "i2sadc_bclk"), 377 JH71X0CLKC_MUXDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, i2sadc_lrclk_parents), 378 JH71X0CLKC_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", "apb0_bus"), 379 JH71X0CLKC_MUXDIVGATE(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 15, pdm_mclk_parents), 380 JH71X0CLKC_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", "apb0_bus"), 381 JH71X0CLKC_MUXDIVGATE(JH7100_AUDCLK_SPDIF, "spdif", 15, spdif_parents), 382 JH71X0CLKC_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", "apb0_bus"), 383 JH71X0CLKC_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", "apb0_bus"), 384 JH71X0CLKC_MUXDIVGATE(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 15, dac_mclk_parents), 385 JH71X0CLKC_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", "apb0_bus"), 386 JH71X0CLKC_MUXDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, i2sdac_bclk_parents), 387 JH71X0CLKC_INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", "i2sdac_bclk"), 388 JH71X0CLKC_MUXDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, i2sdac_lrclk_parents), 389 JH71X0CLKC_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", "apb0_bus"), 390 JH71X0CLKC_MUXDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, i2s1_bclk_parents), 391 JH71X0CLKC_INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", "i2s1_bclk"), 392 JH71X0CLKC_MUXDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, i2s1_lrclk_parents), 393 JH71X0CLKC_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", "apb0_bus"), 394 JH71X0CLKC_DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, "dom7ahb_bus"), 395 JH71X0CLKC_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", "dom7ahb_bus"), 396 JH71X0CLKC_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", /*CLK_IGNORE_UNUSED,*/ "apb_en"), 397 JH71X0CLKC_GATEDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", /*CLK_IGNORE_UNUSED,*/ 4, "usb_apb"), 398 JH71X0CLKC_GATEDIV(JH7100_AUDCLK_USB_STB, "usb_stb", /*CLK_IGNORE_UNUSED,*/ 3, "usb_apb"), 399 JH71X0CLKC_DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, "dom7ahb_bus"), 400 JH71X0CLKC_MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", vad_mem_parents), 401 }; 402 403 struct jh7100_clk_config { 404 const char *jhcc_name; 405 struct jh71x0_clkc_clk *jhcc_clocks; 406 size_t jhcc_nclks; 407 }; 408 409 static struct jh7100_clk_config jh7100_clk_config = { 410 .jhcc_name = "System", 411 .jhcc_clocks = jh7100_clocks, 412 .jhcc_nclks = __arraycount(jh7100_clocks), 413 }; 414 415 416 static struct jh7100_clk_config jh7110_audclk_config = { 417 .jhcc_name = "Audio", 418 .jhcc_clocks = jh7100_audclk_clocks, 419 .jhcc_nclks = __arraycount(jh7100_audclk_clocks), 420 }; 421 422 static const struct device_compatible_entry compat_data[] = { 423 { .compat = "starfive,jh7100-clkgen", .data = &jh7100_clk_config }, 424 { .compat = "starfive,jh7100-audclk", .data = &jh7110_audclk_config }, 425 DEVICE_COMPAT_EOL 426 }; 427 428 429 static struct clk * 430 jh7100_clkc_fdt_decode(device_t dev, int phandle, const void *data, 431 size_t len) 432 { 433 struct jh71x0_clkc_softc * const sc = device_private(dev); 434 435 if (len != 4) 436 return NULL; 437 438 u_int id = be32dec(data); 439 if (id >= sc->sc_nclks) 440 return NULL; 441 442 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) { 443 printf("Unknown clock %d\n", id); 444 return NULL; 445 } 446 return &sc->sc_clk[id].jcc_clk; 447 } 448 449 static const struct fdtbus_clock_controller_func jh7100_clkc_fdt_funcs = { 450 .decode = jh7100_clkc_fdt_decode 451 }; 452 453 static int 454 jh7100_clkc_match(device_t parent, cfdata_t cf, void *aux) 455 { 456 struct fdt_attach_args * const faa = aux; 457 458 return of_compatible_match(faa->faa_phandle, compat_data); 459 } 460 461 static void 462 jh7100_clkc_attach(device_t parent, device_t self, void *aux) 463 { 464 struct jh71x0_clkc_softc * const sc = device_private(self); 465 struct fdt_attach_args * const faa = aux; 466 const int phandle = faa->faa_phandle; 467 char infomsg[128] = ""; 468 bus_addr_t addr; 469 bus_size_t size; 470 int error; 471 472 error = fdtbus_get_reg(phandle, 0, &addr, &size); 473 if (error) { 474 aprint_error(": couldn't get registers\n"); 475 return; 476 } 477 478 sc->sc_dev = self; 479 sc->sc_phandle = phandle; 480 sc->sc_bst = faa->faa_bst; 481 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 482 if (error) { 483 aprint_error(": couldn't map registers\n"); 484 return; 485 } 486 487 const struct jh7100_clk_config *jhcc = 488 of_compatible_lookup(phandle, compat_data)->data; 489 KASSERT(jhcc != NULL); 490 491 if (jhcc == &jh7100_clk_config) { 492 struct clk * const osclk = fdtbus_clock_get(phandle, "osc_sys"); 493 if (osclk == NULL) { 494 aprint_error(": couldn't get osc_sys\n"); 495 return; 496 } 497 u_int osclk_rate = clk_get_rate(osclk); 498 499 struct clk * const oaclk = fdtbus_clock_get(phandle, "osc_aud"); 500 if (oaclk == NULL) { 501 aprint_error(": couldn't get osc_aud\n"); 502 return; 503 } 504 u_int oaclk_rate = clk_get_rate(oaclk); 505 506 snprintf(infomsg, sizeof(infomsg), "(OSC0 %u Hz, OSC1 %u Hz)", 507 osclk_rate, oaclk_rate); 508 } 509 510 sc->sc_clkdom.name = device_xname(self); 511 sc->sc_clkdom.funcs = &jh71x0_clkc_funcs; 512 sc->sc_clkdom.priv = sc; 513 514 sc->sc_clk = jhcc->jhcc_clocks; 515 sc->sc_nclks = jhcc->jhcc_nclks; 516 for (size_t id = 0; id < sc->sc_nclks; id++) { 517 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) 518 continue; 519 520 sc->sc_clk[id].jcc_clk.domain = &sc->sc_clkdom; 521 clk_attach(&sc->sc_clk[id].jcc_clk); 522 } 523 524 aprint_naive("\n"); 525 aprint_normal(": JH7100 %s clocks %s\n", jhcc->jhcc_name, infomsg); 526 527 for (size_t id = 0; id < sc->sc_nclks; id++) { 528 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) 529 continue; 530 531 struct clk * const clk = &sc->sc_clk[id].jcc_clk; 532 533 aprint_debug_dev(self, "id %zu [%s]: %u Hz\n", id, 534 clk->name ? clk->name : "<none>", clk_get_rate(clk)); 535 } 536 537 fdtbus_register_clock_controller(self, phandle, &jh7100_clkc_fdt_funcs); 538 } 539 540 CFATTACH_DECL_NEW(jh7100_clkc, sizeof(struct jh71x0_clkc_softc), 541 jh7100_clkc_match, jh7100_clkc_attach, NULL, NULL); 542
Indexes created Wed Oct 01 07:09:59 GMT 2025