jh7110_pcie.c revision 1.2.4.2
1 1.2.4.2 perseant /* $NetBSD: jh7110_pcie.c,v 1.2.4.2 2025/08/02 05:56:05 perseant Exp $ */ 2 1.2.4.2 perseant 3 1.2.4.2 perseant /*- 4 1.2.4.2 perseant * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 1.2.4.2 perseant * All rights reserved. 6 1.2.4.2 perseant * 7 1.2.4.2 perseant * This code is derived from software contributed to The NetBSD Foundation 8 1.2.4.2 perseant * by Nick Hudson 9 1.2.4.2 perseant * 10 1.2.4.2 perseant * Redistribution and use in source and binary forms, with or without 11 1.2.4.2 perseant * modification, are permitted provided that the following conditions 12 1.2.4.2 perseant * are met: 13 1.2.4.2 perseant * 1. Redistributions of source code must retain the above copyright 14 1.2.4.2 perseant * notice, this list of conditions and the following disclaimer. 15 1.2.4.2 perseant * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.4.2 perseant * notice, this list of conditions and the following disclaimer in the 17 1.2.4.2 perseant * documentation and/or other materials provided with the distribution. 18 1.2.4.2 perseant * 19 1.2.4.2 perseant * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.4.2 perseant * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.4.2 perseant * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.4.2 perseant * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.4.2 perseant * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.4.2 perseant * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.4.2 perseant * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.4.2 perseant * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.4.2 perseant * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.4.2 perseant * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.4.2 perseant * POSSIBILITY OF SUCH DAMAGE. 30 1.2.4.2 perseant */ 31 1.2.4.2 perseant 32 1.2.4.2 perseant #include <sys/cdefs.h> 33 1.2.4.2 perseant __KERNEL_RCSID(0, "$NetBSD: jh7110_pcie.c,v 1.2.4.2 2025/08/02 05:56:05 perseant Exp $"); 34 1.2.4.2 perseant 35 1.2.4.2 perseant #include <sys/param.h> 36 1.2.4.2 perseant 37 1.2.4.2 perseant #include <sys/bitops.h> 38 1.2.4.2 perseant #include <sys/kmem.h> 39 1.2.4.2 perseant 40 1.2.4.2 perseant #include <dev/fdt/fdtvar.h> 41 1.2.4.2 perseant #include <dev/fdt/syscon.h> 42 1.2.4.2 perseant 43 1.2.4.2 perseant #include <dev/pci/pcivar.h> 44 1.2.4.2 perseant #include <dev/pci/pciconf.h> 45 1.2.4.2 perseant 46 1.2.4.2 perseant #include <riscv/fdt/pcihost_fdtvar.h> 47 1.2.4.2 perseant 48 1.2.4.2 perseant struct jh7110_pcie_irq { 49 1.2.4.2 perseant struct jh7110_pcie_softc * 50 1.2.4.2 perseant jpi_sc; 51 1.2.4.2 perseant void *jpi_arg; 52 1.2.4.2 perseant int (*jpi_fn)(void *); 53 1.2.4.2 perseant int jpi_mpsafe; 54 1.2.4.2 perseant }; 55 1.2.4.2 perseant 56 1.2.4.2 perseant struct jh7110_pcie_softc { 57 1.2.4.2 perseant bus_space_tag_t sc_bst; 58 1.2.4.2 perseant 59 1.2.4.2 perseant struct pcihost_softc sc_phsc; 60 1.2.4.2 perseant 61 1.2.4.2 perseant bus_space_handle_t sc_apb_bsh; 62 1.2.4.2 perseant bus_addr_t sc_apb_addr; 63 1.2.4.2 perseant bus_size_t sc_apb_size; 64 1.2.4.2 perseant 65 1.2.4.2 perseant bus_space_handle_t sc_cfg_bsh; 66 1.2.4.2 perseant bus_addr_t sc_cfg_addr; 67 1.2.4.2 perseant bus_size_t sc_cfg_size; 68 1.2.4.2 perseant 69 1.2.4.2 perseant // syscon 70 1.2.4.2 perseant const struct syscon * sc_syscon; 71 1.2.4.2 perseant bus_size_t sc_stg_base; 72 1.2.4.2 perseant 73 1.2.4.2 perseant struct fdtbus_gpio_pin *sc_perst_gpio; 74 1.2.4.2 perseant 75 1.2.4.2 perseant // # pins 76 1.2.4.2 perseant struct jh7110_pcie_irq *sc_irq[PCI_INTERRUPT_PIN_MAX]; 77 1.2.4.2 perseant }; 78 1.2.4.2 perseant 79 1.2.4.2 perseant #define RD4(sc, reg) \ 80 1.2.4.2 perseant bus_space_read_4((sc)->sc_bst, (sc)->sc_apb_bsh, (reg)) 81 1.2.4.2 perseant #define WR4(sc, reg, val) \ 82 1.2.4.2 perseant bus_space_write_4((sc)->sc_bst, (sc)->sc_apb_bsh, (reg), (val)) 83 1.2.4.2 perseant 84 1.2.4.2 perseant #define SET4(sc, off, mask) \ 85 1.2.4.2 perseant WR4((sc), (off), RD4((sc), (off)) | (mask)) 86 1.2.4.2 perseant #define CLR4(sc, off, mask) \ 87 1.2.4.2 perseant WR4((sc), (off), RD4((sc), (off)) & ~(mask)) 88 1.2.4.2 perseant #define UPD4(sc, off, clr, set) \ 89 1.2.4.2 perseant WR4((sc), (off), (RD4((sc), (off)) & ~(clr)) | (set)) 90 1.2.4.2 perseant 91 1.2.4.2 perseant #define JH7110_PCIE0_CFG_BASE 0x940000000UL 92 1.2.4.2 perseant #define JH7110_PCIE1_CFG_BASE 0x9c0000000UL 93 1.2.4.2 perseant 94 1.2.4.2 perseant /* PLDA register definitions */ 95 1.2.4.2 perseant #define PLDA_GEN_SETTINGS 0x80 96 1.2.4.2 perseant #define PLDA_GEN_RP_ENABLE 1 97 1.2.4.2 perseant #define PLDA_PCI_IDS 0x9c 98 1.2.4.2 perseant #define PLDA_PCI_IDS_REVISION_MASK __BITS( 7, 0) 99 1.2.4.2 perseant #define PLDA_PCI_IDS_CLASSCODE_MASK __BITS(31, 8) 100 1.2.4.2 perseant #define PLDA_MISC 0xb4 101 1.2.4.2 perseant #define PLDA_MISC_PHYFUNC_DISABLE __BIT(15) 102 1.2.4.2 perseant #define PLDA_WINROM 0xfc 103 1.2.4.2 perseant #define PLDA_WINROM_PREF64SUPPORT __BIT(3) 104 1.2.4.2 perseant 105 1.2.4.2 perseant #define PLDA_IMASK_LOCAL 0x180 106 1.2.4.2 perseant #define PLDA_IMASK_INT_INTA __BIT(24) 107 1.2.4.2 perseant #define PLDA_IMASK_INT_INTB __BIT(25) 108 1.2.4.2 perseant #define PLDA_IMASK_INT_INTC __BIT(26) 109 1.2.4.2 perseant #define PLDA_IMASK_INT_INTD __BIT(27) 110 1.2.4.2 perseant #define PLDA_IMASK_INT_INTX __BITS(27, 24) 111 1.2.4.2 perseant #define PLDA_IMASK_INT_MSI __BIT(28) 112 1.2.4.2 perseant #define PLDA_ISTATUS_LOCAL 0x184 113 1.2.4.2 perseant #define PLDA_ISTATUS_INT_INTA __BIT(24) 114 1.2.4.2 perseant #define PLDA_ISTATUS_INT_INTB __BIT(25) 115 1.2.4.2 perseant #define PLDA_ISTATUS_INT_INTC __BIT(26) 116 1.2.4.2 perseant #define PLDA_ISTATUS_INT_INTD __BIT(27) 117 1.2.4.2 perseant #define PLDA_ISTATUS_INT_INTX __BITS(27, 24) 118 1.2.4.2 perseant #define PLDA_ISTATUS_INT_MSI __BIT(28) 119 1.2.4.2 perseant #define PLDA_IMASK_HOST 0x188 120 1.2.4.2 perseant #define PLDA_ISTATUS_HOST 0x18c 121 1.2.4.2 perseant #define PLDA_IMSI_ADDR 0x190 122 1.2.4.2 perseant #define PLDA_ISTATUS_MSI 0x194 123 1.2.4.2 perseant #define PLDA_PMSG_SUPPORT_RX 0x3f0 124 1.2.4.2 perseant #define PLDA_PMSG_LTR_SUPPORT __BIT(2) 125 1.2.4.2 perseant 126 1.2.4.2 perseant /* PCIe Master table init defines */ 127 1.2.4.2 perseant #define PLDA_ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600 128 1.2.4.2 perseant #define PLDA_ATR0_PCIE_ATR_SIZE 0x25 129 1.2.4.2 perseant #define PLDA_ATR0_PCIE_ATR_SIZE_SHIFT 1 130 1.2.4.2 perseant #define PLDA_ATR0_PCIE_WIN0_SRC_ADDR 0x604 131 1.2.4.2 perseant #define PLDA_ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608 132 1.2.4.2 perseant #define PLDA_ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60c 133 1.2.4.2 perseant #define PLDA_ATR0_PCIE_WIN0_TRSL_PARAM 0x610 134 1.2.4.2 perseant 135 1.2.4.2 perseant #define PLDA_ATR_AXI4_SLV0_SRC_ADDR_LO(n) (0x800 + (n) * 0x20) 136 1.2.4.2 perseant #define PLDA_ATR_SIZE_SRC_MASK __BITS(31, 12) 137 1.2.4.2 perseant #define PLDA_ATR_SIZE_MASK __BITS(6, 1) 138 1.2.4.2 perseant #define PLDA_ATR_IMPL __BIT(0) 139 1.2.4.2 perseant #define PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(n) (0x804 + (n) * 0x20) 140 1.2.4.2 perseant #define PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(n) (0x808 + (n) * 0x20) 141 1.2.4.2 perseant #define PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(n) (0x80c + (n) * 0x20) 142 1.2.4.2 perseant #define PLDA_ATR_AXI4_SLV0_TRSL_PARAM(n) (0x810 + (n) * 0x20) 143 1.2.4.2 perseant #define PLDA_TRSL_ID_PCIE_RX_TX 0 144 1.2.4.2 perseant #define PLDA_TRSL_ID_PCIE_CONFIG 1 145 1.2.4.2 perseant 146 1.2.4.2 perseant #define PCIE_FUNC_NUM 4 147 1.2.4.2 perseant 148 1.2.4.2 perseant /* system control */ 149 1.2.4.2 perseant #define STG_SYSCON_PCIE0_BASE 0x0048 150 1.2.4.2 perseant #define STG_SYSCON_PCIE1_BASE 0x01f8 151 1.2.4.2 perseant 152 1.2.4.2 perseant #define STG_SYSCON_AR_OFFSET 0x0078 153 1.2.4.2 perseant #define STG_SYSCON_AXI4_SLVL_AR_MASK __BITS(22, 8) 154 1.2.4.2 perseant #define STG_SYSCON_AXI4_SLVL_PHY_AR_MASK __BITS(20,17) 155 1.2.4.2 perseant #define STG_SYSCON_AXI4_SLVL_PHY_AR(x) \ 156 1.2.4.2 perseant __SHIFTIN((x), STG_SYSCON_AXI4_SLVL_PHY_AR_MASK) 157 1.2.4.2 perseant 158 1.2.4.2 perseant #define STG_SYSCON_AW_OFFSET 0x007c 159 1.2.4.2 perseant #define STG_SYSCON_CLKREQ __BIT(22) 160 1.2.4.2 perseant #define STG_SYSCON_CKREF_SRC_MASK __BITS(19, 18) 161 1.2.4.2 perseant #define STG_SYSCON_AXI4_SLVL_AW_MASK __BITS(14, 0) 162 1.2.4.2 perseant #define STG_SYSCON_AXI4_SLVL_PHY_AW_MASK __BITS(12, 9) 163 1.2.4.2 perseant #define STG_SYSCON_AXI4_SLVL_PHY_AW(x) \ 164 1.2.4.2 perseant __SHIFTIN((x), STG_SYSCON_AXI4_SLVL_PHY_AW_MASK) 165 1.2.4.2 perseant 166 1.2.4.2 perseant #define STG_SYSCON_RP_NEP_OFFSET 0x00e8 167 1.2.4.2 perseant #define STG_SYSCON_K_RP_NEP __BIT(8) 168 1.2.4.2 perseant 169 1.2.4.2 perseant #define STG_SYSCON_LNKSTA_OFFSET 0x0170 170 1.2.4.2 perseant #define DATA_LINK_ACTIVE __BIT(5) 171 1.2.4.2 perseant 172 1.2.4.2 perseant #define ECAM_BUS_MASK __BITS(27, 20) 173 1.2.4.2 perseant #define ECAM_DEV_MASK __BITS(19, 15) 174 1.2.4.2 perseant #define ECAM_FUNC_MASK __BITS(14, 12) 175 1.2.4.2 perseant #define ECAM_OFFSET_MASK __BITS(11, 0) 176 1.2.4.2 perseant 177 1.2.4.2 perseant static int 178 1.2.4.2 perseant jh7110_pcie_bus_maxdevs(void *v, int bus) 179 1.2.4.2 perseant { 180 1.2.4.2 perseant struct pcihost_softc * const phsc = v; 181 1.2.4.2 perseant 182 1.2.4.2 perseant if (bus >= phsc->sc_bus_min || bus <= phsc->sc_bus_max) 183 1.2.4.2 perseant return 1; 184 1.2.4.2 perseant return 0; 185 1.2.4.2 perseant } 186 1.2.4.2 perseant 187 1.2.4.2 perseant static pcitag_t 188 1.2.4.2 perseant jh7110_pcie_make_tag(void *v, int bus, int dev, int fn) 189 1.2.4.2 perseant { 190 1.2.4.2 perseant // struct pcihost_softc * const phsc = v; 191 1.2.4.2 perseant 192 1.2.4.2 perseant /* Return ECAM address. */ 193 1.2.4.2 perseant return 194 1.2.4.2 perseant __SHIFTIN(bus, ECAM_BUS_MASK) | 195 1.2.4.2 perseant __SHIFTIN(dev, ECAM_DEV_MASK) | 196 1.2.4.2 perseant __SHIFTIN(fn, ECAM_FUNC_MASK) | 197 1.2.4.2 perseant 0; 198 1.2.4.2 perseant } 199 1.2.4.2 perseant 200 1.2.4.2 perseant static void 201 1.2.4.2 perseant jh7110_pcie_decompose_tag(void *v, pcitag_t tag, 202 1.2.4.2 perseant int *busp, int *devp, int *fnp) 203 1.2.4.2 perseant { 204 1.2.4.2 perseant // struct pcihost_softc * const phsc = v; 205 1.2.4.2 perseant 206 1.2.4.2 perseant if (busp != NULL) 207 1.2.4.2 perseant *busp = __SHIFTOUT(tag, ECAM_BUS_MASK); 208 1.2.4.2 perseant if (devp != NULL) 209 1.2.4.2 perseant *devp = __SHIFTOUT(tag, ECAM_DEV_MASK); 210 1.2.4.2 perseant if (fnp != NULL) 211 1.2.4.2 perseant *fnp = __SHIFTOUT(tag, ECAM_FUNC_MASK); 212 1.2.4.2 perseant } 213 1.2.4.2 perseant 214 1.2.4.2 perseant static bool 215 1.2.4.2 perseant jh7110_pcie_conf_ok(struct jh7110_pcie_softc *sc, 216 1.2.4.2 perseant int bus, int dev, int fn, int offset) 217 1.2.4.2 perseant { 218 1.2.4.2 perseant 219 1.2.4.2 perseant /* Only one device on root port and the first subordinate port. */ 220 1.2.4.2 perseant if (bus < 2 && dev < 1) 221 1.2.4.2 perseant return true; 222 1.2.4.2 perseant 223 1.2.4.2 perseant return false; 224 1.2.4.2 perseant } 225 1.2.4.2 perseant 226 1.2.4.2 perseant static pcireg_t 227 1.2.4.2 perseant jh7110_pcie_conf_read(void *v, pcitag_t tag, int offset) 228 1.2.4.2 perseant { 229 1.2.4.2 perseant struct pcihost_softc * const phsc = v; 230 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = 231 1.2.4.2 perseant container_of(phsc, struct jh7110_pcie_softc, sc_phsc); 232 1.2.4.2 perseant int bus, dev, fn; 233 1.2.4.2 perseant 234 1.2.4.2 perseant KASSERT(offset >= 0); 235 1.2.4.2 perseant KASSERT(offset < PCI_EXTCONF_SIZE); 236 1.2.4.2 perseant 237 1.2.4.2 perseant jh7110_pcie_decompose_tag(phsc, tag, &bus, &dev, &fn); 238 1.2.4.2 perseant 239 1.2.4.2 perseant if (!jh7110_pcie_conf_ok(sc, bus, dev, fn, offset)) 240 1.2.4.2 perseant return 0xffffffff; 241 1.2.4.2 perseant 242 1.2.4.2 perseant bus_size_t reg = 243 1.2.4.2 perseant __SHIFTIN(bus, ECAM_BUS_MASK) | 244 1.2.4.2 perseant __SHIFTIN(dev, ECAM_DEV_MASK) | 245 1.2.4.2 perseant __SHIFTIN(fn, ECAM_FUNC_MASK) | 246 1.2.4.2 perseant offset; 247 1.2.4.2 perseant 248 1.2.4.2 perseant return bus_space_read_4(sc->sc_bst, sc->sc_cfg_bsh, reg); 249 1.2.4.2 perseant } 250 1.2.4.2 perseant 251 1.2.4.2 perseant static void 252 1.2.4.2 perseant jh7110_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 253 1.2.4.2 perseant { 254 1.2.4.2 perseant struct pcihost_softc * const phsc = v; 255 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = 256 1.2.4.2 perseant container_of(phsc, struct jh7110_pcie_softc, sc_phsc); 257 1.2.4.2 perseant int bus, dev, fn; 258 1.2.4.2 perseant 259 1.2.4.2 perseant KASSERT(offset >= 0); 260 1.2.4.2 perseant KASSERT(offset < PCI_EXTCONF_SIZE); 261 1.2.4.2 perseant 262 1.2.4.2 perseant jh7110_pcie_decompose_tag(phsc, tag, &bus, &dev, &fn); 263 1.2.4.2 perseant 264 1.2.4.2 perseant if (!jh7110_pcie_conf_ok(sc, bus, dev, fn, offset)) 265 1.2.4.2 perseant return; 266 1.2.4.2 perseant 267 1.2.4.2 perseant bus_size_t reg = 268 1.2.4.2 perseant __SHIFTIN(bus, ECAM_BUS_MASK) | 269 1.2.4.2 perseant __SHIFTIN(dev, ECAM_DEV_MASK) | 270 1.2.4.2 perseant __SHIFTIN(fn, ECAM_FUNC_MASK) | 271 1.2.4.2 perseant offset; 272 1.2.4.2 perseant 273 1.2.4.2 perseant bus_space_write_4(sc->sc_bst, sc->sc_cfg_bsh, reg, data); 274 1.2.4.2 perseant } 275 1.2.4.2 perseant 276 1.2.4.2 perseant /* INTx interrupt controller */ 277 1.2.4.2 perseant static void * 278 1.2.4.2 perseant jh7110_pcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 279 1.2.4.2 perseant int (*func)(void *), void *arg, const char *xname) 280 1.2.4.2 perseant { 281 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = device_private(dev); 282 1.2.4.2 perseant const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 283 1.2.4.2 perseant const u_int pin = be32toh(specifier[0]) - 1; 284 1.2.4.2 perseant 285 1.2.4.2 perseant KASSERT((RD4(sc, PLDA_IMASK_LOCAL) & (PLDA_IMASK_INT_INTA << pin)) == 0); 286 1.2.4.2 perseant 287 1.2.4.2 perseant struct jh7110_pcie_irq *jpi = sc->sc_irq[pin]; 288 1.2.4.2 perseant if (jpi == NULL) { 289 1.2.4.2 perseant jpi = kmem_alloc(sizeof(*jpi), KM_SLEEP); 290 1.2.4.2 perseant jpi->jpi_sc = sc; 291 1.2.4.2 perseant jpi->jpi_fn = func; 292 1.2.4.2 perseant jpi->jpi_arg = arg; 293 1.2.4.2 perseant jpi->jpi_mpsafe = mpsafe; 294 1.2.4.2 perseant 295 1.2.4.2 perseant sc->sc_irq[pin] = jpi; 296 1.2.4.2 perseant } else { 297 1.2.4.2 perseant device_printf(dev, "shared interrupts not supported\n"); 298 1.2.4.2 perseant return NULL; 299 1.2.4.2 perseant } 300 1.2.4.2 perseant 301 1.2.4.2 perseant /* Unmask the interrupt. */ 302 1.2.4.2 perseant SET4(sc, PLDA_IMASK_LOCAL, (PLDA_IMASK_INT_INTA << pin)); 303 1.2.4.2 perseant 304 1.2.4.2 perseant return jpi; 305 1.2.4.2 perseant } 306 1.2.4.2 perseant 307 1.2.4.2 perseant 308 1.2.4.2 perseant static void 309 1.2.4.2 perseant jh7110_pcie_intx_disestablish(device_t dev, void *ih) 310 1.2.4.2 perseant { 311 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = device_private(dev); 312 1.2.4.2 perseant struct pcihost_softc * const phsc = &sc->sc_phsc; 313 1.2.4.2 perseant 314 1.2.4.2 perseant device_printf(dev, "%s\n", __func__); 315 1.2.4.2 perseant 316 1.2.4.2 perseant fdtbus_intr_disestablish(phsc->sc_phandle, ih); 317 1.2.4.2 perseant } 318 1.2.4.2 perseant 319 1.2.4.2 perseant static bool 320 1.2.4.2 perseant jh7110_pcie_intx_string(device_t dev, u_int *specifier, char *buf, 321 1.2.4.2 perseant size_t buflen) 322 1.2.4.2 perseant { 323 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = device_private(dev); 324 1.2.4.2 perseant struct pcihost_softc * const phsc = &sc->sc_phsc; 325 1.2.4.2 perseant 326 1.2.4.2 perseant fdtbus_intr_str(phsc->sc_phandle, 0, buf, buflen); 327 1.2.4.2 perseant 328 1.2.4.2 perseant return true; 329 1.2.4.2 perseant } 330 1.2.4.2 perseant 331 1.2.4.2 perseant static int 332 1.2.4.2 perseant jh7110_pcie_intx_intr(struct jh7110_pcie_softc *sc, uint32_t status) 333 1.2.4.2 perseant { 334 1.2.4.2 perseant int handled = 0; 335 1.2.4.2 perseant u_int pin; 336 1.2.4.2 perseant 337 1.2.4.2 perseant CTASSERT(__arraycount(sc->sc_irq) == 4); 338 1.2.4.2 perseant for (pin = 0; pin < __arraycount(sc->sc_irq); pin++) { 339 1.2.4.2 perseant if ((status & (PLDA_IMASK_INT_INTA << pin)) == 0) 340 1.2.4.2 perseant continue; 341 1.2.4.2 perseant 342 1.2.4.2 perseant struct jh7110_pcie_irq *jpi = sc->sc_irq[pin]; 343 1.2.4.2 perseant 344 1.2.4.2 perseant if (jpi == NULL) 345 1.2.4.2 perseant continue; 346 1.2.4.2 perseant 347 1.2.4.2 perseant if (!jpi->jpi_mpsafe) 348 1.2.4.2 perseant KERNEL_LOCK(1, NULL); 349 1.2.4.2 perseant handled |= jpi->jpi_fn(jpi->jpi_arg); 350 1.2.4.2 perseant if (!jpi->jpi_mpsafe) 351 1.2.4.2 perseant KERNEL_UNLOCK_ONE(NULL); 352 1.2.4.2 perseant } 353 1.2.4.2 perseant 354 1.2.4.2 perseant return handled; 355 1.2.4.2 perseant } 356 1.2.4.2 perseant 357 1.2.4.2 perseant 358 1.2.4.2 perseant static int 359 1.2.4.2 perseant jh7110_pcie_intr(void *v) 360 1.2.4.2 perseant { 361 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = v; 362 1.2.4.2 perseant int handled = 0; 363 1.2.4.2 perseant 364 1.2.4.2 perseant uint32_t status = RD4(sc, PLDA_ISTATUS_LOCAL); 365 1.2.4.2 perseant if (status == 0) 366 1.2.4.2 perseant return 0; 367 1.2.4.2 perseant 368 1.2.4.2 perseant if (status & PLDA_ISTATUS_INT_INTX) 369 1.2.4.2 perseant handled |= jh7110_pcie_intx_intr(sc, status); 370 1.2.4.2 perseant 371 1.2.4.2 perseant WR4(sc, PLDA_ISTATUS_LOCAL, status); 372 1.2.4.2 perseant 373 1.2.4.2 perseant return handled; 374 1.2.4.2 perseant } 375 1.2.4.2 perseant 376 1.2.4.2 perseant static struct fdtbus_interrupt_controller_func jh7110_pcie_intxfuncs = { 377 1.2.4.2 perseant .establish = jh7110_pcie_intx_establish, 378 1.2.4.2 perseant .disestablish = jh7110_pcie_intx_disestablish, 379 1.2.4.2 perseant .intrstr = jh7110_pcie_intx_string, 380 1.2.4.2 perseant }; 381 1.2.4.2 perseant 382 1.2.4.2 perseant #define SCRD4(sc, off) syscon_read_4((sc), (off)) 383 1.2.4.2 perseant #define SCWR4(sc, off, val) syscon_write_4((sc), (off), (val)) 384 1.2.4.2 perseant 385 1.2.4.2 perseant #define SCSET4(sc, off, mask) \ 386 1.2.4.2 perseant SCWR4((sc), (off), SCRD4((sc), (off)) | (mask)) 387 1.2.4.2 perseant #define SCCLR4(sc, off, mask) \ 388 1.2.4.2 perseant SCWR4((sc), (off), SCRD4((sc), (off)) & ~(mask)) 389 1.2.4.2 perseant #define SCUPD4(sc, off, clr, set) \ 390 1.2.4.2 perseant SCWR4((sc), (off), (SCRD4((sc), (off)) & ~(clr)) | (set)) 391 1.2.4.2 perseant 392 1.2.4.2 perseant 393 1.2.4.2 perseant static int 394 1.2.4.2 perseant jh7110_pcie_host_init(struct jh7110_pcie_softc *sc) 395 1.2.4.2 perseant { 396 1.2.4.2 perseant struct pcihost_softc * const phsc = &sc->sc_phsc; 397 1.2.4.2 perseant 398 1.2.4.2 perseant syscon_lock(sc->sc_syscon); 399 1.2.4.2 perseant SCSET4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_RP_NEP_OFFSET, 400 1.2.4.2 perseant STG_SYSCON_K_RP_NEP); 401 1.2.4.2 perseant 402 1.2.4.2 perseant SCUPD4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_AW_OFFSET, 403 1.2.4.2 perseant STG_SYSCON_CKREF_SRC_MASK, 404 1.2.4.2 perseant __SHIFTIN(2, STG_SYSCON_CKREF_SRC_MASK)); 405 1.2.4.2 perseant 406 1.2.4.2 perseant SCSET4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_AW_OFFSET, 407 1.2.4.2 perseant STG_SYSCON_CLKREQ); 408 1.2.4.2 perseant 409 1.2.4.2 perseant /* enable clocks */ 410 1.2.4.2 perseant struct clk *clk; 411 1.2.4.2 perseant fdtbus_clock_assign(phsc->sc_phandle); 412 1.2.4.2 perseant for (u_int c = 0; 413 1.2.4.2 perseant (clk = fdtbus_clock_get_index(phsc->sc_phandle, c)) != NULL; 414 1.2.4.2 perseant c++) { 415 1.2.4.2 perseant if (clk_enable(clk) != 0) { 416 1.2.4.2 perseant aprint_error_dev(phsc->sc_dev, 417 1.2.4.2 perseant "couldn't enable clock #%d\n", c); 418 1.2.4.2 perseant return ENXIO; 419 1.2.4.2 perseant } 420 1.2.4.2 perseant } 421 1.2.4.2 perseant /* de-assert resets */ 422 1.2.4.2 perseant struct fdtbus_reset *rst; 423 1.2.4.2 perseant for (u_int r = 0; 424 1.2.4.2 perseant (rst = fdtbus_reset_get_index(phsc->sc_phandle, r)) != NULL; 425 1.2.4.2 perseant r++) { 426 1.2.4.2 perseant if (fdtbus_reset_deassert(rst) != 0) { 427 1.2.4.2 perseant aprint_error_dev(phsc->sc_dev, 428 1.2.4.2 perseant "couldn't de-assert reset #%d\n", r); 429 1.2.4.2 perseant return ENXIO; 430 1.2.4.2 perseant } 431 1.2.4.2 perseant } 432 1.2.4.2 perseant 433 1.2.4.2 perseant fdtbus_gpio_write(sc->sc_perst_gpio, 1); 434 1.2.4.2 perseant 435 1.2.4.2 perseant /* Disable additional functions. */ 436 1.2.4.2 perseant for (u_int i = 1; i < PCIE_FUNC_NUM; i++) { 437 1.2.4.2 perseant 438 1.2.4.2 perseant SCUPD4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_AR_OFFSET, 439 1.2.4.2 perseant STG_SYSCON_AXI4_SLVL_AR_MASK, 440 1.2.4.2 perseant __SHIFTIN(i, STG_SYSCON_AXI4_SLVL_PHY_AR_MASK)); 441 1.2.4.2 perseant 442 1.2.4.2 perseant SCUPD4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_AW_OFFSET, 443 1.2.4.2 perseant STG_SYSCON_AXI4_SLVL_AW_MASK, 444 1.2.4.2 perseant __SHIFTIN(i, STG_SYSCON_AXI4_SLVL_PHY_AW_MASK)); 445 1.2.4.2 perseant 446 1.2.4.2 perseant SET4(sc, PLDA_MISC, PLDA_MISC_PHYFUNC_DISABLE); 447 1.2.4.2 perseant } 448 1.2.4.2 perseant 449 1.2.4.2 perseant SCCLR4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_AR_OFFSET, 450 1.2.4.2 perseant STG_SYSCON_AXI4_SLVL_AR_MASK); 451 1.2.4.2 perseant 452 1.2.4.2 perseant SCCLR4(sc->sc_syscon, sc->sc_stg_base + STG_SYSCON_AW_OFFSET, 453 1.2.4.2 perseant STG_SYSCON_AXI4_SLVL_AW_MASK); 454 1.2.4.2 perseant 455 1.2.4.2 perseant /* Configure controller as root port. */ 456 1.2.4.2 perseant UPD4(sc, PLDA_GEN_SETTINGS, PLDA_GEN_RP_ENABLE, PLDA_GEN_RP_ENABLE); 457 1.2.4.2 perseant uint64_t base_addr = 0; 458 1.2.4.2 perseant 459 1.2.4.2 perseant #define CONFIG_SPACE_ADDR_OFFSET 0x1000 460 1.2.4.2 perseant 461 1.2.4.2 perseant SET4(sc, CONFIG_SPACE_ADDR_OFFSET + 0x10, BUS_ADDR_LO32(base_addr)); 462 1.2.4.2 perseant SET4(sc, CONFIG_SPACE_ADDR_OFFSET + 0x14, BUS_ADDR_HI32(base_addr)); 463 1.2.4.2 perseant 464 1.2.4.2 perseant /* Configure as PCI bridge. */ 465 1.2.4.2 perseant UPD4(sc, PLDA_PCI_IDS, 466 1.2.4.2 perseant PLDA_PCI_IDS_CLASSCODE_MASK, 467 1.2.4.2 perseant PCI_CLASS_CODE(PCI_CLASS_BRIDGE, 468 1.2.4.2 perseant PCI_SUBCLASS_BRIDGE_PCI, 469 1.2.4.2 perseant PCI_INTERFACE_BRIDGE_PCI_PCI)); 470 1.2.4.2 perseant 471 1.2.4.2 perseant /* Enable prefetchable memory windows. */ 472 1.2.4.2 perseant SET4(sc, PLDA_WINROM, PLDA_WINROM_PREF64SUPPORT); 473 1.2.4.2 perseant 474 1.2.4.2 perseant /* Disable LTR message forwarding. */ 475 1.2.4.2 perseant CLR4(sc, PLDA_PMSG_SUPPORT_RX, PLDA_PMSG_LTR_SUPPORT); 476 1.2.4.2 perseant 477 1.2.4.2 perseant /* 478 1.2.4.2 perseant * PERST# must remain asserted for at least 100us after the 479 1.2.4.2 perseant * reference clock becomes stable. But also has to remain 480 1.2.4.2 perseant * active at least 100ms after power up. Since we may have 481 1.2.4.2 perseant * just powered on the device, play it safe and use 100ms. 482 1.2.4.2 perseant */ 483 1.2.4.2 perseant delay(100 * 1000); 484 1.2.4.2 perseant 485 1.2.4.2 perseant /* Deassert PERST#. */ 486 1.2.4.2 perseant fdtbus_gpio_write(sc->sc_perst_gpio, 0); 487 1.2.4.2 perseant 488 1.2.4.2 perseant /* Wait for link to come up. */ 489 1.2.4.2 perseant uint32_t reg; 490 1.2.4.2 perseant for (int timo = 100; timo > 0; timo--) { 491 1.2.4.2 perseant reg = SCRD4(sc->sc_syscon, 492 1.2.4.2 perseant sc->sc_stg_base + STG_SYSCON_LNKSTA_OFFSET); 493 1.2.4.2 perseant if (reg & DATA_LINK_ACTIVE) 494 1.2.4.2 perseant break; 495 1.2.4.2 perseant delay(1000); 496 1.2.4.2 perseant } 497 1.2.4.2 perseant 498 1.2.4.2 perseant syscon_unlock(sc->sc_syscon); 499 1.2.4.2 perseant 500 1.2.4.2 perseant if ((reg & DATA_LINK_ACTIVE) == 0) { 501 1.2.4.2 perseant aprint_error_dev(phsc->sc_dev, "link not up\n"); 502 1.2.4.2 perseant return ENXIO; 503 1.2.4.2 perseant } 504 1.2.4.2 perseant 505 1.2.4.2 perseant return 0; 506 1.2.4.2 perseant } 507 1.2.4.2 perseant 508 1.2.4.2 perseant static int 509 1.2.4.2 perseant jh7110_pcie_atr_init(struct jh7110_pcie_softc *sc) 510 1.2.4.2 perseant { 511 1.2.4.2 perseant const uint32_t *ranges; 512 1.2.4.2 perseant bus_addr_t phyaddr; // PADDR? 513 1.2.4.2 perseant bus_addr_t pciaddr; 514 1.2.4.2 perseant bus_size_t size; 515 1.2.4.2 perseant 516 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_LO(0), 517 1.2.4.2 perseant PLDA_ATR_IMPL | 518 1.2.4.2 perseant __SHIFTIN(ilog2(sc->sc_cfg_size) - 1, PLDA_ATR_SIZE_MASK) | 519 1.2.4.2 perseant BUS_ADDR_LO32(sc->sc_cfg_addr)); 520 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(0), BUS_ADDR_HI32(sc->sc_cfg_addr)); 521 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(0), 0); 522 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(0), 0); 523 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_PARAM(0), PLDA_TRSL_ID_PCIE_CONFIG); 524 1.2.4.2 perseant 525 1.2.4.2 perseant struct pcihost_softc * const phsc = &sc->sc_phsc; 526 1.2.4.2 perseant int ranges_len; 527 1.2.4.2 perseant ranges = fdtbus_get_prop(phsc->sc_phandle, "ranges", &ranges_len); 528 1.2.4.2 perseant if (ranges == NULL) { 529 1.2.4.2 perseant aprint_error_dev(phsc->sc_dev, 530 1.2.4.2 perseant "couldn't find 'ranges' property\n"); 531 1.2.4.2 perseant return ENXIO; 532 1.2.4.2 perseant } 533 1.2.4.2 perseant const int ranges_cells = ranges_len / sizeof(uint32_t); 534 1.2.4.2 perseant 535 1.2.4.2 perseant for (u_int i = 0, n = 1; i < ranges_cells && n < 8; i += 7, n++) { 536 1.2.4.2 perseant pciaddr = 537 1.2.4.2 perseant __SHIFTIN(be32toh(ranges[i + 1]), __BITS(63, 32)) | 538 1.2.4.2 perseant __SHIFTIN(be32toh(ranges[i + 2]), __BITS(31, 0)); 539 1.2.4.2 perseant phyaddr = 540 1.2.4.2 perseant __SHIFTIN(be32toh(ranges[i + 3]), __BITS(63, 32)) | 541 1.2.4.2 perseant __SHIFTIN(be32toh(ranges[i + 4]), __BITS(31, 0)); 542 1.2.4.2 perseant size = be32toh(ranges[i + 6]); 543 1.2.4.2 perseant 544 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_LO(n), 545 1.2.4.2 perseant PLDA_ATR_IMPL | 546 1.2.4.2 perseant __SHIFTIN(ilog2(size) /* - 1 */, PLDA_ATR_SIZE_MASK) | 547 1.2.4.2 perseant BUS_ADDR_LO32(phyaddr)); 548 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(n), BUS_ADDR_HI32(phyaddr)); 549 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(n), BUS_ADDR_LO32(pciaddr)); 550 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(n), BUS_ADDR_HI32(pciaddr)); 551 1.2.4.2 perseant WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_PARAM(n), PLDA_TRSL_ID_PCIE_RX_TX); 552 1.2.4.2 perseant } 553 1.2.4.2 perseant 554 1.2.4.2 perseant uint32_t val; 555 1.2.4.2 perseant val = RD4(sc, PLDA_ATR0_PCIE_WIN0_SRCADDR_PARAM); 556 1.2.4.2 perseant val |= (PLDA_ATR0_PCIE_ATR_SIZE << PLDA_ATR0_PCIE_ATR_SIZE_SHIFT); 557 1.2.4.2 perseant WR4(sc, PLDA_ATR0_PCIE_WIN0_SRCADDR_PARAM, val); 558 1.2.4.2 perseant WR4(sc, PLDA_ATR0_PCIE_WIN0_SRC_ADDR, 0); 559 1.2.4.2 perseant 560 1.2.4.2 perseant return 0; 561 1.2.4.2 perseant } 562 1.2.4.2 perseant 563 1.2.4.2 perseant /* Compat string(s) */ 564 1.2.4.2 perseant static const struct device_compatible_entry compat_data[] = { 565 1.2.4.2 perseant { .compat = "starfive,jh7110-pcie" }, 566 1.2.4.2 perseant DEVICE_COMPAT_EOL 567 1.2.4.2 perseant }; 568 1.2.4.2 perseant 569 1.2.4.2 perseant 570 1.2.4.2 perseant static int 571 1.2.4.2 perseant jh7110_pcie_match(device_t parent, cfdata_t cf, void *aux) 572 1.2.4.2 perseant { 573 1.2.4.2 perseant struct fdt_attach_args * const faa = aux; 574 1.2.4.2 perseant 575 1.2.4.2 perseant return of_compatible_match(faa->faa_phandle, compat_data); 576 1.2.4.2 perseant } 577 1.2.4.2 perseant 578 1.2.4.2 perseant static void 579 1.2.4.2 perseant jh7110_pcie_attach(device_t parent, device_t self, void *aux) 580 1.2.4.2 perseant { 581 1.2.4.2 perseant struct jh7110_pcie_softc * const sc = device_private(self); 582 1.2.4.2 perseant struct pcihost_softc * const phsc = &sc->sc_phsc; 583 1.2.4.2 perseant struct fdt_attach_args * const faa = aux; 584 1.2.4.2 perseant const int phandle = faa->faa_phandle; 585 1.2.4.2 perseant int error; 586 1.2.4.2 perseant 587 1.2.4.2 perseant sc->sc_bst = faa->faa_bst; 588 1.2.4.2 perseant 589 1.2.4.2 perseant phsc->sc_dev = self; 590 1.2.4.2 perseant phsc->sc_bst = faa->faa_bst; 591 1.2.4.2 perseant phsc->sc_pci_bst = faa->faa_bst; 592 1.2.4.2 perseant phsc->sc_dmat = faa->faa_dmat; 593 1.2.4.2 perseant phsc->sc_phandle = faa->faa_phandle; 594 1.2.4.2 perseant 595 1.2.4.2 perseant /* Handle old and new binding names. */ 596 1.2.4.2 perseant if (fdtbus_get_reg_byname(phandle, "apb", 597 1.2.4.2 perseant &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 598 1.2.4.2 perseant aprint_error(": couldn't get apb registers\n"); 599 1.2.4.2 perseant return; 600 1.2.4.2 perseant } 601 1.2.4.2 perseant if (fdtbus_get_reg_byname(phandle, "cfg", 602 1.2.4.2 perseant &sc->sc_cfg_addr, &sc->sc_cfg_size) != 0) { 603 1.2.4.2 perseant aprint_error(": couldn't get cfg registers\n"); 604 1.2.4.2 perseant return; 605 1.2.4.2 perseant } 606 1.2.4.2 perseant 607 1.2.4.2 perseant const int mapflags = 0 /*BUS_SPACE_MAP_NONPOSTED*/; 608 1.2.4.2 perseant error = bus_space_map(sc->sc_bst, sc->sc_apb_addr, 609 1.2.4.2 perseant sc->sc_apb_size, mapflags, &sc->sc_apb_bsh); 610 1.2.4.2 perseant if (error) { 611 1.2.4.2 perseant aprint_error(": can't map APB registers\n"); 612 1.2.4.2 perseant return; 613 1.2.4.2 perseant } 614 1.2.4.2 perseant error = bus_space_map(sc->sc_bst, sc->sc_cfg_addr, 615 1.2.4.2 perseant sc->sc_cfg_size, mapflags, &sc->sc_cfg_bsh); 616 1.2.4.2 perseant if (error) { 617 1.2.4.2 perseant aprint_error(": can't map CFG registers\n"); 618 1.2.4.2 perseant return; 619 1.2.4.2 perseant } 620 1.2.4.2 perseant int len; 621 1.2.4.2 perseant const char *stgsyscon = "starfive,stg-syscon"; 622 1.2.4.2 perseant const u_int *stgsyscon_data = 623 1.2.4.2 perseant fdtbus_get_prop(phandle, stgsyscon, &len); 624 1.2.4.2 perseant if (stgsyscon_data == NULL) { 625 1.2.4.2 perseant aprint_error(": couldn't get '%s' property\n", stgsyscon); 626 1.2.4.2 perseant return; 627 1.2.4.2 perseant } 628 1.2.4.2 perseant 629 1.2.4.2 perseant if (len != 1 * sizeof(uint32_t)) { 630 1.2.4.2 perseant aprint_error(": incorrect '%s' data (len = %u)\n", stgsyscon, 631 1.2.4.2 perseant len); 632 1.2.4.2 perseant return; 633 1.2.4.2 perseant } 634 1.2.4.2 perseant int syscon_phandle = 635 1.2.4.2 perseant fdtbus_get_phandle_from_native(be32dec(&stgsyscon_data[0])); 636 1.2.4.2 perseant 637 1.2.4.2 perseant sc->sc_syscon = fdtbus_syscon_lookup(syscon_phandle); 638 1.2.4.2 perseant if (sc->sc_syscon == NULL) { 639 1.2.4.2 perseant aprint_error(": couldn't get '%s' (%d)\n", stgsyscon, 640 1.2.4.2 perseant syscon_phandle); 641 1.2.4.2 perseant return; 642 1.2.4.2 perseant } 643 1.2.4.2 perseant 644 1.2.4.2 perseant sc->sc_perst_gpio = fdtbus_gpio_acquire(phandle, 645 1.2.4.2 perseant "perst-gpios", GPIO_PIN_OUTPUT); 646 1.2.4.2 perseant if (sc->sc_perst_gpio == NULL) { 647 1.2.4.2 perseant aprint_error(": couldn't get 'perst-gpios'"); 648 1.2.4.2 perseant return; 649 1.2.4.2 perseant } 650 1.2.4.2 perseant 651 1.2.4.2 perseant switch (sc->sc_cfg_addr) { 652 1.2.4.2 perseant case JH7110_PCIE0_CFG_BASE: 653 1.2.4.2 perseant sc->sc_stg_base = STG_SYSCON_PCIE0_BASE; 654 1.2.4.2 perseant break; 655 1.2.4.2 perseant case JH7110_PCIE1_CFG_BASE: 656 1.2.4.2 perseant sc->sc_stg_base = STG_SYSCON_PCIE1_BASE; 657 1.2.4.2 perseant break; 658 1.2.4.2 perseant default: 659 1.2.4.2 perseant aprint_error(": unknown controller at 0x%lx\n", 660 1.2.4.2 perseant sc->sc_cfg_addr); 661 1.2.4.2 perseant return; 662 1.2.4.2 perseant } 663 1.2.4.2 perseant 664 1.2.4.2 perseant aprint_naive("\n"); 665 1.2.4.2 perseant aprint_normal(": PCIe\n"); 666 1.2.4.2 perseant 667 1.2.4.2 perseant error = jh7110_pcie_host_init(sc); 668 1.2.4.2 perseant if (error) { 669 1.2.4.2 perseant /* error already printed */ 670 1.2.4.2 perseant return; 671 1.2.4.2 perseant } 672 1.2.4.2 perseant 673 1.2.4.2 perseant /* Configure Address Translation. */ 674 1.2.4.2 perseant error = jh7110_pcie_atr_init(sc); 675 1.2.4.2 perseant if (error) { 676 1.2.4.2 perseant 677 1.2.4.2 perseant } 678 1.2.4.2 perseant 679 1.2.4.2 perseant /* Mask and acknowledge all interrupts. */ 680 1.2.4.2 perseant WR4(sc, PLDA_IMASK_LOCAL, 0); 681 1.2.4.2 perseant WR4(sc, PLDA_ISTATUS_LOCAL, 0xffffffff); 682 1.2.4.2 perseant 683 1.2.4.2 perseant char intrstr[128]; 684 1.2.4.2 perseant if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 685 1.2.4.2 perseant aprint_error(": failed to decode interrupt\n"); 686 1.2.4.2 perseant return; 687 1.2.4.2 perseant } 688 1.2.4.2 perseant void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 689 1.2.4.2 perseant FDT_INTR_MPSAFE, jh7110_pcie_intr, sc, device_xname(self)); 690 1.2.4.2 perseant if (ih == NULL) { 691 1.2.4.2 perseant aprint_error_dev(self, "failed to establish interrupt on %s\n", 692 1.2.4.2 perseant intrstr); 693 1.2.4.2 perseant // XXXNH unwind 694 1.2.4.2 perseant return; 695 1.2.4.2 perseant } 696 1.2.4.2 perseant aprint_normal_dev(self, "interrupting on %s\n", intrstr); 697 1.2.4.2 perseant 698 1.2.4.2 perseant fdtbus_register_interrupt_controller(self, 699 1.2.4.2 perseant OF_child(phsc->sc_phandle), &jh7110_pcie_intxfuncs); 700 1.2.4.2 perseant 701 1.2.4.2 perseant phsc->sc_type = PCIHOST_ECAM; 702 1.2.4.2 perseant pcihost_init(&phsc->sc_pc, phsc); 703 1.2.4.2 perseant 704 1.2.4.2 perseant phsc->sc_pc.pc_bus_maxdevs = jh7110_pcie_bus_maxdevs; 705 1.2.4.2 perseant phsc->sc_pc.pc_make_tag = jh7110_pcie_make_tag; 706 1.2.4.2 perseant phsc->sc_pc.pc_decompose_tag = jh7110_pcie_decompose_tag; 707 1.2.4.2 perseant phsc->sc_pc.pc_conf_read = jh7110_pcie_conf_read; 708 1.2.4.2 perseant phsc->sc_pc.pc_conf_write = jh7110_pcie_conf_write; 709 1.2.4.2 perseant 710 1.2.4.2 perseant pcihost_init2(phsc); 711 1.2.4.2 perseant } 712 1.2.4.2 perseant 713 1.2.4.2 perseant CFATTACH_DECL_NEW(jh7110_pcie, sizeof(struct jh7110_pcie_softc), 714 1.2.4.2 perseant jh7110_pcie_match, jh7110_pcie_attach, NULL, NULL); 715
Indexes created Sat Oct 25 07:10:08 GMT 2025