jh7110_pinctrl.c revision 1.1
1 /* $NetBSD: jh7110_pinctrl.c,v 1.1 2024/11/11 19:23:18 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: jh7110_pinctrl.c,v 1.1 2024/11/11 19:23:18 skrll Exp $"); 34 35 #include <sys/param.h> 36 37 #include <sys/kmem.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 struct jh7110_pinctrl_softc; 42 struct jh7110_pinctrl_data { 43 u_int jpd_npins; 44 u_int jpd_ngpios; 45 46 bus_size_t jpd_dout; 47 uint32_t jpd_dout_mask; 48 bus_size_t jpd_doen; 49 uint32_t jpd_doen_mask; 50 bus_size_t jpd_gpi; 51 uint32_t jpd_gpi_mask; 52 bus_size_t jpd_gin; 53 bus_size_t jpd_gpioin; 54 }; 55 56 struct jh7110_pinctrl_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_bst; 59 bus_space_handle_t sc_bsh; 60 int sc_phandle; 61 62 kmutex_t sc_lock; 63 64 const struct jh7110_pinctrl_data * 65 sc_jpd; 66 }; 67 68 struct jh7110_pinctrl_gpio_pin { 69 struct jh7110_pinctrl_softc *pin_sc; 70 u_int pin_no; 71 bool pin_actlo; 72 }; 73 74 75 // https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_iomux_cfg.html 76 77 /* SYS registers */ 78 #define JH7110_SYS_DOEN 0x0000 79 #define JH7110_SYS_DOUT 0x0040 80 #define JH7110_SYS_GPI 0x0080 81 #define JH7110_SYS_GPIOIN 0x0118 82 83 #define JH7110_SYS_NGPIO 64 84 #define JH7110_SYS_NPIN 96 85 86 /* AON registers */ 87 #define JH7110_AON_DOEN 0x0000 88 #define JH7110_AON_DOUT 0x0004 89 #define JH7110_AON_GPI 0x0008 90 #define JH7110_AON_GPIOIN 0x002c 91 92 #define JH7110_AON_NGPIO 4 93 #define JH7110_AON_NPIN 20 94 95 // XXXNH rename 96 #define GPOUT_LOW 0 97 #define GPOUT_HIGH 1 98 99 #define GPI_NONE 0xff 100 101 102 #define RD4(sc, reg) \ 103 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 104 #define WR4(sc, reg, val) \ 105 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 106 107 /* pad control bits */ 108 #define JH7110_PADCFG_IE __BIT(0) 109 #define JH7110_PADCFG_DS_MASK __BITS(1, 2) 110 #define JH7110_PADCFG_DS_2MA __SHIFTIN(0, JH7110_PADCFG_DS_MASK) 111 #define JH7110_PADCFG_DS_4MA __SHIFTIN(1, JH7110_PADCFG_DS_MASK) 112 #define JH7110_PADCFG_DS_8MA __SHIFTIN(2, JH7110_PADCFG_DS_MASK) 113 #define JH7110_PADCFG_DS_12MA __SHIFTIN(3, JH7110_PADCFG_DS_MASK) 114 #define JH7110_PADCFG_PU __BIT(3) 115 #define JH7110_PADCFG_PD __BIT(4) 116 #define JH7110_PADCFG_BIAS_MASK (JH7110_PADCFG_PD | JH7110_PADCFG_PU) 117 #define JH7110_PADCFG_SLEW __BIT(5) 118 #define JH7110_PADCFG_SMT __BIT(6) 119 #define JH7110_PADCFG_POS __BIT(7) 120 121 /* SYS pins */ 122 #define JH7110_SYS_PAD_GPIO0 0 123 #define JH7110_SYS_PAD_GPIO1 1 124 #define JH7110_SYS_PAD_GPIO2 2 125 #define JH7110_SYS_PAD_GPIO3 3 126 #define JH7110_SYS_PAD_GPIO4 4 127 #define JH7110_SYS_PAD_GPIO5 5 128 #define JH7110_SYS_PAD_GPIO6 6 129 #define JH7110_SYS_PAD_GPIO7 7 130 #define JH7110_SYS_PAD_GPIO8 8 131 #define JH7110_SYS_PAD_GPIO9 9 132 #define JH7110_SYS_PAD_GPIO10 10 133 #define JH7110_SYS_PAD_GPIO11 11 134 #define JH7110_SYS_PAD_GPIO12 12 135 #define JH7110_SYS_PAD_GPIO13 13 136 #define JH7110_SYS_PAD_GPIO14 14 137 #define JH7110_SYS_PAD_GPIO15 15 138 #define JH7110_SYS_PAD_GPIO16 16 139 #define JH7110_SYS_PAD_GPIO17 17 140 #define JH7110_SYS_PAD_GPIO18 18 141 #define JH7110_SYS_PAD_GPIO19 19 142 #define JH7110_SYS_PAD_GPIO20 20 143 #define JH7110_SYS_PAD_GPIO21 21 144 #define JH7110_SYS_PAD_GPIO22 22 145 #define JH7110_SYS_PAD_GPIO23 23 146 #define JH7110_SYS_PAD_GPIO24 24 147 #define JH7110_SYS_PAD_GPIO25 25 148 #define JH7110_SYS_PAD_GPIO26 26 149 #define JH7110_SYS_PAD_GPIO27 27 150 #define JH7110_SYS_PAD_GPIO28 28 151 #define JH7110_SYS_PAD_GPIO29 29 152 #define JH7110_SYS_PAD_GPIO30 30 153 #define JH7110_SYS_PAD_GPIO31 31 154 #define JH7110_SYS_PAD_GPIO32 32 155 #define JH7110_SYS_PAD_GPIO33 33 156 #define JH7110_SYS_PAD_GPIO34 34 157 #define JH7110_SYS_PAD_GPIO35 35 158 #define JH7110_SYS_PAD_GPIO36 36 159 #define JH7110_SYS_PAD_GPIO37 37 160 #define JH7110_SYS_PAD_GPIO38 38 161 #define JH7110_SYS_PAD_GPIO39 39 162 #define JH7110_SYS_PAD_GPIO40 40 163 #define JH7110_SYS_PAD_GPIO41 41 164 #define JH7110_SYS_PAD_GPIO42 42 165 #define JH7110_SYS_PAD_GPIO43 43 166 #define JH7110_SYS_PAD_GPIO44 44 167 #define JH7110_SYS_PAD_GPIO45 45 168 #define JH7110_SYS_PAD_GPIO46 46 169 #define JH7110_SYS_PAD_GPIO47 47 170 #define JH7110_SYS_PAD_GPIO48 48 171 #define JH7110_SYS_PAD_GPIO49 49 172 #define JH7110_SYS_PAD_GPIO50 50 173 #define JH7110_SYS_PAD_GPIO51 51 174 #define JH7110_SYS_PAD_GPIO52 52 175 #define JH7110_SYS_PAD_GPIO53 53 176 #define JH7110_SYS_PAD_GPIO54 54 177 #define JH7110_SYS_PAD_GPIO55 55 178 #define JH7110_SYS_PAD_GPIO56 56 179 #define JH7110_SYS_PAD_GPIO57 57 180 #define JH7110_SYS_PAD_GPIO58 58 181 #define JH7110_SYS_PAD_GPIO59 59 182 #define JH7110_SYS_PAD_GPIO60 60 183 #define JH7110_SYS_PAD_GPIO61 61 184 #define JH7110_SYS_PAD_GPIO62 62 185 #define JH7110_SYS_PAD_GPIO63 63 186 #define JH7110_SYS_PAD_SD0_CLK 64 187 #define JH7110_SYS_PAD_SD0_CMD 65 188 #define JH7110_SYS_PAD_SD0_DATA0 66 189 #define JH7110_SYS_PAD_SD0_DATA1 67 190 #define JH7110_SYS_PAD_SD0_DATA2 68 191 #define JH7110_SYS_PAD_SD0_DATA3 69 192 #define JH7110_SYS_PAD_SD0_DATA4 70 193 #define JH7110_SYS_PAD_SD0_DATA5 71 194 #define JH7110_SYS_PAD_SD0_DATA6 72 195 #define JH7110_SYS_PAD_SD0_DATA7 73 196 #define JH7110_SYS_PAD_SD0_STRB 74 197 #define JH7110_SYS_PAD_GMAC1_MDC 75 198 #define JH7110_SYS_PAD_GMAC1_MDIO 76 199 #define JH7110_SYS_PAD_GMAC1_RXD0 77 200 #define JH7110_SYS_PAD_GMAC1_RXD1 78 201 #define JH7110_SYS_PAD_GMAC1_RXD2 79 202 #define JH7110_SYS_PAD_GMAC1_RXD3 80 203 #define JH7110_SYS_PAD_GMAC1_RXDV 81 204 #define JH7110_SYS_PAD_GMAC1_RXC 82 205 #define JH7110_SYS_PAD_GMAC1_TXD0 83 206 #define JH7110_SYS_PAD_GMAC1_TXD1 84 207 #define JH7110_SYS_PAD_GMAC1_TXD2 85 208 #define JH7110_SYS_PAD_GMAC1_TXD3 86 209 #define JH7110_SYS_PAD_GMAC1_TXEN 87 210 #define JH7110_SYS_PAD_GMAC1_TXC 88 211 #define JH7110_SYS_PAD_QSPI_SCLK 89 212 #define JH7110_SYS_PAD_QSPI_CS0 90 213 #define JH7110_SYS_PAD_QSPI_DATA0 91 214 #define JH7110_SYS_PAD_QSPI_DATA1 92 215 #define JH7110_SYS_PAD_QSPI_DATA2 93 216 #define JH7110_SYS_PAD_QSPI_DATA3 94 217 218 struct jh7110_func_sel { 219 uint16_t jfs_funcreg; 220 uint16_t jfs_max; 221 uint32_t jfs_mask; 222 }; 223 224 #define JH7110_FS(_reg, _mask, _max) \ 225 { \ 226 .jfs_funcreg = (_reg), \ 227 .jfs_max = (_max), \ 228 .jfs_mask = (_mask), \ 229 } 230 231 // https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_iomux_cfg.html#sys_iomux_cfg__section_fw2_v3b_xsb 232 static const struct jh7110_func_sel jh7110_sys_func_sel[] = { 233 [JH7110_SYS_PAD_GMAC1_RXC] = JH7110_FS(0x29c, __BITS( 1, 0), 1), 234 [JH7110_SYS_PAD_GPIO10] = JH7110_FS(0x29c, __BITS( 4, 2), 3), 235 [JH7110_SYS_PAD_GPIO11] = JH7110_FS(0x29c, __BITS( 7, 5), 3), 236 [JH7110_SYS_PAD_GPIO12] = JH7110_FS(0x29c, __BITS(10, 8), 3), 237 [JH7110_SYS_PAD_GPIO13] = JH7110_FS(0x29c, __BITS(13,11), 3), 238 [JH7110_SYS_PAD_GPIO14] = JH7110_FS(0x29c, __BITS(16,14), 3), 239 [JH7110_SYS_PAD_GPIO15] = JH7110_FS(0x29c, __BITS(19,17), 3), 240 [JH7110_SYS_PAD_GPIO16] = JH7110_FS(0x29c, __BITS(22,20), 3), 241 [JH7110_SYS_PAD_GPIO17] = JH7110_FS(0x29c, __BITS(25,23), 3), 242 [JH7110_SYS_PAD_GPIO18] = JH7110_FS(0x29c, __BITS(28,26), 3), 243 [JH7110_SYS_PAD_GPIO19] = JH7110_FS(0x29c, __BITS(31,29), 3), 244 245 [JH7110_SYS_PAD_GPIO20] = JH7110_FS(0x2a0, __BITS( 2, 0), 3), 246 [JH7110_SYS_PAD_GPIO21] = JH7110_FS(0x2a0, __BITS( 5, 3), 3), 247 [JH7110_SYS_PAD_GPIO22] = JH7110_FS(0x2a0, __BITS( 8, 6), 3), 248 [JH7110_SYS_PAD_GPIO23] = JH7110_FS(0x2a0, __BITS(11, 9), 3), 249 [JH7110_SYS_PAD_GPIO24] = JH7110_FS(0x2a0, __BITS(14,12), 3), 250 [JH7110_SYS_PAD_GPIO25] = JH7110_FS(0x2a0, __BITS(17,15), 3), 251 [JH7110_SYS_PAD_GPIO26] = JH7110_FS(0x2a0, __BITS(20,18), 3), 252 [JH7110_SYS_PAD_GPIO27] = JH7110_FS(0x2a0, __BITS(23,21), 3), 253 [JH7110_SYS_PAD_GPIO28] = JH7110_FS(0x2a0, __BITS(26,24), 3), 254 [JH7110_SYS_PAD_GPIO29] = JH7110_FS(0x2a0, __BITS(29,27), 3), 255 256 [JH7110_SYS_PAD_GPIO30] = JH7110_FS(0x2a4, __BITS( 2, 0), 3), 257 [JH7110_SYS_PAD_GPIO31] = JH7110_FS(0x2a4, __BITS( 5, 3), 3), 258 [JH7110_SYS_PAD_GPIO32] = JH7110_FS(0x2a4, __BITS( 8, 6), 3), 259 [JH7110_SYS_PAD_GPIO33] = JH7110_FS(0x2a4, __BITS(11, 9), 3), 260 [JH7110_SYS_PAD_GPIO34] = JH7110_FS(0x2a4, __BITS(14,12), 3), 261 [JH7110_SYS_PAD_GPIO35] = JH7110_FS(0x2a4, __BITS(17,15), 3), 262 [JH7110_SYS_PAD_GPIO36] = JH7110_FS(0x2a4, __BITS(19,17), 3), 263 [JH7110_SYS_PAD_GPIO37] = JH7110_FS(0x2a4, __BITS(23,20), 3), 264 [JH7110_SYS_PAD_GPIO38] = JH7110_FS(0x2a4, __BITS(26,23), 3), 265 [JH7110_SYS_PAD_GPIO39] = JH7110_FS(0x2a4, __BITS(28,26), 3), 266 [JH7110_SYS_PAD_GPIO40] = JH7110_FS(0x2a4, __BITS(31,29), 3), 267 268 [JH7110_SYS_PAD_GPIO41] = JH7110_FS(0x2a8, __BITS( 2, 0), 3), 269 [JH7110_SYS_PAD_GPIO42] = JH7110_FS(0x2a8, __BITS( 5, 3), 3), 270 [JH7110_SYS_PAD_GPIO43] = JH7110_FS(0x2a8, __BITS( 8, 6), 3), 271 [JH7110_SYS_PAD_GPIO44] = JH7110_FS(0x2a8, __BITS(11, 9), 3), 272 [JH7110_SYS_PAD_GPIO45] = JH7110_FS(0x2a8, __BITS(14,12), 3), 273 [JH7110_SYS_PAD_GPIO46] = JH7110_FS(0x2a8, __BITS(17,15), 3), 274 [JH7110_SYS_PAD_GPIO47] = JH7110_FS(0x2a8, __BITS(20,18), 3), 275 [JH7110_SYS_PAD_GPIO48] = JH7110_FS(0x2a8, __BITS(23,21), 3), 276 [JH7110_SYS_PAD_GPIO49] = JH7110_FS(0x2a8, __BITS(26,24), 3), 277 [JH7110_SYS_PAD_GPIO50] = JH7110_FS(0x2a8, __BITS(29,27), 3), 278 [JH7110_SYS_PAD_GPIO51] = JH7110_FS(0x2a8, __BITS(31,30), 3), 279 280 [JH7110_SYS_PAD_GPIO52] = JH7110_FS(0x2ac, __BITS( 1, 0), 3), 281 [JH7110_SYS_PAD_GPIO53] = JH7110_FS(0x2ac, __BITS( 3, 2), 3), 282 [JH7110_SYS_PAD_GPIO54] = JH7110_FS(0x2ac, __BITS( 5, 4), 3), 283 [JH7110_SYS_PAD_GPIO55] = JH7110_FS(0x2ac, __BITS( 8, 6), 3), 284 [JH7110_SYS_PAD_GPIO56] = JH7110_FS(0x2ac, __BITS(11, 9), 3), 285 [JH7110_SYS_PAD_GPIO57] = JH7110_FS(0x2ac, __BITS(14,12), 3), 286 [JH7110_SYS_PAD_GPIO58] = JH7110_FS(0x2ac, __BITS(17,15), 3), 287 [JH7110_SYS_PAD_GPIO59] = JH7110_FS(0x2ac, __BITS(20,18), 3), 288 [JH7110_SYS_PAD_GPIO60] = JH7110_FS(0x2ac, __BITS(23,21), 3), 289 [JH7110_SYS_PAD_GPIO61] = JH7110_FS(0x2ac, __BITS(26,24), 3), 290 [JH7110_SYS_PAD_GPIO62] = JH7110_FS(0x2ac, __BITS(29,27), 3), 291 [JH7110_SYS_PAD_GPIO63] = JH7110_FS(0x2ac, __BITS(31,30), 3), 292 293 [JH7110_SYS_PAD_GPIO6] = JH7110_FS(0x2b0, __BITS( 1, 0), 3), 294 [JH7110_SYS_PAD_GPIO7] = JH7110_FS(0x2b0, __BITS( 4, 2), 3), 295 [JH7110_SYS_PAD_GPIO8] = JH7110_FS(0x2b0, __BITS( 7, 5), 3), 296 [JH7110_SYS_PAD_GPIO9] = JH7110_FS(0x2b0, __BITS(10, 8), 3), 297 }; 298 299 static void 300 jh7110_set_function(struct jh7110_pinctrl_softc *sc, u_int pin_no, 301 u_int func) 302 { 303 if (pin_no >= __arraycount(jh7110_sys_func_sel)) 304 return; 305 306 const struct jh7110_func_sel * const jfs = 307 &jh7110_sys_func_sel[pin_no]; 308 309 if (func > jfs->jfs_max) 310 return; 311 312 if (jfs->jfs_funcreg == 0) 313 return; 314 315 uint32_t funcold, funcval; 316 mutex_enter(&sc->sc_lock); 317 funcold = RD4(sc, jfs->jfs_funcreg); 318 319 funcval = funcold & ~jfs->jfs_mask; 320 funcval |= __SHIFTIN(func, jfs->jfs_mask); 321 322 WR4(sc, jfs->jfs_funcreg, funcval); 323 mutex_exit(&sc->sc_lock); 324 } 325 326 327 static void 328 jh7110_set_gpiomux(struct jh7110_pinctrl_softc * const sc, u_int pin_no, 329 u_int din, u_int dout, u_int doen) 330 { 331 const struct jh7110_pinctrl_data * const jpd = sc->sc_jpd; 332 const u_int offset = 4 * (pin_no / 4); 333 const u_int shift = 8 * (pin_no % 4); 334 const uint32_t dout_mask = jpd->jpd_dout_mask << shift; 335 const uint32_t doen_mask = jpd->jpd_doen_mask << shift; 336 const bus_size_t dout_reg = jpd->jpd_dout + offset; 337 const bus_size_t doen_reg = jpd->jpd_doen + offset; 338 uint32_t doutval, doutold; 339 uint32_t doenval, doenold; 340 uint32_t dinval, dinold; 341 342 mutex_enter(&sc->sc_lock); 343 doutold = RD4(sc, dout_reg); 344 doutval = doutold & ~dout_mask; 345 doutval |= __SHIFTIN(dout, dout_mask); 346 347 doenold = RD4(sc, doen_reg); 348 doenval = doenold & ~doen_mask; 349 doenval |= __SHIFTIN(doen, doen_mask); 350 351 WR4(sc, dout_reg, doutval); 352 WR4(sc, doen_reg, doenval); 353 if (din != GPI_NONE) { 354 const u_int din_offset = 4 * (din / 4); 355 const u_int din_shift = 8 * (din % 4); 356 const uint32_t din_mask = jpd->jpd_gpi_mask << din_shift; 357 const bus_size_t din_reg = jpd->jpd_gpi + din_offset; 358 359 dinold = RD4(sc, din_reg); 360 dinval = dinold & ~din_mask; 361 /* 362 * The register value indicates the selected GPIO number + 2 363 * (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the 364 * input signal. 365 */ 366 dinval |= __SHIFTIN(pin_no + 2, din_mask); 367 WR4(sc, din_reg, dinval); 368 } 369 mutex_exit(&sc->sc_lock); 370 } 371 372 373 static const struct jh7110_pinctrl_data jh7110_aon_pinctrl_data = { 374 .jpd_npins = JH7110_AON_NPIN, 375 .jpd_ngpios = JH7110_AON_NGPIO, 376 .jpd_doen = JH7110_AON_DOEN, 377 .jpd_doen_mask = __BITS(2, 0), 378 .jpd_dout = JH7110_AON_DOUT, 379 .jpd_dout_mask = __BITS(3, 0), 380 .jpd_gpi = JH7110_AON_GPI, 381 .jpd_gpi_mask = __BITS(3, 0), 382 .jpd_gpioin = JH7110_AON_GPIOIN, 383 }; 384 385 static const struct jh7110_pinctrl_data jh7110_sys_pinctrl_data = { 386 .jpd_npins = JH7110_SYS_NPIN, 387 .jpd_ngpios = JH7110_SYS_NGPIO, 388 .jpd_doen = JH7110_SYS_DOEN, 389 .jpd_doen_mask = __BITS(5, 0), 390 .jpd_dout = JH7110_SYS_DOUT, 391 .jpd_dout_mask = __BITS(6, 0), 392 .jpd_gpi = JH7110_SYS_GPI, 393 .jpd_gpi_mask = __BITS(6, 0), 394 .jpd_gpioin = JH7110_SYS_GPIOIN, 395 }; 396 397 398 static int 399 jh7110_set_pinmux(struct jh7110_pinctrl_softc *sc, u_int pin, 400 u_int din, u_int dout, u_int doen, u_int func) 401 { 402 const struct jh7110_pinctrl_data * const jpd = sc->sc_jpd; 403 404 if (pin < jpd->jpd_ngpios && func == 0) 405 jh7110_set_gpiomux(sc, pin, din, dout, doen); 406 return 0; 407 408 if (sc->sc_jpd == &jh7110_aon_pinctrl_data) 409 return 0; 410 411 if (pin < jpd->jpd_npins) 412 jh7110_set_function(sc, pin, func); 413 414 return 0; 415 } 416 417 418 /* Device Tree encoding */ 419 #define DT_PINMUX_DIN_MASK __BITS(31, 24) 420 #define DT_PINMUX_DOUT_MASK __BITS(23, 16) 421 #define DT_PINMUX_DOEN_MASK __BITS(15, 10) 422 #define DT_PINMUX_FUNC_MASK __BITS( 9, 8) 423 #define DT_PINMUX_PIN_MASK __BITS( 7, 0) 424 425 static int 426 jh7110_parse_slew_rate(int phandle) 427 { 428 int slew_rate; 429 430 if (of_getprop_uint32(phandle, "slew-rate", &slew_rate) == 0) 431 return slew_rate; 432 433 return -1; 434 } 435 436 static void 437 jh7110_pinctrl_pin_properties(struct jh7110_pinctrl_softc *sc, int phandle, 438 uint16_t *val, uint16_t *mask) 439 { 440 *mask = 0; 441 *val = 0; 442 443 const int bias = fdtbus_pinctrl_parse_bias(phandle, NULL); 444 const int drive_strength = fdtbus_pinctrl_parse_drive_strength(phandle); 445 const int slew_rate = jh7110_parse_slew_rate(phandle); 446 447 #define JH7110_PADCFG_POS __BIT(7) 448 #define JH7110_PADCFG_SMT __BIT(6) 449 #define JH7110_PADCFG_SLEW __BIT(5) 450 451 switch (bias) { 452 case 0: 453 *mask |= JH7110_PADCFG_BIAS_MASK; 454 break; 455 case GPIO_PIN_PULLUP: 456 *mask |= JH7110_PADCFG_BIAS_MASK; 457 *val |= JH7110_PADCFG_PU; 458 break; 459 case GPIO_PIN_PULLDOWN: 460 *mask |= JH7110_PADCFG_BIAS_MASK; 461 *val |= JH7110_PADCFG_PD; 462 break; 463 case -1: 464 default: 465 break; 466 } 467 468 switch (drive_strength) { 469 case 2: 470 *mask |= JH7110_PADCFG_DS_MASK; 471 *val |= JH7110_PADCFG_DS_2MA; 472 break; 473 case 4: 474 *mask |= JH7110_PADCFG_DS_MASK; 475 *val |= JH7110_PADCFG_DS_4MA; 476 break; 477 case 8: 478 *mask |= JH7110_PADCFG_DS_MASK; 479 *val |= JH7110_PADCFG_DS_8MA; 480 break; 481 case 12: 482 *mask |= JH7110_PADCFG_DS_MASK; 483 *val |= JH7110_PADCFG_DS_12MA; 484 break; 485 case -1: 486 break; 487 default: 488 aprint_error_dev(sc->sc_dev, "phandle %d invalid drive " 489 "strength %d\n", phandle, drive_strength); 490 } 491 492 if (of_hasprop(phandle, "input-enable")) { 493 *mask |= JH7110_PADCFG_IE; 494 *val |= JH7110_PADCFG_IE; 495 } 496 if (of_hasprop(phandle, "input-disable")) { 497 *mask |= JH7110_PADCFG_IE; 498 *val &= ~JH7110_PADCFG_IE; 499 } 500 if (of_hasprop(phandle, "input-schmitt-enable")) { 501 *mask |= JH7110_PADCFG_SMT; 502 *val |= JH7110_PADCFG_SMT; 503 } 504 if (of_hasprop(phandle, "input-schmitt-disable")) { 505 *mask |= JH7110_PADCFG_SMT; 506 *val &= ~JH7110_PADCFG_SMT; 507 } 508 509 switch (slew_rate) { 510 case 0: 511 *mask |= JH7110_PADCFG_SLEW; 512 *val &= ~JH7110_PADCFG_SLEW; 513 break; 514 case 1: 515 *mask |= JH7110_PADCFG_SLEW; 516 *val |= JH7110_PADCFG_SLEW; 517 break; 518 case -1: 519 break; 520 default: 521 aprint_error_dev(sc->sc_dev, "invalid slew rate"); 522 } 523 } 524 525 526 static void 527 jh7110_pinctrl_set_config_group(struct jh7110_pinctrl_softc *sc, int group) 528 { 529 int pinmux_len; 530 const u_int *pinmux = fdtbus_get_prop(group, "pinmux", &pinmux_len); 531 size_t plen; 532 const u_int *parray; 533 534 aprint_debug_dev(sc->sc_dev, "set_config: group %d\n", group); 535 if (pinmux == NULL) { 536 aprint_debug_dev(sc->sc_dev, "group %d neither 'pins' nor " 537 "'pinmux' exist\n", group); 538 return; 539 } 540 if (pinmux != NULL) { 541 plen = pinmux_len; 542 parray = pinmux; 543 } 544 const size_t npins = plen / sizeof(uint32_t); 545 546 aprint_debug_dev(sc->sc_dev, "set_config: group %d, len %zu\n", 547 group, plen); 548 549 uint16_t val, mask; 550 jh7110_pinctrl_pin_properties(sc, group, &val, &mask); 551 552 for (size_t i = 0; i < npins; i++) { 553 uint32_t p = be32dec(&parray[i]); 554 u_int pin_no; 555 556 #if 0 557 if (pins != NULL) { 558 pin_no = p; 559 aprint_debug_dev(sc->sc_dev, "set_config: group %d" 560 ", gpio %d doen %#x\n", group, pin_no, 561 RD4(sc, GPO_DOEN_CFG(pin_no))); 562 WR4(sc, GPO_DOEN_CFG(pin_no), GPO_DISABLE); 563 jh7110_padctl_rmw(sc, pin_no, 564 val, mask); 565 } 566 #endif 567 if (pinmux != NULL) { 568 u_int din = __SHIFTOUT(p, DT_PINMUX_DIN_MASK); 569 u_int dout = __SHIFTOUT(p, DT_PINMUX_DOUT_MASK); 570 u_int doen = __SHIFTOUT(p, DT_PINMUX_DOEN_MASK); 571 u_int func = __SHIFTOUT(p, DT_PINMUX_FUNC_MASK); 572 pin_no = __SHIFTOUT(p, DT_PINMUX_PIN_MASK); 573 jh7110_set_pinmux(sc, pin_no, din, dout, 574 doen, func); 575 } 576 } 577 } 578 579 static int 580 jh7110_pinctrl_set_config(device_t dev, const void *data, size_t len) 581 { 582 struct jh7110_pinctrl_softc * const sc = device_private(dev); 583 584 if (len != sizeof(uint32_t)) 585 return -1; 586 587 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 588 aprint_debug_dev(sc->sc_dev, "set_config: phandle %d\n", phandle); 589 590 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 591 jh7110_pinctrl_set_config_group(sc, child); 592 } 593 594 return 0; 595 } 596 597 static struct fdtbus_pinctrl_controller_func jh7110_pinctrl_funcs = { 598 .set_config = jh7110_pinctrl_set_config, 599 }; 600 601 602 static void * 603 jh7110_pinctrl_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 604 { 605 struct jh7110_pinctrl_softc * const sc = device_private(dev); 606 607 if (len != 3 * sizeof(uint32_t)) 608 return NULL; 609 610 const u_int *gpio = data; 611 const u_int pin_no = be32toh(gpio[1]); 612 const bool actlo = be32toh(gpio[2]) & 1; 613 614 // XXXNH twiddle something?? 615 struct jh7110_pinctrl_gpio_pin *pin = 616 kmem_zalloc(sizeof(*pin), KM_SLEEP); 617 pin->pin_sc = sc; 618 pin->pin_no = pin_no; 619 pin->pin_actlo = actlo; 620 621 return pin; 622 } 623 624 static void 625 jh7110_pinctrl_gpio_release(device_t dev, void *priv) 626 { 627 struct jh7110_pinctrl_softc * const sc = device_private(dev); 628 struct jh7110_pinctrl_gpio_pin *pin = priv; 629 630 KASSERT(sc == pin->pin_sc); 631 // XXXNH untwiddle something? 632 kmem_free(pin, sizeof(*pin)); 633 } 634 635 636 static int 637 jh7110_pinctrl_gpio_read(device_t dev, void *priv, bool raw) 638 { 639 struct jh7110_pinctrl_softc * const sc = device_private(dev); 640 struct jh7110_pinctrl_gpio_pin *pin = priv; 641 642 const u_int pin_no = pin ->pin_no; 643 const u_int pins_per_bank = 32; 644 const size_t banksz = sizeof(uint32_t); 645 const bus_size_t offset = ((pin_no) / pins_per_bank) * banksz; 646 const uint32_t mask = __BIT(pin_no % pins_per_bank); 647 const uint32_t bank = RD4(sc, sc->sc_jpd->jpd_gpioin + offset); 648 649 int val = __SHIFTOUT(bank, mask); 650 if (!raw && pin->pin_actlo) 651 val = !val; 652 653 return val; 654 } 655 656 657 static void 658 jh7110_pinctrl_gpio_write(device_t dev, void *priv, int val, bool raw) 659 { 660 struct jh7110_pinctrl_softc * const sc = device_private(dev); 661 struct jh7110_pinctrl_gpio_pin *pin = priv; 662 663 const u_int pin_no = pin ->pin_no; 664 const u_int pins_per_bank = 4; 665 const size_t banksz = sizeof(uint32_t); 666 const u_int bits_per_bank = banksz * NBBY; 667 const u_int bits_per_pin = bits_per_bank / pins_per_bank; 668 const bus_size_t offset = ((pin_no) / pins_per_bank) * banksz; 669 const u_int shift = bits_per_pin * (pin_no % pins_per_bank); 670 const uint32_t mask = sc->sc_jpd->jpd_dout_mask << shift; 671 672 if (!raw && pin->pin_actlo) 673 val = !val; 674 675 mutex_enter(&sc->sc_lock); 676 uint32_t bank = RD4(sc, sc->sc_jpd->jpd_dout + offset); 677 bank &= ~mask; 678 bank |= __SHIFTIN(val != 0 ? GPOUT_HIGH : GPOUT_LOW, mask); 679 WR4(sc, sc->sc_jpd->jpd_dout + offset, bank); 680 mutex_exit(&sc->sc_lock); 681 } 682 683 684 static struct fdtbus_gpio_controller_func jh7110_pinctrl_gpio_funcs = { 685 .acquire = jh7110_pinctrl_gpio_acquire, 686 .release = jh7110_pinctrl_gpio_release, 687 .read = jh7110_pinctrl_gpio_read, 688 .write = jh7110_pinctrl_gpio_write, 689 }; 690 691 692 static const struct device_compatible_entry compat_data[] = { 693 { .compat = "starfive,jh7110-sys-pinctrl", .data = &jh7110_sys_pinctrl_data }, 694 { .compat = "starfive,jh7110-aon-pinctrl", .data = &jh7110_aon_pinctrl_data }, 695 DEVICE_COMPAT_EOL 696 }; 697 698 699 static int 700 jh7110_pinctrl_match(device_t parent, cfdata_t cf, void *aux) 701 { 702 struct fdt_attach_args * const faa = aux; 703 704 return of_compatible_match(faa->faa_phandle, compat_data); 705 } 706 707 static void 708 jh7110_pinctrl_attach(device_t parent, device_t self, void *aux) 709 { 710 struct jh7110_pinctrl_softc *sc = device_private(self); 711 struct fdt_attach_args * const faa = aux; 712 const int phandle = faa->faa_phandle; 713 bus_addr_t addr; 714 bus_size_t size; 715 int error; 716 717 sc->sc_dev = self; 718 sc->sc_phandle = phandle; 719 sc->sc_bst = faa->faa_bst; 720 error = fdtbus_get_reg(phandle, 0, &addr, &size); 721 if (error) { 722 aprint_error(": couldn't get registers\n"); 723 return; 724 } 725 726 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 727 if (error) { 728 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, 729 error); 730 return; 731 } 732 733 sc->sc_jpd = of_compatible_lookup(phandle, compat_data)->data; 734 735 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 736 737 aprint_naive("\n"); 738 aprint_normal(": Pin Controller\n"); 739 740 fdtbus_register_gpio_controller(sc->sc_dev, sc->sc_phandle, 741 &jh7110_pinctrl_gpio_funcs); 742 743 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 744 fdtbus_register_pinctrl_config(self, child, 745 &jh7110_pinctrl_funcs); 746 } 747 } 748 749 CFATTACH_DECL_NEW(jh7110_pinctrl, sizeof(struct jh7110_pinctrl_softc), 750 jh7110_pinctrl_match, jh7110_pinctrl_attach, NULL, NULL); 751
Indexes created Mon Sep 29 21:09:56 GMT 2025