sun20i_d1_ccu.c revision 1.1
1 /* $NetBSD: sun20i_d1_ccu.c,v 1.1 2024/08/13 07:20:23 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 Rui-Xiang Guo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun20i_d1_ccu.c,v 1.1 2024/08/13 07:20:23 skrll Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <riscv/sunxi/sun20i_d1_ccu.h> 42 43 #define PLL_CPU_CTRL_REG 0x000 44 #define PLL_DDR_CTRL_REG 0x010 45 #define PLL_PERI_CTRL_REG 0x020 46 #define PLL_AUDIO1_CTRL_REG 0x080 47 #define PSI_CLK_REG 0x510 48 #define APB0_CLK_REG 0x520 49 #define APB1_CLK_REG 0x524 50 #define MBUS_CLK_REG 0x540 51 #define DE_BGR_REG 0x60c 52 #define DI_BGR_REG 0x62c 53 #define G2D_BGR_REG 0x63c 54 #define CE_BGR_REG 0x68c 55 #define VE_BGR_REG 0x69c 56 #define DMA_BGR_REG 0x70c 57 #define MSGBOX_BGR_REG 0x71c 58 #define SPINLOCK_BGR_REG 0x72c 59 #define HSTIMER_BGR_REG 0x73c 60 #define AVS_CLK_REG 0x740 61 #define DBGSYS_BGR_REG 0x78c 62 #define PWM_BGR_REG 0x7ac 63 #define IOMMU_BGR_REG 0x7bc 64 #define DRAM_CLK_REG 0x800 65 #define MBUS_MAT_CLK_GATING_REG 0x804 66 #define DRAM_BGR_REG 0x80c 67 #define SMHC0_CLK_REG 0x830 68 #define SMHC1_CLK_REG 0x834 69 #define SMHC2_CLK_REG 0x838 70 #define SMHC_BGR_REG 0x84c 71 #define UART_BGR_REG 0x90c 72 #define TWI_BGR_REG 0x91c 73 #define SPI_BGR_REG 0x96c 74 #define EMAC_BGR_REG 0x97c 75 #define IRTX_BGR_REG 0x9cc 76 #define GPADC_BGR_REG 0x9ec 77 #define THS_BGR_REG 0x9fc 78 #define I2S_BGR_REG 0xa20 79 #define OWA_BGR_REG 0xa2c 80 #define DMIC_BGR_REG 0xa4c 81 #define AUDIO_CODEC_BGR_REG 0xa5c 82 #define USB0_CLK_REG 0xa70 83 #define USB1_CLK_REG 0xa74 84 #define USB_BGR_REG 0xa8c 85 #define LRADC_BGR_REG 0xa9c 86 #define DPSS_TOP_BGR_REG 0xabc 87 #define HDMI_BGR_REG 0xb1c 88 #define DSI_BGR_REG 0xb4c 89 #define TCONLCD_BGR_REG 0xb7c 90 #define TCONTV_BGR_REG 0xb9c 91 #define LVDS_BGR_REG 0xbac 92 #define TVE_BGR_REG 0xbbc 93 #define TVD_BGR_REG 0xbdc 94 #define LEDC_BGR_REG 0xbfc 95 #define CSI_BGR_REG 0xc1c 96 #define TPADC_BGR_REG 0xc5c 97 #define DSP_BGR_REG 0xc7c 98 #define RISCV_CFG_BGR_REG 0xd0c 99 100 static int sun20i_d1_ccu_match(device_t, cfdata_t, void *); 101 static void sun20i_d1_ccu_attach(device_t, device_t, void *); 102 103 static const struct device_compatible_entry compat_data[] = { 104 { .compat = "allwinner,sun20i-d1-ccu" }, 105 DEVICE_COMPAT_EOL 106 }; 107 108 CFATTACH_DECL_NEW(sunxi_d1_ccu, sizeof(struct sunxi_ccu_softc), 109 sun20i_d1_ccu_match, sun20i_d1_ccu_attach, NULL, NULL); 110 111 static struct sunxi_ccu_reset sun20i_d1_ccu_resets[] = { 112 SUNXI_CCU_RESET(D1_RST_MBUS, MBUS_CLK_REG, 30), 113 114 SUNXI_CCU_RESET(D1_RST_BUS_DE, DE_BGR_REG, 16), 115 116 SUNXI_CCU_RESET(D1_RST_BUS_DI, DI_BGR_REG, 16), 117 118 SUNXI_CCU_RESET(D1_RST_BUS_G2D, G2D_BGR_REG, 16), 119 120 SUNXI_CCU_RESET(D1_RST_BUS_CE, CE_BGR_REG, 16), 121 122 SUNXI_CCU_RESET(D1_RST_BUS_VE, VE_BGR_REG, 16), 123 124 SUNXI_CCU_RESET(D1_RST_BUS_DMA, DMA_BGR_REG, 16), 125 126 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX0, MSGBOX_BGR_REG, 16), 127 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX1, MSGBOX_BGR_REG, 17), 128 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX2, MSGBOX_BGR_REG, 18), 129 130 SUNXI_CCU_RESET(D1_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16), 131 132 SUNXI_CCU_RESET(D1_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16), 133 134 SUNXI_CCU_RESET(D1_RST_BUS_DBGSYS, DBGSYS_BGR_REG, 16), 135 136 SUNXI_CCU_RESET(D1_RST_BUS_PWM, PWM_BGR_REG, 16), 137 138 SUNXI_CCU_RESET(D1_RST_BUS_DRAM, DRAM_BGR_REG, 16), 139 140 SUNXI_CCU_RESET(D1_RST_BUS_MMC0, SMHC_BGR_REG, 16), 141 SUNXI_CCU_RESET(D1_RST_BUS_MMC1, SMHC_BGR_REG, 17), 142 SUNXI_CCU_RESET(D1_RST_BUS_MMC2, SMHC_BGR_REG, 18), 143 144 SUNXI_CCU_RESET(D1_RST_BUS_UART0, UART_BGR_REG, 16), 145 SUNXI_CCU_RESET(D1_RST_BUS_UART1, UART_BGR_REG, 17), 146 SUNXI_CCU_RESET(D1_RST_BUS_UART2, UART_BGR_REG, 18), 147 SUNXI_CCU_RESET(D1_RST_BUS_UART3, UART_BGR_REG, 19), 148 SUNXI_CCU_RESET(D1_RST_BUS_UART4, UART_BGR_REG, 20), 149 SUNXI_CCU_RESET(D1_RST_BUS_UART5, UART_BGR_REG, 21), 150 151 SUNXI_CCU_RESET(D1_RST_BUS_I2C0, TWI_BGR_REG, 16), 152 SUNXI_CCU_RESET(D1_RST_BUS_I2C1, TWI_BGR_REG, 17), 153 SUNXI_CCU_RESET(D1_RST_BUS_I2C2, TWI_BGR_REG, 18), 154 SUNXI_CCU_RESET(D1_RST_BUS_I2C3, TWI_BGR_REG, 19), 155 156 SUNXI_CCU_RESET(D1_RST_BUS_SPI0, SPI_BGR_REG, 16), 157 SUNXI_CCU_RESET(D1_RST_BUS_SPI1, SPI_BGR_REG, 17), 158 159 SUNXI_CCU_RESET(D1_RST_BUS_EMAC, EMAC_BGR_REG, 16), 160 161 SUNXI_CCU_RESET(D1_RST_BUS_IRTX, IRTX_BGR_REG, 16), 162 163 SUNXI_CCU_RESET(D1_RST_BUS_GPADC, GPADC_BGR_REG, 16), 164 165 SUNXI_CCU_RESET(D1_RST_BUS_THS, THS_BGR_REG, 16), 166 167 SUNXI_CCU_RESET(D1_RST_BUS_I2S0, I2S_BGR_REG, 16), 168 SUNXI_CCU_RESET(D1_RST_BUS_I2S1, I2S_BGR_REG, 17), 169 SUNXI_CCU_RESET(D1_RST_BUS_I2S2, I2S_BGR_REG, 18), 170 171 SUNXI_CCU_RESET(D1_RST_BUS_SPDIF, OWA_BGR_REG, 16), 172 173 SUNXI_CCU_RESET(D1_RST_BUS_DMIC, DMIC_BGR_REG, 16), 174 175 SUNXI_CCU_RESET(D1_RST_BUS_AUDIO, AUDIO_CODEC_BGR_REG, 16), 176 177 SUNXI_CCU_RESET(D1_RST_USB_PHY0, USB0_CLK_REG, 30), 178 179 SUNXI_CCU_RESET(D1_RST_USB_PHY1, USB1_CLK_REG, 30), 180 181 SUNXI_CCU_RESET(D1_RST_BUS_OHCI0, USB_BGR_REG, 16), 182 SUNXI_CCU_RESET(D1_RST_BUS_OHCI1, USB_BGR_REG, 17), 183 SUNXI_CCU_RESET(D1_RST_BUS_EHCI0, USB_BGR_REG, 20), 184 SUNXI_CCU_RESET(D1_RST_BUS_EHCI1, USB_BGR_REG, 21), 185 SUNXI_CCU_RESET(D1_RST_BUS_OTG, USB_BGR_REG, 24), 186 187 SUNXI_CCU_RESET(D1_RST_BUS_LRADC, LRADC_BGR_REG, 16), 188 189 SUNXI_CCU_RESET(D1_RST_BUS_DPSS_TOP, DPSS_TOP_BGR_REG, 16), 190 191 SUNXI_CCU_RESET(D1_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17), 192 SUNXI_CCU_RESET(D1_RST_BUS_HDMI_MAIN, HDMI_BGR_REG, 16), 193 194 SUNXI_CCU_RESET(D1_RST_BUS_DSI, DSI_BGR_REG, 16), 195 196 SUNXI_CCU_RESET(D1_RST_BUS_TCONLCD, TCONLCD_BGR_REG, 16), 197 198 SUNXI_CCU_RESET(D1_RST_BUS_TCONTV, TCONTV_BGR_REG, 16), 199 200 SUNXI_CCU_RESET(D1_RST_BUS_LVDS, LVDS_BGR_REG, 16), 201 202 SUNXI_CCU_RESET(D1_RST_BUS_TVE_TOP, TVE_BGR_REG, 16), 203 SUNXI_CCU_RESET(D1_RST_BUS_TVE, TVE_BGR_REG, 17), 204 205 SUNXI_CCU_RESET(D1_RST_BUS_TVD_TOP, TVD_BGR_REG, 16), 206 SUNXI_CCU_RESET(D1_RST_BUS_TVD, TVD_BGR_REG, 17), 207 208 SUNXI_CCU_RESET(D1_RST_BUS_LEDC, LEDC_BGR_REG, 16), 209 210 SUNXI_CCU_RESET(D1_RST_BUS_CSI, CSI_BGR_REG, 16), 211 212 SUNXI_CCU_RESET(D1_RST_BUS_TPADC, TPADC_BGR_REG, 16), 213 214 SUNXI_CCU_RESET(D1_RST_BUS_DSP, DSP_BGR_REG, 16), 215 SUNXI_CCU_RESET(D1_RST_BUS_DSP_CFG, DSP_BGR_REG, 17), 216 SUNXI_CCU_RESET(D1_RST_BUS_DSP_DBG, DSP_BGR_REG, 18), 217 218 SUNXI_CCU_RESET(D1_RST_BUS_RISCV_CFG, RISCV_CFG_BGR_REG, 16), 219 }; 220 221 static const char *psi_parents[] = { "hosc", "losc", "iosc", "pll_periph" }; 222 static const char *apb_parents[] = { "hosc", "losc", "psi", "pll_periph" }; 223 static const char *dram_parents[] = { "pll_ddr", "pll_audio1_div2", "pll_periph_2x", "pll_periph_800m" }; 224 static const char *mmc_parents[] = { "hosc", "pll_periph", "pll_periph_2x", "pll_audio1_div2" }; 225 static const char *mmc2_parents[] = { "pll_periph", "pll_periph_2x", "pll_periph_800m", "pll_audio1_div2" }; 226 227 static struct sunxi_ccu_clk sun20i_d1_ccu_clks[] = { 228 SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_CPU, "pll_cpu", "hosc", 229 PLL_CPU_CTRL_REG, /* reg */ 230 __BITS(15,8), /* n */ 231 0, /* k */ 232 0, /* m */ 233 0, /* p */ 234 __BIT(31), /* enable */ 235 __BIT(28), /* lock */ 236 NULL, /* table */ 237 SUNXI_CCU_NKMP_SCALE_CLOCK), 238 239 SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_DDR, "pll_ddr", "hosc", 240 PLL_DDR_CTRL_REG, /* reg */ 241 __BITS(15,8), /* n */ 242 0, /* k */ 243 __BIT(1), /* m */ 244 __BIT(0), /* p */ 245 __BIT(31), /* enable */ 246 __BIT(28), /* lock */ 247 NULL, /* table */ 248 SUNXI_CCU_NKMP_SCALE_CLOCK), 249 250 SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_PERIPH_2X, "pll_periph_2x", "hosc", 251 PLL_PERI_CTRL_REG, /* reg */ 252 __BITS(15,8), /* n */ 253 0, /* k */ 254 __BIT(1), /* m */ 255 __BITS(18,16), /* p */ 256 __BIT(31), /* enable */ 257 __BIT(28), /* lock */ 258 NULL, /* table */ 259 SUNXI_CCU_NKMP_SCALE_CLOCK), 260 261 SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_PERIPH_800M, "pll_periph_800m", "hosc", 262 PLL_PERI_CTRL_REG, /* reg */ 263 __BITS(15,8), /* n */ 264 0, /* k */ 265 __BIT(1), /* m */ 266 __BITS(22,20), /* p */ 267 __BIT(31), /* enable */ 268 __BIT(28), /* lock */ 269 NULL, /* table */ 270 SUNXI_CCU_NKMP_SCALE_CLOCK), 271 272 SUNXI_CCU_FIXED_FACTOR(D1_CLK_PLL_PERIPH, "pll_periph", "pll_periph_2x", 2, 1), 273 274 SUNXI_CCU_NKMP_TABLE(D1_CLK_PLL_AUDIO1, "pll_audio1_div2", "hosc", 275 PLL_AUDIO1_CTRL_REG, /* reg */ 276 __BITS(15,8), /* n */ 277 0, /* k */ 278 __BIT(1), /* m */ 279 __BITS(18,16), /* p */ 280 __BIT(31), /* enable */ 281 __BIT(28), /* lock */ 282 NULL, /* table */ 283 SUNXI_CCU_NKMP_SCALE_CLOCK), 284 285 SUNXI_CCU_NM(D1_CLK_PSI, "psi", psi_parents, 286 PSI_CLK_REG, /* reg */ 287 __BITS(9,8), /* n */ 288 __BITS(1,0), /* m */ 289 __BITS(25,24), /* sel */ 290 0, /* enable */ 291 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 292 293 SUNXI_CCU_NM(D1_CLK_APB0, "apb0", apb_parents, 294 APB0_CLK_REG, /* reg */ 295 __BITS(9,8), /* n */ 296 __BITS(4,0), /* m */ 297 __BITS(25,24), /* sel */ 298 0, /* enable */ 299 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 300 301 SUNXI_CCU_NM(D1_CLK_APB1, "apb1", apb_parents, 302 APB1_CLK_REG, /* reg */ 303 __BITS(9,8), /* n */ 304 __BITS(4,0), /* m */ 305 __BITS(25,24), /* sel */ 306 0, /* enable */ 307 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 308 309 SUNXI_CCU_FIXED_FACTOR(D1_CLK_MBUS, "mbus", "dram", 4, 1), 310 311 SUNXI_CCU_NM(D1_CLK_DRAM, "dram", dram_parents, 312 DRAM_CLK_REG, /* reg */ 313 __BITS(9,8), /* n */ 314 __BITS(1,0), /* m */ 315 __BITS(26,24), /* sel */ 316 __BIT(31), /* enable */ 317 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 318 319 SUNXI_CCU_NM(D1_CLK_MMC0, "mmc0", mmc_parents, 320 SMHC0_CLK_REG, /* reg */ 321 __BITS(9,8), /* n */ 322 __BITS(3,0), /* m */ 323 __BITS(26,24), /* sel */ 324 __BIT(31), /* enable */ 325 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 326 SUNXI_CCU_NM(D1_CLK_MMC1, "mmc1", mmc_parents, 327 SMHC1_CLK_REG, /* reg */ 328 __BITS(9,8), /* n */ 329 __BITS(3,0), /* m */ 330 __BITS(26,24), /* sel */ 331 __BIT(31), /* enable */ 332 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 333 SUNXI_CCU_NM(D1_CLK_MMC2, "mmc2", mmc2_parents, 334 SMHC2_CLK_REG, /* reg */ 335 __BITS(9,8), /* n */ 336 __BITS(3,0), /* m */ 337 __BITS(26,24), /* sel */ 338 __BIT(31), /* enable */ 339 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 340 341 SUNXI_CCU_GATE(D1_CLK_BUS_DE, "bus-de", "psi", 342 DE_BGR_REG, 0), 343 344 SUNXI_CCU_GATE(D1_CLK_BUS_DI, "bus-di", "psi", 345 DI_BGR_REG, 0), 346 347 SUNXI_CCU_GATE(D1_CLK_BUS_G2D, "bus-g2d", "psi", 348 G2D_BGR_REG ,0), 349 350 SUNXI_CCU_GATE(D1_CLK_BUS_CE, "bus-ce", "psi", 351 CE_BGR_REG, 0), 352 353 SUNXI_CCU_GATE(D1_CLK_BUS_VE, "bus-ve", "psi", 354 VE_BGR_REG, 0), 355 356 SUNXI_CCU_GATE(D1_CLK_BUS_DMA, "bus-dma", "psi", 357 DMA_BGR_REG, 0), 358 359 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX0, "bus-msgbox0", "psi", 360 MSGBOX_BGR_REG, 0), 361 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX1, "bus-msgbox1", "psi", 362 MSGBOX_BGR_REG, 1), 363 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX2, "bus-msgbox2", "psi", 364 MSGBOX_BGR_REG, 2), 365 366 SUNXI_CCU_GATE(D1_CLK_BUS_SPINLOCK, "bus-spinlock", "psi", 367 SPINLOCK_BGR_REG, 0), 368 369 SUNXI_CCU_GATE(D1_CLK_BUS_HSTIMER, "bus-hstimer", "psi", 370 HSTIMER_BGR_REG, 0), 371 372 SUNXI_CCU_GATE(D1_CLK_AVS, "avs", "hosc", 373 AVS_CLK_REG, 31), 374 375 SUNXI_CCU_GATE(D1_CLK_BUS_DBGSYS, "bus-dbgsys", "psi", 376 DBGSYS_BGR_REG, 0), 377 378 SUNXI_CCU_GATE(D1_CLK_BUS_PWM, "bus-pwm", "apb0", 379 PWM_BGR_REG, 0), 380 381 SUNXI_CCU_GATE(D1_CLK_BUS_IOMMU, "bus-iommu", "apb0", 382 IOMMU_BGR_REG, 0), 383 384 SUNXI_CCU_GATE(D1_CLK_MBUS_DMA, "mbus-dma", "mbus", 385 MBUS_MAT_CLK_GATING_REG, 0), 386 SUNXI_CCU_GATE(D1_CLK_MBUS_VE, "mbus-ve", "mbus", 387 MBUS_MAT_CLK_GATING_REG, 1), 388 SUNXI_CCU_GATE(D1_CLK_MBUS_CE, "mbus-ce", "mbus", 389 MBUS_MAT_CLK_GATING_REG, 2), 390 SUNXI_CCU_GATE(D1_CLK_MBUS_TVIN, "mbus-tvin", "mbus", 391 MBUS_MAT_CLK_GATING_REG, 7), 392 SUNXI_CCU_GATE(D1_CLK_MBUS_CSI, "mbus-csi", "mbus", 393 MBUS_MAT_CLK_GATING_REG, 8), 394 SUNXI_CCU_GATE(D1_CLK_MBUS_G2D, "mbus-g2d", "mbus", 395 MBUS_MAT_CLK_GATING_REG, 10), 396 SUNXI_CCU_GATE(D1_CLK_MBUS_RISCV, "mbus-riscv", "mbus", 397 MBUS_MAT_CLK_GATING_REG, 11), 398 399 SUNXI_CCU_GATE(D1_CLK_BUS_DRAM, "bus-dram", "psi", 400 DRAM_BGR_REG, 0), 401 402 SUNXI_CCU_GATE(D1_CLK_BUS_MMC0, "bus-mmc0", "psi", 403 SMHC_BGR_REG, 0), 404 SUNXI_CCU_GATE(D1_CLK_BUS_MMC1, "bus-mmc1", "psi", 405 SMHC_BGR_REG, 1), 406 SUNXI_CCU_GATE(D1_CLK_BUS_MMC2, "bus-mmc2", "psi", 407 SMHC_BGR_REG, 2), 408 409 SUNXI_CCU_GATE(D1_CLK_BUS_UART0, "bus-uart0", "apb1", 410 UART_BGR_REG, 0), 411 SUNXI_CCU_GATE(D1_CLK_BUS_UART1, "bus-uart1", "apb1", 412 UART_BGR_REG, 1), 413 SUNXI_CCU_GATE(D1_CLK_BUS_UART2, "bus-uart2", "apb1", 414 UART_BGR_REG, 2), 415 SUNXI_CCU_GATE(D1_CLK_BUS_UART3, "bus-uart3", "apb1", 416 UART_BGR_REG, 3), 417 SUNXI_CCU_GATE(D1_CLK_BUS_UART4, "bus-uart4", "apb1", 418 UART_BGR_REG, 4), 419 SUNXI_CCU_GATE(D1_CLK_BUS_UART5, "bus-uart5", "apb1", 420 UART_BGR_REG, 5), 421 422 SUNXI_CCU_GATE(D1_CLK_BUS_I2C0, "bus-i2c0", "apb1", 423 TWI_BGR_REG, 0), 424 SUNXI_CCU_GATE(D1_CLK_BUS_I2C1, "bus-i2c1", "apb1", 425 TWI_BGR_REG, 1), 426 SUNXI_CCU_GATE(D1_CLK_BUS_I2C2, "bus-i2c2", "apb1", 427 TWI_BGR_REG, 2), 428 SUNXI_CCU_GATE(D1_CLK_BUS_I2C3, "bus-i2c3", "apb1", 429 TWI_BGR_REG, 3), 430 431 SUNXI_CCU_GATE(D1_CLK_BUS_SPI0, "bus-spi0", "psi", 432 SPI_BGR_REG, 0), 433 SUNXI_CCU_GATE(D1_CLK_BUS_SPI1, "bus-spi1", "psi", 434 SPI_BGR_REG, 1), 435 436 SUNXI_CCU_GATE(D1_CLK_BUS_EMAC, "bus-emac", "psi", 437 EMAC_BGR_REG, 0), 438 439 SUNXI_CCU_GATE(D1_CLK_BUS_IRTX, "bus-irtx", "apb0", 440 IRTX_BGR_REG, 0), 441 442 SUNXI_CCU_GATE(D1_CLK_BUS_GPADC, "bus-gpadc", "apb0", 443 GPADC_BGR_REG, 0), 444 445 SUNXI_CCU_GATE(D1_CLK_BUS_THS, "bus-ths", "apb0", 446 THS_BGR_REG, 0), 447 448 SUNXI_CCU_GATE(D1_CLK_BUS_I2S0, "bus-i2s0", "apb0", 449 I2S_BGR_REG, 0), 450 SUNXI_CCU_GATE(D1_CLK_BUS_I2S1, "bus-i2s1", "apb0", 451 I2S_BGR_REG, 1), 452 SUNXI_CCU_GATE(D1_CLK_BUS_I2S2, "bus-i2s2", "apb0", 453 I2S_BGR_REG, 2), 454 455 SUNXI_CCU_GATE(D1_CLK_BUS_SPDIF, "bus-spdif", "apb0", 456 OWA_BGR_REG, 0), 457 458 SUNXI_CCU_GATE(D1_CLK_BUS_DMIC, "bus-dmic", "apb0", 459 DMIC_BGR_REG, 0), 460 461 SUNXI_CCU_GATE(D1_CLK_BUS_AUDIO, "bus-audio", "apb0", 462 AUDIO_CODEC_BGR_REG, 0), 463 464 SUNXI_CCU_GATE(D1_CLK_BUS_OHCI0, "bus-ohci0", "psi", 465 USB_BGR_REG, 0), 466 SUNXI_CCU_GATE(D1_CLK_BUS_OHCI1, "bus-ohci1", "psi", 467 USB_BGR_REG, 1), 468 SUNXI_CCU_GATE(D1_CLK_BUS_EHCI0, "bus-ehci0", "psi", 469 USB_BGR_REG, 4), 470 SUNXI_CCU_GATE(D1_CLK_BUS_EHCI1, "bus-ehci1", "psi", 471 USB_BGR_REG, 5), 472 SUNXI_CCU_GATE(D1_CLK_BUS_OTG, "bus-otg", "psi", 473 USB_BGR_REG, 8), 474 475 SUNXI_CCU_GATE(D1_CLK_BUS_LRADC, "bus-lradc", "apb0", 476 LRADC_BGR_REG, 0), 477 478 SUNXI_CCU_GATE(D1_CLK_BUS_DPSS_TOP, "bus-dpss-top", "psi", 479 DPSS_TOP_BGR_REG, 0), 480 481 SUNXI_CCU_GATE(D1_CLK_BUS_HDMI, "bus-hdmi", "psi", 482 HDMI_BGR_REG, 0), 483 484 SUNXI_CCU_GATE(D1_CLK_BUS_DSI, "bus-dsi", "psi", 485 DSI_BGR_REG, 0), 486 487 SUNXI_CCU_GATE(D1_CLK_BUS_TCONLCD, "bus-tconlcd", "psi", 488 TCONLCD_BGR_REG, 0), 489 490 SUNXI_CCU_GATE(D1_CLK_BUS_TCONTV, "bus-tcontv", "psi", 491 TCONTV_BGR_REG, 0), 492 493 SUNXI_CCU_GATE(D1_CLK_BUS_TVE_TOP, "bus-tve-top", "psi", 494 TVE_BGR_REG, 0), 495 SUNXI_CCU_GATE(D1_CLK_BUS_TVE, "bus-tve", "psi", 496 TVE_BGR_REG, 1), 497 498 SUNXI_CCU_GATE(D1_CLK_BUS_TVD_TOP, "bus-tvd-top", "psi", 499 TVD_BGR_REG, 0), 500 SUNXI_CCU_GATE(D1_CLK_BUS_TVD, "bus-tvd", "psi", 501 TVD_BGR_REG, 1), 502 503 SUNXI_CCU_GATE(D1_CLK_BUS_LEDC, "bus-ledc", "psi", 504 LEDC_BGR_REG, 0), 505 506 SUNXI_CCU_GATE(D1_CLK_BUS_CSI, "bus-csi", "psi", 507 CSI_BGR_REG, 0), 508 509 SUNXI_CCU_GATE(D1_CLK_BUS_TPADC, "bus-tpadc", "apb0", 510 TPADC_BGR_REG, 0), 511 512 SUNXI_CCU_GATE(D1_CLK_BUS_DSP_CFG, "bus-dsp-cfg", "psi", 513 DSP_BGR_REG, 1), 514 515 SUNXI_CCU_GATE(D1_CLK_BUS_RISCV_CFG, "bus-riscv-cfg", "psi", 516 RISCV_CFG_BGR_REG, 0), 517 }; 518 519 static int 520 sun20i_d1_ccu_match(device_t parent, cfdata_t cf, void *aux) 521 { 522 struct fdt_attach_args * const faa = aux; 523 524 return of_compatible_match(faa->faa_phandle, compat_data); 525 } 526 527 static void 528 sun20i_d1_ccu_attach(device_t parent, device_t self, void *aux) 529 { 530 struct sunxi_ccu_softc * const sc = device_private(self); 531 struct fdt_attach_args * const faa = aux; 532 533 sc->sc_dev = self; 534 sc->sc_phandle = faa->faa_phandle; 535 sc->sc_bst = faa->faa_bst; 536 537 sc->sc_resets = sun20i_d1_ccu_resets; 538 sc->sc_nresets = __arraycount(sun20i_d1_ccu_resets); 539 540 sc->sc_clks = sun20i_d1_ccu_clks; 541 sc->sc_nclks = __arraycount(sun20i_d1_ccu_clks); 542 543 if (sunxi_ccu_attach(sc) != 0) 544 return; 545 546 aprint_naive("\n"); 547 aprint_normal(": D1 CCU\n"); 548 549 sunxi_ccu_print(sc); 550 } 551
Indexes created Thu Oct 02 14:10:14 GMT 2025