mca_machdep.c revision 1.1
1 /* $NetBSD: mca_machdep.c,v 1.1 2007/12/17 19:09:40 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * Copyright (c) 1996-1999 Scott D. Telford. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Scott Telford <s.telford (at) ed.ac.uk> and Jaromir Dolecek 10 * <jdolecek (at) NetBSD.org>. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Machine-specific functions for MCA autoconfiguration. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: mca_machdep.c,v 1.1 2007/12/17 19:09:40 garbled Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/systm.h> 53 #include <sys/syslog.h> 54 #include <sys/time.h> 55 #include <sys/kernel.h> 56 57 #include <powerpc/pio.h> 58 #define _POWERPC_BUS_DMA_PRIVATE 59 #include <machine/bus.h> 60 61 #include <dev/mca/mcavar.h> 62 #include <dev/mca/mcareg.h> 63 64 #include "opt_mcaverbose.h" 65 66 #ifdef UNUSED 67 static void _mca_bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, 68 bus_addr_t, bus_size_t, int); 69 #endif 70 71 /* 72 * For now, we use MCA DMA to 0-16M always. Some IBM PS/2 have 32bit MCA bus, 73 * but majority of them have 24bit only. 74 */ 75 #define MCA_DMA_BOUNCE_THRESHOLD (16 * 1024 * 1024) 76 77 /* Updated in mca_busprobe() if appropriate. */ 78 int MCA_system = 0; 79 80 //static bus_space_handle_t dmaiot, dmacmdh, dmaexech; 81 82 #define MAX_SLAVE_CHANNELS 8 83 #define MAX_DMA_CHANNELS 16 84 85 #define INIT_DMA_CHN_BITMASK() (0xFFFFFFFF << (32 - MAX_DMA_CHANS)) 86 #define INIT_SLAVE_CHN_BITMASK(slaves) (0xFFFFFFFF << (32 - (slaves)) 87 88 #define DMA_AVAIL(chn, bitmask) ((bitmask) & (1 << (31 - (chn)))) 89 #define DMA_ALLOC(chn, bitmask) ((bitmask) &= ~(1 << (31 - (chn)))) 90 #define DMA_FREE(chn, bitmask) ((bitmask) |= (1 << (31 - (chn)))) 91 92 /* 93 * MCA DMA controller commands. The exact sense of individual bits 94 * are from Tymm Twillman <tymm (at) computer.org>, who worked on Linux MCA DMA 95 * support. 96 */ 97 #define DMACMD_SET_IO 0x00 /* set port (16bit) for i/o transfer */ 98 #define DMACMD_SET_ADDR 0x20 /* set addr (24bit) for i/o transfer */ 99 #define DMACMD_GET_ADDR 0x30 /* get addr (24bit) for i/o transfer */ 100 #define DMACMD_SET_CNT 0x40 /* set memory size for DMA (16b) */ 101 #define DMACMD_GET_CNT 0x50 /* get count of remaining bytes in DMA*/ 102 #define DMACMD_GET_STATUS 0x60 /* ?? */ 103 #define DMACMD_SET_MODE 0x70 /* set DMA mode */ 104 # define DMACMD_MODE_XFER 0x04 /* do transfer, read by default */ 105 # define DMACMD_MODE_READ 0x08 /* read transfer */ 106 # define DMACMD_MODE_WRITE 0x00 /* write transfer */ 107 # define DMACMD_MODE_IOPORT 0x01 /* DMA from/to IO register */ 108 # define DMACMD_MODE_16BIT 0x40 /* 16bit transfers (default 8bit) */ 109 #define DMACMD_SET_ARBUS 0x80 /* ?? */ 110 #define DMACMD_MASK 0x90 /* command mask */ 111 #define DMACMD_RESET_MASK 0xA0 /* reset */ 112 #define DMACMD_MASTER_CLEAR 0xD0 /* ?? */ 113 114 const struct evcnt * 115 mca_intr_evcnt(mca_chipset_tag_t ic, int irq) 116 { 117 /* XXX for now, no evcnt parent reported */ 118 return NULL; 119 } 120 121 /* 122 * Map the MCA DMA controller registers. 123 */ 124 void 125 mca_attach_hook(struct device *parent, struct device *self, 126 struct mcabus_attach_args *mba) 127 { 128 #if 0 129 dmaiot = mba->mba_iot; 130 131 if (bus_space_map(dmaiot, DMA_CMD, 1, 0, &dmacmdh) 132 || bus_space_map(dmaiot, DMA_EXEC, 1, 0, &dmaexech)) 133 panic("mca: couldn't map DMA registers"); 134 #endif 135 } 136 137 /* 138 * Read value of MCA POS register "reg" in slot "slot". 139 */ 140 141 int 142 mca_conf_read(mca_chipset_tag_t mc, int slot, int reg) 143 { 144 int data; 145 146 slot &= 15; /* slot must be in range 0-15 */ 147 data = inb(RS6000_BUS_SPACE_IO + MCA_POS_REG(reg) + (slot<<16)); 148 return data; 149 } 150 151 152 /* 153 * Write "data" to MCA POS register "reg" in slot "slot". 154 */ 155 156 void 157 mca_conf_write(mca_chipset_tag_t mc, int slot, int reg, int data) 158 { 159 slot &= 15; /* slot must be in range 0-15 */ 160 outb(RS6000_BUS_SPACE_IO + MCA_POS_REG(reg) + (slot<<16), data); 161 } 162 163 164 void * 165 mca_intr_establish(mca_chipset_tag_t mc, mca_intr_handle_t ih, 166 int level, int (*func)(void *), void *arg) 167 { 168 if (ih == 0 || ih >= ICU_LEN) 169 panic("mca_intr_establish: bogus handle 0x%x", ih); 170 171 /* MCA interrupts are always level-triggered */ 172 return intr_establish(ih, IST_LEVEL, level, func, arg); 173 } 174 175 void 176 mca_intr_disestablish(mca_chipset_tag_t mc, void *cookie) 177 { 178 intr_disestablish(cookie); 179 } 180 181 182 /* 183 * Handle a NMI. 184 * return true to panic system, false to ignore. 185 */ 186 int 187 mca_nmi(void) 188 { 189 /* 190 * PS/2 MCA devices can generate NMIs - we can find out which 191 * slot generated it from the POS registers. 192 */ 193 194 int slot, mcanmi=0; 195 196 /* if there is no MCA bus, call x86_nmi() */ 197 if (!MCA_system) 198 goto out; 199 200 /* ensure motherboard setup is disabled */ 201 outb(MCA_MB_SETUP_REG, 0xff); 202 203 /* find if an MCA slot has the CHCK bit asserted (low) in POS 5 */ 204 for(slot=0; slot<MCA_MAX_SLOTS; slot++) { 205 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET); 206 if ((inb(MCA_POS_REG(5)) & MCA_POS5_CHCK) == 0) { 207 mcanmi = 1; 208 /* find if CHCK status is available in POS 6/7 */ 209 if((inb(MCA_POS_REG(5)) & MCA_POS5_CHCK_STAT) == 0) 210 log(LOG_CRIT, "MCA NMI: slot %d, POS6=0x%02x, POS7=0x%02x\n", 211 slot+1, inb(MCA_POS_REG(6)), 212 inb(MCA_POS_REG(7))); 213 else 214 log(LOG_CRIT, "MCA NMI: slot %d\n", slot+1); 215 } 216 } 217 outb(MCA_ADAP_SETUP_REG, 0); 218 219 out: 220 if (!mcanmi) { 221 /* no CHCK bits asserted, assume ISA NMI */ 222 //return (x86_nmi()); 223 return 0; 224 } else 225 return(0); 226 } 227 228 /* 229 * Realistically, we should probe for the presence of an MCA bus here, and 230 * return a reasonable value. However, this port is never expected to run 231 * on anything other than MCA, so rather than write a bunch of complex code 232 * to find that we indeed have a bus, lets just assume we do. 233 */ 234 void 235 mca_busprobe(void) 236 { 237 MCA_system = 1; 238 } 239 240 #define PORT_DISKLED 0x92 241 #define DISKLED_ON 0x40 242 243 /* 244 * Light disk busy LED on IBM PS/2. 245 */ 246 void 247 mca_disk_busy(void) 248 { 249 outb(PORT_DISKLED, inb(PORT_DISKLED) | DISKLED_ON); 250 } 251 252 /* 253 * Turn off disk LED on IBM PS/2. 254 */ 255 void 256 mca_disk_unbusy(void) 257 { 258 outb(PORT_DISKLED, inb(PORT_DISKLED) & ~DISKLED_ON); 259 } 260 261 /* 262 * -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- 263 * MCA DMA specific stuff. We use ISA routines for bulk of the work, 264 * since MCA shares much of the charasteristics with it. We just hook 265 * the DMA channel initialization and kick MCA DMA controller appropriately. 266 * -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- 267 */ 268 269 #ifdef NOTYET 270 /* 271 * Synchronize a MCA DMA map. 272 */ 273 static void 274 _mca_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 275 bus_size_t len, int ops) 276 { 277 struct rs6000_dma_cookie *cookie; 278 bus_addr_t phys; 279 bus_size_t cnt; 280 int dmach, mode; 281 282 _bus_dmamap_sync(t, map, offset, len, ops); 283 284 /* 285 * Don't do anything if not using the DMA controller. 286 */ 287 if ((map->_dm_flags & _MCABUS_DMA_USEDMACTRL) == 0) 288 return; 289 290 /* 291 * Don't do anything if not PRE* operation, allow only 292 * one of PREREAD and PREWRITE. 293 */ 294 if (ops != BUS_DMASYNC_PREREAD && ops != BUS_DMASYNC_PREWRITE) 295 return; 296 297 cookie = (struct rs6000_dma_cookie *)map->_dm_cookie; 298 dmach = (cookie->id_flags & 0xf0) >> 4; 299 300 phys = map->dm_segs[0].ds_addr; 301 cnt = map->dm_segs[0].ds_len; 302 303 mode = DMACMD_MODE_XFER; 304 mode |= (ops == BUS_DMASYNC_PREREAD) 305 ? DMACMD_MODE_READ : DMACMD_MODE_WRITE; 306 if (map->_dm_flags & MCABUS_DMA_IOPORT) 307 mode |= DMACMD_MODE_IOPORT; 308 309 /* Use 16bit DMA if requested */ 310 if (map->_dm_flags & MCABUS_DMA_16BIT) { 311 #ifdef DIAGNOSTIC 312 if ((cnt % 2) != 0) { 313 panic("_mca_bus_dmamap_sync: 16bit DMA and cnt %lu odd", 314 cnt); 315 } 316 #endif 317 mode |= DMACMD_MODE_16BIT; 318 cnt /= 2; 319 } 320 321 /* 322 * Initialize the MCA DMA controller appropriately. The exact 323 * sequence to setup the controller is taken from Minix. 324 */ 325 326 /* Disable access to DMA channel. */ 327 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_MASK | dmach); 328 329 /* Set the transfer mode. */ 330 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_MODE | dmach); 331 bus_space_write_1(dmaiot, dmaexech, 0, mode); 332 333 /* Set the address byte pointer. */ 334 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_ADDR | dmach); 335 /* address bits 0..7 */ 336 bus_space_write_1(dmaiot, dmaexech, 0, (phys >> 0) & 0xff); 337 /* address bits 8..15 */ 338 bus_space_write_1(dmaiot, dmaexech, 0, (phys >> 8) & 0xff); 339 /* address bits 16..23 */ 340 bus_space_write_1(dmaiot, dmaexech, 0, (phys >> 16) & 0xff); 341 342 /* Set the count byte pointer */ 343 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_CNT | dmach); 344 /* count bits 0..7 */ 345 bus_space_write_1(dmaiot, dmaexech, 0, ((cnt - 1) >> 0) & 0xff); 346 /* count bits 8..15 */ 347 bus_space_write_1(dmaiot, dmaexech, 0, ((cnt - 1) >> 8) & 0xff); 348 349 /* Enable access to DMA channel. */ 350 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_RESET_MASK | dmach); 351 } 352 #endif 353 354 /* 355 * Allocate a DMA map, and set up DMA channel. 356 */ 357 int 358 mca_dmamap_create(bus_dma_tag_t t, bus_size_t size, int flags, 359 bus_dmamap_t *dmamp, int dmach) 360 { 361 #if 0 362 int error; 363 struct rs6000_dma_cookie *cookie; 364 365 #ifdef DEBUG 366 /* Sanity check */ 367 if (dmach < 0 || dmach >= MAX_DMA_CHANNELS) { 368 printf("mcadma_create: invalid DMA channel %d\n", 369 dmach); 370 return (EINVAL); 371 } 372 373 if (size > 65536) { 374 panic("mca_dmamap_create: dmamap sz %ld > 65536", 375 (long) size); 376 } 377 #endif 378 379 /* 380 * MCA DMA transfer can be maximum 65536 bytes long and must 381 * be in one chunk. No specific boundary constraints are present. 382 */ 383 if ((error = _bus_dmamap_create(t, size, 1, 65536, 0, flags, dmamp))) 384 return (error); 385 386 cookie = (struct rs6000_dma_cookie *) (*dmamp)->_dm_cookie; 387 388 if (cookie == NULL) { 389 /* 390 * Allocate our cookie if not yet done. 391 */ 392 cookie = malloc(sizeof(struct rs6000_dma_cookie), M_DMAMAP, 393 ((flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 394 if (cookie == NULL) { 395 396 return ENOMEM; 397 } 398 (*dmamp)->_dm_cookie = cookie; 399 } 400 401 402 /* Encode DMA channel */ 403 cookie->id_flags &= 0x0f; 404 cookie->id_flags |= dmach << 4; 405 406 /* Mark the dmamap as using DMA controller. Some devices 407 * drive DMA themselves, and don't need the MCA DMA controller. 408 * To distinguish the two, use a flag for dmamaps which use the DMA 409 * controller. 410 */ 411 (*dmamp)->_dm_flags |= _MCABUS_DMA_USEDMACTRL; 412 #endif 413 return (0); 414 } 415 416 /* 417 * Set I/O port for DMA. Implemented separately from _mca_bus_dmamap_sync() 418 * so that it's available for one-shot setup. 419 */ 420 void 421 mca_dma_set_ioport(int dma, uint16_t port) 422 { 423 #if 0 424 /* Disable access to dma channel. */ 425 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_MASK | dma); 426 427 /* Set I/O port to use for DMA */ 428 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_IO | dma); 429 bus_space_write_1(dmaiot, dmaexech, 0, port & 0xff); 430 bus_space_write_1(dmaiot, dmaexech, 0, (port >> 8) & 0xff); 431 432 /* Enable access to DMA channel. */ 433 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_RESET_MASK | dma); 434 #endif 435 } 436
Indexes created Tue Sep 30 20:09:53 GMT 2025